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MPS430 cordicPWM sine wave generator

Started by miso December 13, 2012
"John Larkin" <jlarkin@highlandtechnology.com> wrote:

For dirty PWM sinewave, CORDIC is merely academic exercise.

> Even at 24 bits, I'd expect that lookup and interpolation would be > pretty good, and certainly fast. Use 32-bit values in the lookup > table. Sine isn't that radical a curve.
The accuracy of interpolation of the Nth order with K nodes is O(1/K^(N+1)) The 16 bit accurate linear interpolation of sine requires LUT with 512 entries over a quarter of period. For 24 bit accuracy with linear interpolation, the LUT would be 8K entries; which is not very comfortable with FPGA. Cubic interpolation should perform to 24 bit accuracy with LUT of 512 entries; for the cost of increased complexity. Here is the elegant way of generating precise sine and cosine waveforms with minimum math: http://www.claysturner.com/dsp/digital_resonators.pdf Vladimir Vassilevsky DSP and Mixed Signal Consultant www.abvolt.com
On Fri, 14 Dec 2012 14:21:59 -0800, miso <miso@sushi.com> wrote:

>You simply don't get it. You can change the frequency on the fly with >the cordic without changing the sample rate. You simply change the phase >step.
A DDS phase accumulator and a sine lookup table will do that. We do that on a bunch of products: for example, an FPGA with a 48 bit DDS accumulator driving a sine table with interpolation, always clocked at, say, 128 MHz. That's simple and really fast. I think Cordic pre-dates DDS. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On Fri, 14 Dec 2012 07:16:55 -0500, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Wed, 12 Dec 2012 23:46:18 -0800, the renowned miso <miso@sushi.com> >wrote: > >>The eval kit is a whole $4.30 including shipping, and it comes 2nd day >>Fedex. >>> http://e2e.ti.com/group/microcontrollerprojects/m/msp430microcontrollerprojects/609573.aspx >> >>The person coded the cordic, and then implemented the sine wave with PWM. >> > >Well, it's an interesting exercise.. it's done in FPGAs when you need >a lot of time resolution, but for a 64-point sine wave with fixed >phase, all you need is 16 words of lookup table.
Sixteen very small words.
On Fri, 14 Dec 2012 16:47:27 -0600, "Vladimir Vassilevsky"
<nospam@nowhere.com> wrote:

> >"John Larkin" <jlarkin@highlandtechnology.com> wrote: > >For dirty PWM sinewave, CORDIC is merely academic exercise. > >> Even at 24 bits, I'd expect that lookup and interpolation would be >> pretty good, and certainly fast. Use 32-bit values in the lookup >> table. Sine isn't that radical a curve. > >The accuracy of interpolation of the Nth order with K nodes is O(1/K^(N+1)) >The 16 bit accurate linear interpolation of sine requires LUT with 512 >entries over a quarter of period. >For 24 bit accuracy with linear interpolation, the LUT would be 8K entries; >which is not very comfortable with FPGA.
An 8K table with 16 or 24 bits per entry is only 131 or 196 kbits, and even modest FPGAs have a lot more block ram than that. This one has 8 channels, each with a 4Kx16 lookup table, using a modest FPGA with ram to spare. http://www.highlandtechnology.com/DSS/V346DS.shtml Each channel has a 48 bit phase accumulator and interpolation. We use 16 bit dacs clocked at 128 MHz.
>Cubic interpolation should perform to 24 bit accuracy with LUT of 512 >entries; for the cost of increased complexity. > >Here is the elegant way of generating precise sine and cosine waveforms with >minimum math: > >http://www.claysturner.com/dsp/digital_resonators.pdf
OK, but a general DDS can't use memory of previous points to compute the next point. We like the freedom to do FM, or chirps, or jump instantly to any phase angle. A lookup table is static. Many FPGA rams are dual-ported, which makes the interpolation even easier. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
On 2012-12-14, miso <miso@sushi.com> wrote:
> You simply don't get it. You can change the frequency on the fly with > the cordic without changing the sample rate. You simply change the phase > step.
That doesn't make cordic special, the same can be, and is done with other DDS methods. -- &#9858;&#9859; 100% natural --- news://freenews.netfront.net/ - complaints: news@netfront.net ---
On 12/15/2012 1:06 AM, Jasen Betts wrote:
> On 2012-12-14, miso <miso@sushi.com> wrote: >> You simply don't get it. You can change the frequency on the fly with >> the cordic without changing the sample rate. You simply change the phase >> step. > > That doesn't make cordic special, the same can be, and is done with other DDS > methods. > >
The cordic is easily the most flexible method for transcendental function computations. I've been through the math library at Stanford looking for easy algorithms to do such computation. There are faster schemes, but the cordic is the easiest. It is an indispensable tool. It is way more valuable than just sine/cosine computation. It was the heart of many m-ary DPSK demod schemes we integrated. You can be sloppy on board level designs, but you need to be efficient in chips, especially mixed-mode where the transistors are not fine geometry.
On Fri, 14 Dec 2012 15:17:53 -0800, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>On Fri, 14 Dec 2012 14:21:59 -0800, miso <miso@sushi.com> wrote: > >>You simply don't get it. You can change the frequency on the fly with=20 >>the cordic without changing the sample rate. You simply change the =
phase=20
>>step. > >A DDS phase accumulator and a sine lookup table will do that. We do >that on a bunch of products: for example, an FPGA with a 48 bit DDS >accumulator driving a sine table with interpolation, always clocked >at, say, 128 MHz. That's simple and really fast. > >I think Cordic pre-dates DDS.
By a bit, it predates the old 8087 math coprocessor. ?-)
On Sun, 16 Dec 2012 12:29:19 -0800, the renowned josephkk
<joseph_barrett@sbcglobal.net> wrote:

>On Fri, 14 Dec 2012 15:17:53 -0800, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>On Fri, 14 Dec 2012 14:21:59 -0800, miso <miso@sushi.com> wrote: >> >>>You simply don't get it. You can change the frequency on the fly with >>>the cordic without changing the sample rate. You simply change the phase >>>step. >> >>A DDS phase accumulator and a sine lookup table will do that. We do >>that on a bunch of products: for example, an FPGA with a 48 bit DDS >>accumulator driving a sine table with interpolation, always clocked >>at, say, 128 MHz. That's simple and really fast. >> >>I think Cordic pre-dates DDS. > >By a bit, it predates the old 8087 math coprocessor. > >?-)
By a lot, it (almost) predates the IC. Here is the original paper (1959):- http://diwww.epfl.ch/w3lap/courses/comparith/Papers/3-Volder_CORDIC.pdf It's one of those inventions that changes the world. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
On Sun, 16 Dec 2012 15:54:04 -0500, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Sun, 16 Dec 2012 12:29:19 -0800, the renowned josephkk ><joseph_barrett@sbcglobal.net> wrote: > >>On Fri, 14 Dec 2012 15:17:53 -0800, John Larkin >><jlarkin@highlandtechnology.com> wrote: >> >>>On Fri, 14 Dec 2012 14:21:59 -0800, miso <miso@sushi.com> wrote: >>> >>>>You simply don't get it. You can change the frequency on the fly with=
=20
>>>>the cordic without changing the sample rate. You simply change the =
phase=20
>>>>step. >>> >>>A DDS phase accumulator and a sine lookup table will do that. We do >>>that on a bunch of products: for example, an FPGA with a 48 bit DDS >>>accumulator driving a sine table with interpolation, always clocked >>>at, say, 128 MHz. That's simple and really fast. >>> >>>I think Cordic pre-dates DDS. >> >>By a bit, it predates the old 8087 math coprocessor. >> >>?-) > >By a lot, it (almost) predates the IC.=20 > >Here is the original paper (1959):- > >http://diwww.epfl.ch/w3lap/courses/comparith/Papers/3-Volder_CORDIC.pdf > >It's one of those inventions that changes the world.=20 > > >Best regards,=20 >Spehro Pefhany
Somehow that does not surprise me. ?-)