Reply by Simon S Aysdie●November 16, 20212021-11-16
On Wednesday, November 10, 2021 at 4:56:33 AM UTC-8, Chris B wrote:
> "Lasse Langwadt Christensen" <lang...@fonz.dk> schrieb im Newsbeitrag
> news:70a19dca-ef5a-4376...@googlegroups.com...
> > mandag den 8. november 2021 kl. 18.44.30 UTC+1 skrev
> > jla...@highlandsniptechnology.com:
> >> I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4
> >> dielectrics.
> >>
> >> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to
> >> ground some pins. The grounded pins would hit an inner ground plane
> >> flood-over, namely no thermals. Clearly annular rings on the pad stack
> >> wouldn't matter on those layers; it's all copper.
> >>
> >> But where other pins aren't grounded, I want miminal loss of copper on
> >> the ground plane. So I'd prefer no annular ring, just a plated hole
> >> with the voltage clearance between the drill and the circular cutout
> >> of the ground pour.
> >>
> >> Does that sound OK?
> >
> > technical term, "non-functional pad"
> >
> > https://www.dfrsolutions.com/hubfs/DfR_Solutions_Website/Resources-Archived/White-Papers/Reliability/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf
> >
> >
> >
> But removing the pads usually does not give you more copper for the plane;
> the area of the annular ring on inner layers is also needed for drill
> "wander" and positional tolerances (unless your inner pads were large to
> begin with)
Exactly. As you say, if they weren't oversized then what I'll call the breakout rule won't allow the GND copper to fill in anyway.
Reply by ●November 11, 20212021-11-11
On Thu, 11 Nov 2021 09:26:32 -0000 (UTC), Rhydian
<news@rblack01.plus.com> wrote:
>On Wed, 10 Nov 2021 10:59:42 -0800, John Larkin wrote:
>
>[snip]
>
>> I want some software that will predict sheet resistance (electrical or
>> thermal, they are equivalent) for simple arbitrary shapes.
>>
>> Does anybody have suggestions? I could write one, but the graphical
>> entry is the hard part. ATLC uses a bitmap from Paint, which I guess I
>> could figure out.
>>
>> When I was in school, some time ago, we cut teledeltos paper, conductive
>> stuff, and measured it.
>
>This is one I use occasionally:
>
>https://www.softpedia.com/get/Science-CAD/Copper-Plane-Current-
>Analysis.shtml
>
>Similar idea to ATLC2, input is a bitmap. I had a similar design,
>multiple high-current connector pins coming onto a board, it helped a lot
>with optimising the layout.
That looks cool. The screen shots are silly; they don't show what
results look like.
ATLC makes beautiful field plots.
https://www.dropbox.com/s/xavwrdzwz4y8iep/Edge_alone_4.jpg?raw=1https://www.dropbox.com/s/1zb71vy9g576c6y/E-field.jpg?raw=1
My customer just told us that they will never run more than 2 amps per
pin pair, down from 5, so our thermal situation is vastly better.
Still, the sheet resistance thing keeps coming up. I'll try CPCA.
--
Father Brown's figure remained quite dark and still;
but in that instant he had lost his head. His head was
always most valuable when he had lost it.
Reply by Chris B●November 11, 20212021-11-11
"Lasse Langwadt Christensen" <langwadt@fonz.dk> schrieb im Newsbeitrag
news:ec96a960-a342-48aa-8096-245d571e34a6n@googlegroups.com...
> onsdag den 10. november 2021 kl. 13.56.33 UTC+1 skrev Chris B:
>> "Lasse Langwadt Christensen" <lang...@fonz.dk> schrieb im Newsbeitrag
>> news:70a19dca-ef5a-4376...@googlegroups.com...
>> > mandag den 8. november 2021 kl. 18.44.30 UTC+1 skrev
>> > jla...@highlandsniptechnology.com:
>> >> I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4
>> >> dielectrics.
>> >>
>> >> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to
>> >> ground some pins. The grounded pins would hit an inner ground plane
>> >> flood-over, namely no thermals. Clearly annular rings on the pad stack
>> >> wouldn't matter on those layers; it's all copper.
>> >>
>> >> But where other pins aren't grounded, I want miminal loss of copper on
>> >> the ground plane. So I'd prefer no annular ring, just a plated hole
>> >> with the voltage clearance between the drill and the circular cutout
>> >> of the ground pour.
>> >>
>> >> Does that sound OK?
>> >
>> > technical term, "non-functional pad"
>> >
>> > https://www.dfrsolutions.com/hubfs/DfR_Solutions_Website/Resources-Archived/White-Papers/Reliability/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf
>> >
>> >
>> >
>> But removing the pads usually does not give you more copper for the
>> plane;
>> the area of the annular ring on inner layers is also needed for drill
>> "wander" and positional tolerances (unless your inner pads were large to
>> begin with)
>
> you don't get any extra space if you remove them in postprocessing,
> but you might if you design for it
>
>
>
>
Even when you design for it, it doesn't give you more room. Top/bottom pads
are for soldering, inner pads are for tolerance only. Drilling has e.g.
0.1mm tolerance, so the plated-through hole could be at the same area an
annular ring of 0.1mm width would be. Your clearance needs to be measured
from drill+tolerance, so you win nothing. Most PCB fabricators specify min
annular ring equal to drill tolerance [1]; most CAD systems get the DRC
wrong...
I'm in board fabrication doing design check and have to tell customers
exactly this about once or twice per month.
[1] for thick copper >35um, ae rule of thumb for inner layers is min annular
= tolerance + 2x (thickness-35um)
Chris
Reply by Phil Hobbs●November 11, 20212021-11-11
John Larkin wrote:
> On Wed, 10 Nov 2021 10:06:34 -0800 (PST), Lasse Langwadt Christensen
> <langwadt@fonz.dk> wrote:
>
>> onsdag den 10. november 2021 kl. 13.56.33 UTC+1 skrev Chris B:
>>> "Lasse Langwadt Christensen" <lang...@fonz.dk> schrieb im Newsbeitrag
>>> news:70a19dca-ef5a-4376...@googlegroups.com...
>>>> mandag den 8. november 2021 kl. 18.44.30 UTC+1 skrev
>>>> jla...@highlandsniptechnology.com:
>>>>> I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4
>>>>> dielectrics.
>>>>>
>>>>> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to
>>>>> ground some pins. The grounded pins would hit an inner ground plane
>>>>> flood-over, namely no thermals. Clearly annular rings on the pad stack
>>>>> wouldn't matter on those layers; it's all copper.
>>>>>
>>>>> But where other pins aren't grounded, I want miminal loss of copper on
>>>>> the ground plane. So I'd prefer no annular ring, just a plated hole
>>>>> with the voltage clearance between the drill and the circular cutout
>>>>> of the ground pour.
>>>>>
>>>>> Does that sound OK?
>>>>
>>>> technical term, "non-functional pad"
>>>>
>>>> https://www.dfrsolutions.com/hubfs/DfR_Solutions_Website/Resources-Archived/White-Papers/Reliability/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf
>>>>
>>>>
>>>>
>>> But removing the pads usually does not give you more copper for the plane;
>>> the area of the annular ring on inner layers is also needed for drill
>>> "wander" and positional tolerances (unless your inner pads were large to
>>> begin with)
>>
>> you don't get any extra space if you remove them in postprocessing,
>> but you might if you design for it
>>
>>
>>
>
> I want some software that will predict sheet resistance (electrical or
> thermal, they are equivalent) for simple arbitrary shapes.
>
> Does anybody have suggestions? I could write one, but the graphical
> entry is the hard part. ATLC uses a bitmap from Paint, which I guess I
> could figure out.
>
> When I was in school, some time ago, we cut teledeltos paper,
> conductive stuff, and measured it.
>
Writing bumpfiles is super easy. There's little reason to write anything
else, actually--Image Magick will convert them to whatever format you want.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.nethttp://hobbs-eo.com
Reply by Rhydian●November 11, 20212021-11-11
On Wed, 10 Nov 2021 10:59:42 -0800, John Larkin wrote:
[snip]
> I want some software that will predict sheet resistance (electrical or
> thermal, they are equivalent) for simple arbitrary shapes.
>
> Does anybody have suggestions? I could write one, but the graphical
> entry is the hard part. ATLC uses a bitmap from Paint, which I guess I
> could figure out.
>
> When I was in school, some time ago, we cut teledeltos paper, conductive
> stuff, and measured it.
This is one I use occasionally:
https://www.softpedia.com/get/Science-CAD/Copper-Plane-Current-
Analysis.shtml
Similar idea to ATLC2, input is a bitmap. I had a similar design,
multiple high-current connector pins coming onto a board, it helped a lot
with optimising the layout.
Reply by John Larkin●November 10, 20212021-11-10
On Wed, 10 Nov 2021 10:06:34 -0800 (PST), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:
>onsdag den 10. november 2021 kl. 13.56.33 UTC+1 skrev Chris B:
>> "Lasse Langwadt Christensen" <lang...@fonz.dk> schrieb im Newsbeitrag
>> news:70a19dca-ef5a-4376...@googlegroups.com...
>> > mandag den 8. november 2021 kl. 18.44.30 UTC+1 skrev
>> > jla...@highlandsniptechnology.com:
>> >> I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4
>> >> dielectrics.
>> >>
>> >> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to
>> >> ground some pins. The grounded pins would hit an inner ground plane
>> >> flood-over, namely no thermals. Clearly annular rings on the pad stack
>> >> wouldn't matter on those layers; it's all copper.
>> >>
>> >> But where other pins aren't grounded, I want miminal loss of copper on
>> >> the ground plane. So I'd prefer no annular ring, just a plated hole
>> >> with the voltage clearance between the drill and the circular cutout
>> >> of the ground pour.
>> >>
>> >> Does that sound OK?
>> >
>> > technical term, "non-functional pad"
>> >
>> > https://www.dfrsolutions.com/hubfs/DfR_Solutions_Website/Resources-Archived/White-Papers/Reliability/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf
>> >
>> >
>> >
>> But removing the pads usually does not give you more copper for the plane;
>> the area of the annular ring on inner layers is also needed for drill
>> "wander" and positional tolerances (unless your inner pads were large to
>> begin with)
>
>you don't get any extra space if you remove them in postprocessing,
>but you might if you design for it
>
>
>
I want some software that will predict sheet resistance (electrical or
thermal, they are equivalent) for simple arbitrary shapes.
Does anybody have suggestions? I could write one, but the graphical
entry is the hard part. ATLC uses a bitmap from Paint, which I guess I
could figure out.
When I was in school, some time ago, we cut teledeltos paper,
conductive stuff, and measured it.
--
If a man will begin with certainties, he shall end with doubts,
but if he will be content to begin with doubts he shall end in certainties.
Francis Bacon
Reply by Lasse Langwadt Christensen●November 10, 20212021-11-10
onsdag den 10. november 2021 kl. 13.56.33 UTC+1 skrev Chris B:
> "Lasse Langwadt Christensen" <lang...@fonz.dk> schrieb im Newsbeitrag
> news:70a19dca-ef5a-4376...@googlegroups.com...
> > mandag den 8. november 2021 kl. 18.44.30 UTC+1 skrev
> > jla...@highlandsniptechnology.com:
> >> I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4
> >> dielectrics.
> >>
> >> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to
> >> ground some pins. The grounded pins would hit an inner ground plane
> >> flood-over, namely no thermals. Clearly annular rings on the pad stack
> >> wouldn't matter on those layers; it's all copper.
> >>
> >> But where other pins aren't grounded, I want miminal loss of copper on
> >> the ground plane. So I'd prefer no annular ring, just a plated hole
> >> with the voltage clearance between the drill and the circular cutout
> >> of the ground pour.
> >>
> >> Does that sound OK?
> >
> > technical term, "non-functional pad"
> >
> > https://www.dfrsolutions.com/hubfs/DfR_Solutions_Website/Resources-Archived/White-Papers/Reliability/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf
> >
> >
> >
> But removing the pads usually does not give you more copper for the plane;
> the area of the annular ring on inner layers is also needed for drill
> "wander" and positional tolerances (unless your inner pads were large to
> begin with)
you don't get any extra space if you remove them in postprocessing,
but you might if you design for it
Reply by Chris B●November 10, 20212021-11-10
"Lasse Langwadt Christensen" <langwadt@fonz.dk> schrieb im Newsbeitrag
news:70a19dca-ef5a-4376-92b0-965bae5a6324n@googlegroups.com...
> mandag den 8. november 2021 kl. 18.44.30 UTC+1 skrev
> jla...@highlandsniptechnology.com:
>> I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4
>> dielectrics.
>>
>> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to
>> ground some pins. The grounded pins would hit an inner ground plane
>> flood-over, namely no thermals. Clearly annular rings on the pad stack
>> wouldn't matter on those layers; it's all copper.
>>
>> But where other pins aren't grounded, I want miminal loss of copper on
>> the ground plane. So I'd prefer no annular ring, just a plated hole
>> with the voltage clearance between the drill and the circular cutout
>> of the ground pour.
>>
>> Does that sound OK?
>
> technical term, "non-functional pad"
>
> https://www.dfrsolutions.com/hubfs/DfR_Solutions_Website/Resources-Archived/White-Papers/Reliability/Non-Functional-Pads-Should-they-Stay-or-Should-they-Go.pdf
>
>
>
But removing the pads usually does not give you more copper for the plane;
the area of the annular ring on inner layers is also needed for drill
"wander" and positional tolerances (unless your inner pads were large to
begin with)
Chris
Reply by legg●November 9, 20212021-11-09
On Tue, 9 Nov 2021 13:00:17 -0800 (PST), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:
>tirsdag den 9. november 2021 kl. 21.44.35 UTC+1 skrev legg:
>> On Tue, 9 Nov 2021 09:23:16 -0800 (PST), Lasse Langwadt Christensen
>> <lang...@fonz.dk> wrote:
>>
>> >tirsdag den 9. november 2021 kl. 15.06.28 UTC+1 skrev legg:
>> >> On Tue, 9 Nov 2021 08:49:37 -0000 (UTC),
>> >> DecadentLinux...@decadence.org wrote:
>> >>
>> >> >legg <le...@nospam.magma.ca> wrote in
>> >> >news:0r3kogdjcqndrm0a9...@4ax.com:
>> >> >
>> >> >> It's not something that you ignore to save cost on drill bits
>> >> >> at fab.
>> >> >>
>> >> >
>> >> > No layout we ever did had any concerns over hole counts or sizes much
>> >> >less their cost during getting the job done.
>> >> >
>> >> > The boards I have seen even from cheap quick fabs are pretty dang
>> >> >tight, and the price points don't mention drill bits, so I am guessing
>> >> >the fab houses are better at poking them in instead of just diving and
>> >> >driving and are getting better tool life. Doesn't FR-4 drill easier if
>> >> >it is hot? Or it is glass fibers either way, so doesn't matter I
>> >> >guess... wear is inevitable and quick.
>> >> I've yet to see a fab house claim that - 'we generally prefer to
>> >> remove (annular rings)' in their documentation, or to offer price
>> >> points on this as an option.
>> >>
>> >
>> >5 minutes of googling find several pcb manufacturers that say removing
>> >non-functional pads on inner layers are standard procedure in their cam processing
>> >
>> >
>> Well, perhaps I'm out of date. Of the first 24 PCB mfring links in
>> my portable's bookmarks, only two were still in business. No annular
>> ring references on their site. Ditto with such vendors as JLCPCB.
>>
>> Googling 'removing non-functional pads on inner layers' got me
>> group discussions or software vendors (on a single html page),
>> neither of which are very reliable sources for hard-nosed info
>> on pcb fab.
>>
>> Would probably have had better luck in Mandarin or Cantonese. . .
>> Perhaps you could supply links to the info you found so easily.
>> Not sure I'd add them to my bookmarks, but they would serve
>> better than dead links.
>>
>> I have a 30+years library in paper and electronic format that
>> I'd usually consult, but can't reach before Thursday PM.
>> In real designs, putting signal traces through power connectors,
>> or vice versa, is just a symptom of bad planning.
>
>https://www.eurocircuits.com/frontend-data-preparation/
>https://www.4pcb.com/pcb-cam-based-quoting/
>https://pcbprime.com/pcb-tips/cam-tooling-guidelines/
>
It appears that all of these manufacturers anticipate board
quantities to be too small to justify set-up charges and
dedicated production runs. . . .similar to JLCPCB or DKRed.
Board designs for volume mfring are normally panellized, with
tooling holes and features specific to the end assembly and test
environment, NOT for the convenience of pcb fab.
A PCB fabricator mods gerbers at their own risk. . . .
RL
Reply by Lasse Langwadt Christensen●November 9, 20212021-11-09
tirsdag den 9. november 2021 kl. 21.44.35 UTC+1 skrev legg:
> On Tue, 9 Nov 2021 09:23:16 -0800 (PST), Lasse Langwadt Christensen
> <lang...@fonz.dk> wrote:
>
> >tirsdag den 9. november 2021 kl. 15.06.28 UTC+1 skrev legg:
> >> On Tue, 9 Nov 2021 08:49:37 -0000 (UTC),
> >> DecadentLinux...@decadence.org wrote:
> >>
> >> >legg <le...@nospam.magma.ca> wrote in
> >> >news:0r3kogdjcqndrm0a9...@4ax.com:
> >> >
> >> >> It's not something that you ignore to save cost on drill bits
> >> >> at fab.
> >> >>
> >> >
> >> > No layout we ever did had any concerns over hole counts or sizes much
> >> >less their cost during getting the job done.
> >> >
> >> > The boards I have seen even from cheap quick fabs are pretty dang
> >> >tight, and the price points don't mention drill bits, so I am guessing
> >> >the fab houses are better at poking them in instead of just diving and
> >> >driving and are getting better tool life. Doesn't FR-4 drill easier if
> >> >it is hot? Or it is glass fibers either way, so doesn't matter I
> >> >guess... wear is inevitable and quick.
> >> I've yet to see a fab house claim that - 'we generally prefer to
> >> remove (annular rings)' in their documentation, or to offer price
> >> points on this as an option.
> >>
> >
> >5 minutes of googling find several pcb manufacturers that say removing
> >non-functional pads on inner layers are standard procedure in their cam processing
> >
> >
> Well, perhaps I'm out of date. Of the first 24 PCB mfring links in
> my portable's bookmarks, only two were still in business. No annular
> ring references on their site. Ditto with such vendors as JLCPCB.
>
> Googling 'removing non-functional pads on inner layers' got me
> group discussions or software vendors (on a single html page),
> neither of which are very reliable sources for hard-nosed info
> on pcb fab.
>
> Would probably have had better luck in Mandarin or Cantonese. . .
> Perhaps you could supply links to the info you found so easily.
> Not sure I'd add them to my bookmarks, but they would serve
> better than dead links.
>
> I have a 30+years library in paper and electronic format that
> I'd usually consult, but can't reach before Thursday PM.
> In real designs, putting signal traces through power connectors,
> or vice versa, is just a symptom of bad planning.