jlarkin@highlandsniptechnology.com wrote in news:iuniog9c6pjb5l152mhhpr1fsgl5cvn99m@4ax.com:> > > I'm planning a 4 or 6 layer board with all 2 oz copper and thin > FR4 dielectrics. > > Given a thru-hole multi-row connector (like a 3x32 DIN) I want to > ground some pins. The grounded pins would hit an inner ground > plane flood-over, namely no thermals. Clearly annular rings on the > pad stack wouldn't matter on those layers; it's all copper. > > But where other pins aren't grounded, I want miminal loss of > copper on the ground plane. So I'd prefer no annular ring, just a > plated hole with the voltage clearance between the drill and the > circular cutout of the ground pour. > > Does that sound OK? > > Of course it will be hard to solder. > > >You could tighten the hole to pin tolerance such that it grabs the pin, almost needing to be driven in with a slight force, then apply the reflow heat to the pin, very carefully as you add the solde to the base, having been wetted by a flux pen. That is for hand soldering. For a reflow thing a crimped pin will resist 'fall through', and the tighter hole with ensure good reflow throughout the hole. With lead free being hotter though I would mask them and hand solder later, because the thermal mass of those pins can bake out those plated through attachments real fast. I would like a rating on my comments, John. I used to teach soldering.. hand soldering.
annular ring issue
Started by ●November 8, 2021
Reply by ●November 8, 20212021-11-08
Reply by ●November 8, 20212021-11-08
legg <legg@nospam.magma.ca> wrote in news:hkpiogt81tpgae9gof7t6fte3md0q27rbe@4ax.com:> On Mon, 08 Nov 2021 09:44:02 -0800, > jlarkin@highlandsniptechnology.com wrote: > >> >> >>I'm planning a 4 or 6 layer board with all 2 oz copper and thin >>FR4 dielectrics. >> >>Given a thru-hole multi-row connector (like a 3x32 DIN) I want to >>ground some pins. The grounded pins would hit an inner ground >>plane flood-over, namely no thermals. Clearly annular rings on the >>pad stack wouldn't matter on those layers; it's all copper. >> >>But where other pins aren't grounded, I want miminal loss of >>copper on the ground plane. So I'd prefer no annular ring, just a >>plated hole with the voltage clearance between the drill and the >>circular cutout of the ground pour. >> >>Does that sound OK? >> >>Of course it will be hard to solder. > > There's a minimum annular ring for PTHs to allow for layer/layer > mis-registration tolerances. Plating of PTH and PTH reliability is > affected if there's no layer anchor on the barrel sructure. > > Crunch the numbers using your vendor's tolerances, or accept all > liability down the road. > > Connector PTHs have more issues than simple vias, due to differing > mechanical requirements, but all soldered PTH connectors will > likely follow one set of guidelines, vs the force-fit varieties. > > You're asking questions that a first-year intern might, because > you believe 'the boss' can bend the rules. This is only true in so > far as you're the one signing on the dotted line ($). You may be > setting a bad example for those who may not be so fortunate in > their future endeavors. Asking questions is good, but 'tell me > why I can't do this' gets lame really quick. >We used to break a lot of rules for our HV designs, because we made miniature supplies, so everything was smaller, and pushed the very liits being discussed. We had a dedicated PC with non-networked layout software on it with the design rules adjusted for that one project alone, back in the single seat CAD days. That was fun. We had layers that were slotted sandwiched with layers that did not carry the slot. All things the PCB house we used had to be real time aware of to keep there red flags in their tools from causing a fab house tech to make improper adjustments to your layout.
Reply by ●November 8, 20212021-11-08
On Mon, 8 Nov 2021 22:41:51 -0000 (UTC), DecadentLinuxUserNumeroUno@decadence.org wrote:>legg <legg@nospam.magma.ca> wrote in >news:hkpiogt81tpgae9gof7t6fte3md0q27rbe@4ax.com: > >> On Mon, 08 Nov 2021 09:44:02 -0800, >> jlarkin@highlandsniptechnology.com wrote: >> >>> >>> >>>I'm planning a 4 or 6 layer board with all 2 oz copper and thin >>>FR4 dielectrics. >>> >>>Given a thru-hole multi-row connector (like a 3x32 DIN) I want to >>>ground some pins. The grounded pins would hit an inner ground >>>plane flood-over, namely no thermals. Clearly annular rings on the >>>pad stack wouldn't matter on those layers; it's all copper. >>> >>>But where other pins aren't grounded, I want miminal loss of >>>copper on the ground plane. So I'd prefer no annular ring, just a >>>plated hole with the voltage clearance between the drill and the >>>circular cutout of the ground pour. >>> >>>Does that sound OK? >>> >>>Of course it will be hard to solder. >> >> There's a minimum annular ring for PTHs to allow for layer/layer >> mis-registration tolerances. Plating of PTH and PTH reliability is >> affected if there's no layer anchor on the barrel sructure. >> >> Crunch the numbers using your vendor's tolerances, or accept all >> liability down the road. >> >> Connector PTHs have more issues than simple vias, due to differing >> mechanical requirements, but all soldered PTH connectors will >> likely follow one set of guidelines, vs the force-fit varieties. >> >> You're asking questions that a first-year intern might, because >> you believe 'the boss' can bend the rules. This is only true in so >> far as you're the one signing on the dotted line ($). You may be >> setting a bad example for those who may not be so fortunate in >> their future endeavors. Asking questions is good, but 'tell me >> why I can't do this' gets lame really quick. >> > > We used to break a lot of rules for our HV designs, because we made >miniature supplies, so everything was smaller, and pushed the very >liits being discussed. We had a dedicated PC with non-networked >layout software on it with the design rules adjusted for that one >project alone, back in the single seat CAD days. That was fun. > > We had layers that were slotted sandwiched with layers that did not >carry the slot. All things the PCB house we used had to be real time >aware of to keep there red flags in their tools from causing a fab >house tech to make improper adjustments to your layout.I've considered making slots from one side that went only partially through the board. That could create a suspended substrate transmission line, or could reduce pad capacitances. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
Reply by ●November 8, 20212021-11-08
On Mon, 8 Nov 2021 22:36:08 -0000 (UTC), DecadentLinuxUserNumeroUno@decadence.org wrote:>jlarkin@highlandsniptechnology.com wrote in >news:iuniog9c6pjb5l152mhhpr1fsgl5cvn99m@4ax.com: > >> >> >> I'm planning a 4 or 6 layer board with all 2 oz copper and thin >> FR4 dielectrics. >> >> Given a thru-hole multi-row connector (like a 3x32 DIN) I want to >> ground some pins. The grounded pins would hit an inner ground >> plane flood-over, namely no thermals. Clearly annular rings on the >> pad stack wouldn't matter on those layers; it's all copper. >> >> But where other pins aren't grounded, I want miminal loss of >> copper on the ground plane. So I'd prefer no annular ring, just a >> plated hole with the voltage clearance between the drill and the >> circular cutout of the ground pour. >> >> Does that sound OK? >> >> Of course it will be hard to solder. >> >> >> > > You could tighten the hole to pin tolerance such that it grabs the >pin, almost needing to be driven in with a slight force, then apply >the reflow heat to the pin, very carefully as you add the solde to >the base, having been wetted by a flux pen.What I specifically want now is maximum ground plane flooding, so pins that pass through but don't connect to the plane should have no annular ring, just a plated drill and a minimal clearance to the plane. 0.025 square posts, maybe 38 mil drill, plated hole, and maybe a 6 mil insulating clearance around the drill, on the ground plane. That maximizes thermal conductivity of the grounded pins. Lasse's paper suggests that 1/3 of PCB houses always remove unconnected annular rings 1/3 of PCB houses never remove unconnected annular rings 1/3 of PCB houses don't answer surveys.> > That is for hand soldering. For a reflow thing a crimped pin will >resist 'fall through', and the tighter hole with ensure good reflow >throughout the hole. With lead free being hotter though I would mask >them and hand solder later, because the thermal mass of those pins >can bake out those plated through attachments real fast. > > I would like a rating on my comments, John. I used to teach >soldering.. hand soldering.Sounds good. We'll probably try to use our spiffy new selective solder machine. One little board will have about 220 pins into 4 layers of 2 oz copper without thermal spokes... hard to solder by hand. Just possibly one could drop little toroidal solder preforms onto the pins and run through an oven. I worked for an outfit that did NASA soldering, for the S1B moonshot booster. I designed some boards, and they let me do a couple of NASA solder joints myself, just so I could say I did it. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
Reply by ●November 9, 20212021-11-09
On a sunny day (Mon, 08 Nov 2021 17:07:31 -0500) it happened Joe Gwinn <joegwinn@comcast.net> wrote in <l07jogpm3fj4mdfre7lakovptt0p8p0n8s@4ax.com>:>On Mon, 08 Nov 2021 11:24:14 -0800, John Larkin ><jlarkin@highland_atwork_technology.com> wrote: > >>On Mon, 08 Nov 2021 19:07:06 GMT, Jan Panteltje >><pNaOnStPeAlMtje@yahoo.com> wrote: >> >>>On a sunny day (Mon, 08 Nov 2021 09:44:02 -0800) it happened >>>jlarkin@highlandsniptechnology.com wrote in >>><iuniog9c6pjb5l152mhhpr1fsgl5cvn99m@4ax.com>: >>> >>>> >>>> >>>>I'm planning a 4 or 6 layer board with all 2 oz copper and thin FR4 >>>>dielectrics. >>>> >>>>Given a thru-hole multi-row connector (like a 3x32 DIN) I want to >>>>ground some pins. The grounded pins would hit an inner ground plane >>>>flood-over, namely no thermals. Clearly annular rings on the pad stack >>>>wouldn't matter on those layers; it's all copper. >>>> >>>>But where other pins aren't grounded, I want miminal loss of copper on >>>>the ground plane. So I'd prefer no annular ring, just a plated hole >>>>with the voltage clearance between the drill and the circular cutout >>>>of the ground pour. >>>> >>>>Does that sound OK? >>>> >>>>Of course it will be hard to solder. >>> >>>Sounds doable. >>>At very high currents one start thinking about those mill spec big round connectors with >>>many pins, wiring.. >> >>5 amps per pin, 60 of those per connector. We tested some connectors >>rated for 5 amps/pin, but running a bunch close together heated the >>shell to 90C. >> >>Seems like connector current ratings are all over the place, even for >>the same technologies, and that getting the heat out dominates >>real-world current capability. So the thermal path from the grounded >>pins, into the ground plane, should be as uninterrupted as possible. >> >>Hence no annular rings on the ungrounded pins. The function of the >>grounded pins is to help cool the current-carrying pins. >> >>Just wondering what other people might think. > >I'd worry about stress from thermal cycling causing low-cycle fatigue >failures in the live vias. BTDT. > >A good way to tell if this is a problem is a few test boards, each >with string of vias et al, plus an isolated length of the same copper >with no or only large diameter vias, temperature cycled day and night >for a weekend or so. The resistance of the two paths should be >similar. > >Using a 6.5-digit 4-wire resistance measurement, measure the precise >resistance of the via-chain and of the comparison chain at ten Hertz >or so (a Fluke Data Bucket is traditional). As low-cycle fatigue >accumulates, small voids will nucleate and grow, affecting the >resistance of the via chain, while the reference chain will be >unchanged. > >The ratio the two measured resistances will cancel out the temperature >coefficient of electrical conductivity of the copper, highlighting >tiny differences between the two paths. > >The resistance ratio will start to deviate long before any explicit >failure happens. Void growth is a random process, exhibiting 1/f >noise. One can also take a FFT of the resistance ratio time series, >and look for changes in one-hertz "power" level over time. > >Joe GwinnExactly! Some connectors from some manufacturers are very different, I once had a sales representaive asking me why I bought from an other manufacurer, took his connector apart and put it next to the other, the good ones had clamp springs, his not. Vibration, temperature stress, etc... Do not take any chances going by their max ratings, test it.
Reply by ●November 9, 20212021-11-09
On Mon, 8 Nov 2021 22:41:51 -0000 (UTC), DecadentLinuxUserNumeroUno@decadence.org wrote:>legg <legg@nospam.magma.ca> wrote in >news:hkpiogt81tpgae9gof7t6fte3md0q27rbe@4ax.com: > >> On Mon, 08 Nov 2021 09:44:02 -0800, >> jlarkin@highlandsniptechnology.com wrote: >> >>> >>> >>>I'm planning a 4 or 6 layer board with all 2 oz copper and thin >>>FR4 dielectrics. >>> >>>Given a thru-hole multi-row connector (like a 3x32 DIN) I want to >>>ground some pins. The grounded pins would hit an inner ground >>>plane flood-over, namely no thermals. Clearly annular rings on the >>>pad stack wouldn't matter on those layers; it's all copper. >>> >>>But where other pins aren't grounded, I want miminal loss of >>>copper on the ground plane. So I'd prefer no annular ring, just a >>>plated hole with the voltage clearance between the drill and the >>>circular cutout of the ground pour. >>> >>>Does that sound OK? >>> >>>Of course it will be hard to solder. >> >> There's a minimum annular ring for PTHs to allow for layer/layer >> mis-registration tolerances. Plating of PTH and PTH reliability is >> affected if there's no layer anchor on the barrel sructure. >> >> Crunch the numbers using your vendor's tolerances, or accept all >> liability down the road. >> >> Connector PTHs have more issues than simple vias, due to differing >> mechanical requirements, but all soldered PTH connectors will >> likely follow one set of guidelines, vs the force-fit varieties. >> >> You're asking questions that a first-year intern might, because >> you believe 'the boss' can bend the rules. This is only true in so >> far as you're the one signing on the dotted line ($). You may be >> setting a bad example for those who may not be so fortunate in >> their future endeavors. Asking questions is good, but 'tell me >> why I can't do this' gets lame really quick. >> > > We used to break a lot of rules for our HV designs, because we made >miniature supplies, so everything was smaller, and pushed the very >liits being discussed. We had a dedicated PC with non-networked >layout software on it with the design rules adjusted for that one >project alone, back in the single seat CAD days. That was fun. > > We had layers that were slotted sandwiched with layers that did not >carry the slot. All things the PCB house we used had to be real time >aware of to keep there red flags in their tools from causing a fab >house tech to make improper adjustments to your layout.I've done similar zero-annular ring layouts on HV stuff, with <=4layers. High current's a different issue. Connectors are a different issue. Through-hole wall activation and barrel crack formation are reliability concerns covered in the literature - including the last section of Caswell's article linked by LLC. It's not something that you ignore to save cost on drill bits at fab. RL
Reply by ●November 9, 20212021-11-09
John Larkin <jlarkin@highland_atwork_technology.com> wrote in news:cjgjogl0s2mafou1skkameuar69bi6pn3q@4ax.com:> On Mon, 8 Nov 2021 22:36:08 -0000 (UTC), > DecadentLinuxUserNumeroUno@decadence.org wrote: > >>jlarkin@highlandsniptechnology.com wrote in >>news:iuniog9c6pjb5l152mhhpr1fsgl5cvn99m@4ax.com: >> >>> >>> >>> I'm planning a 4 or 6 layer board with all 2 oz copper and thin >>> FR4 dielectrics. >>> >>> Given a thru-hole multi-row connector (like a 3x32 DIN) I want >>> to ground some pins. The grounded pins would hit an inner ground >>> plane flood-over, namely no thermals. Clearly annular rings on >>> the pad stack wouldn't matter on those layers; it's all copper. >>> >>> But where other pins aren't grounded, I want miminal loss of >>> copper on the ground plane. So I'd prefer no annular ring, just >>> a plated hole with the voltage clearance between the drill and >>> the circular cutout of the ground pour. >>> >>> Does that sound OK? >>> >>> Of course it will be hard to solder. >>> >>> >>> >> >> You could tighten the hole to pin tolerance such that it grabs >> the >>pin, almost needing to be driven in with a slight force, then >>apply the reflow heat to the pin, very carefully as you add the >>solde to the base, having been wetted by a flux pen. > > What I specifically want now is maximum ground plane flooding, so > pins that pass through but don't connect to the plane should have > no annular ring, just a plated drill and a minimal clearance to > the plane. > > 0.025 square posts, maybe 38 mil drill, plated hole, and maybe a 6 > mil insulating clearance around the drill, on the ground plane. > That maximizes thermal conductivity of the grounded pins. > > Lasse's paper suggests that > > 1/3 of PCB houses always remove unconnected annular rings > 1/3 of PCB houses never remove unconnected annular rings > 1/3 of PCB houses don't answer surveys. > > >> >> That is for hand soldering. For a reflow thing a crimped pin >> will >>resist 'fall through', and the tighter hole with ensure good >>reflow throughout the hole. With lead free being hotter though I >>would mask them and hand solder later, because the thermal mass of >>those pins can bake out those plated through attachments real >>fast. >> >> I would like a rating on my comments, John. I used to teach >>soldering.. hand soldering. > > Sounds good. We'll probably try to use our spiffy new selective > solder machine. One little board will have about 220 pins into 4 > layers of 2 oz copper without thermal spokes... hard to solder by > hand. > > Just possibly one could drop little toroidal solder preforms onto > the pins and run through an oven. > > I worked for an outfit that did NASA soldering, for the S1B > moonshot booster. I designed some boards, and they let me do a > couple of NASA solder joints myself, just so I could say I did it. >I had "NASA Certifiable" soldering skills, and way way back at one place, I could solder a joint and the fillet would be right down at the circuit board, abrely there berely visible, on both sides. Perfecyt joints, minimum solder. My stuff looked like it was done by a machine. Even my SMD stuff can look better than machine. I used 11 mil (IIRC) stencils on a PCB layout from General Instrument for their first HDTV processing boards back in like '96 was it... Any way, the paste up made solder joints that were perfect, but still a little fatter than I do by hand. But if you get too thin on the stencil, the rubber wiping face cups the deposits. It is really hard to dial in if one is trying to minimalize the joint sizes. And then there is the flux choice thing. Between a former boss' vast knowledge and experience and the fab house he used for our HV stuff, he was able to always make sure they did not modify anything. We had boards with a break line where the mask ends to get better potting media adhesion down in the HV multiplier section I used to want to do a layout the old way where the via to trace attachment looks like a tear drop, curved traces, etc, and my own custom SMD pads, but a lot of houses back then would take your gerber data and use their rules to make their final process and some things would get morphed. CAD packages can be set up this way but it take a bit of time to transit angular shifts out and curved in. Should be less noisy though. The thing about using an oven with those barely sized rings and 'tubes' (PTH) they detach easier too. I would make one quick hand solder relfow of each pin only applying the heat one time to the pin and adding solder at the ring pin interface real fast, watch it flow, and then off. Minimum time lapse event to obtain a solid void free joint. Unless you are using 63/37 flow temps. Then you could reflow it and get even better results. I hate lead free. RoHS cost us a lot. 63/37 solder does not introduce itself into the environment, just like the lead from cops' bullets down at the gun range don't. It is compounds of lead we have to worry about (car batteries and such). We are likely far worse off from all the PFAS in our bodies which is retained and usually results in a count higher than the streams the water you used to get them has. Probably what has done my thyroid in.
Reply by ●November 9, 20212021-11-09
legg <legg@nospam.magma.ca> wrote in news:0r3kogdjcqndrm0a95lfr2vvfgg2pne2s5@4ax.com:> It's not something that you ignore to save cost on drill bits > at fab. >No layout we ever did had any concerns over hole counts or sizes much less their cost during getting the job done. The boards I have seen even from cheap quick fabs are pretty dang tight, and the price points don't mention drill bits, so I am guessing the fab houses are better at poking them in instead of just diving and driving and are getting better tool life. Doesn't FR-4 drill easier if it is hot? Or it is glass fibers either way, so doesn't matter I guess... wear is inevitable and quick.
Reply by ●November 9, 20212021-11-09
On Tue, 9 Nov 2021 08:49:37 -0000 (UTC), DecadentLinuxUserNumeroUno@decadence.org wrote:>legg <legg@nospam.magma.ca> wrote in >news:0r3kogdjcqndrm0a95lfr2vvfgg2pne2s5@4ax.com: > >> It's not something that you ignore to save cost on drill bits >> at fab. >> > > No layout we ever did had any concerns over hole counts or sizes much >less their cost during getting the job done. > > The boards I have seen even from cheap quick fabs are pretty dang >tight, and the price points don't mention drill bits, so I am guessing >the fab houses are better at poking them in instead of just diving and >driving and are getting better tool life. Doesn't FR-4 drill easier if >it is hot? Or it is glass fibers either way, so doesn't matter I >guess... wear is inevitable and quick.I've yet to see a fab house claim that - 'we generally prefer to remove (annular rings)' in their documentation, or to offer price points on this as an option. If your artwork calls for them, and you're paying for them, then they better be there. It's not monkey business. RL
Reply by ●November 9, 20212021-11-09
On Tuesday, November 9, 2021 at 6:06:28 AM UTC-8, legg wrote:> On Tue, 9 Nov 2021 08:49:37 -0000 (UTC), > DecadentLinux...@decadence.org wrote: > > >legg <le...@nospam.magma.ca> wrote in > >news:0r3kogdjcqndrm0a9...@4ax.com: > > > >> It's not something that you ignore to save cost on drill bits > >> at fab. > >> > > > > No layout we ever did had any concerns over hole counts or sizes much > >less their cost during getting the job done. > > > > The boards I have seen even from cheap quick fabs are pretty dang > >tight, and the price points don't mention drill bits, so I am guessing > >the fab houses are better at poking them in instead of just diving and > >driving and are getting better tool life. Doesn't FR-4 drill easier if > >it is hot? Or it is glass fibers either way, so doesn't matter I > >guess... wear is inevitable and quick. > I've yet to see a fab house claim that - 'we generally prefer to > remove (annular rings)' in their documentation, or to offer price > points on this as an option. > > If your artwork calls for them, and you're paying for them, then > they better be there.I don't get it. If they see a pad that is going to be drilled, they can just flash a donut, instead of a pancake (breakfast time now). Why would it cost extra wear on drill bit?
