Hi We have a GaN FET that is dumping voltage into a capacitor. The GaN drain is connected to 50V, and the capacitor is connected on the source of the FET. Sort of like this: https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg "To load" is connected to a small 50pF capacitor to ground. We need to pump current into it very fast for reasons I cannot disclose. So we turn the high side FET on in about 500ps, and charge the capacitor. Pretty basic :-) We need maximum current into the capacitor, so we are looking to reducing parasitics and losses. One guy on the team is worried about loss and reflections, treating the line from the supply, through the FET and going to the capacitor to ground as a transmission line. Wanting to use best possible PCB material for low loss (Rogers 4350B), and using ADS to simulate in order to optimize the design. He also wants to do it with matched 50ohms impedance all the way. For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that transmission line impedance comes into play at 1/6 of the wavelength, so that's 35mm. So we just need to keep the distance from the decoupling caps down to the FET and capacitor path less than 35mm. The path length is about 10mm. About losses, if I compare standard FR4 to Rogers 4350B (good material), I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss at 10mm path length https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low resistance. I am used to do SMPS design, in which we use wide traces, big ground plane and place components tight so reflections matter less (the return time is less than the rising edge of the waveform). Also, I never match impedances for traces. What would your take be? Regards Klaus
Short track and impedance matching
Started by ●April 25, 2023
Reply by ●April 25, 20232023-04-25
On Tuesday, April 25, 2023 at 9:31:22 PM UTC+10, Klaus Vestergaard Kragelund wrote:> Hi > > We have a GaN FET that is dumping voltage into a capacitor. The GaN > drain is connected to 50V, and the capacitor is connected on the source > of the FET. Sort of like this: > > https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg > > "To load" is connected to a small 50pF capacitor to ground. > > We need to pump current into it very fast for reasons I cannot disclose. > So we turn the high side FET on in about 500ps, and charge the > capacitor. Pretty basic :-) > > We need maximum current into the capacitor, so we are looking to > reducing parasitics and losses. > > One guy on the team is worried about loss and reflections, treating the > line from the supply, through the FET and going to the capacitor to > ground as a transmission line. Wanting to use best possible PCB material > for low loss (Rogers 4350B), and using ADS to simulate in order to > optimize the design. He also wants to do it with matched 50ohms > impedance all the way. > > For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed > is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that > transmission line impedance comes into play at 1/6 of the wavelength, so > that's 35mm. So we just need to keep the distance from the decoupling > caps down to the FET and capacitor path less than 35mm. > > The path length is about 10mm. > > About losses, if I compare standard FR4 to Rogers 4350B (good material), > I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss > at 10mm path length > > https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html > > Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. > I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I > expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low > resistance. > > I am used to do SMPS design, in which we use wide traces, big ground > plane and place components tight so reflections matter less (the return > time is less than the rising edge of the waveform). Also, I never match > impedances for traces. > > What would your take be?Why the emphasis on getting 50R transmission line impedance? You can't get all that far away from it. but a wider track with a somewhat lower impedance would give you lower losses, A potential problem with an FR4 resin bonded glass fibre board is that the periodicity in the woven glass fibre mesh inserts small regular impedance variations along the track. I've never known it to be a problem, but my narrowest pulse was only 500psec wide, which isn't all that fast. Rogers boards tend to be a lot more uniform, but weaker. -- Bill Sloman, Sydney
Reply by ●April 25, 20232023-04-25
On Tuesday, 25 April 2023 at 13:16:55 UTC+1, Anthony William Sloman wrote:> On Tuesday, April 25, 2023 at 9:31:22 PM UTC+10, Klaus Vestergaard Kragelund wrote: > > Hi > > > > We have a GaN FET that is dumping voltage into a capacitor. The GaN > > drain is connected to 50V, and the capacitor is connected on the source > > of the FET. Sort of like this: > > > > https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg > > > > "To load" is connected to a small 50pF capacitor to ground. > > > > We need to pump current into it very fast for reasons I cannot disclose. > > So we turn the high side FET on in about 500ps, and charge the > > capacitor. Pretty basic :-) > > > > We need maximum current into the capacitor, so we are looking to > > reducing parasitics and losses. > > > > One guy on the team is worried about loss and reflections, treating the > > line from the supply, through the FET and going to the capacitor to > > ground as a transmission line. Wanting to use best possible PCB material > > for low loss (Rogers 4350B), and using ADS to simulate in order to > > optimize the design. He also wants to do it with matched 50ohms > > impedance all the way. > > > > For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed > > is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that > > transmission line impedance comes into play at 1/6 of the wavelength, so > > that's 35mm. So we just need to keep the distance from the decoupling > > caps down to the FET and capacitor path less than 35mm. > > > > The path length is about 10mm. > > > > About losses, if I compare standard FR4 to Rogers 4350B (good material), > > I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss > > at 10mm path length > > > > https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html > > > > Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. > > I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I > > expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low > > resistance. > > > > I am used to do SMPS design, in which we use wide traces, big ground > > plane and place components tight so reflections matter less (the return > > time is less than the rising edge of the waveform). Also, I never match > > impedances for traces. > > > > What would your take be? > Why the emphasis on getting 50R transmission line impedance? You can't get all that far away from it. but a wider track with a somewhat lower impedance would give you lower losses, > > A potential problem with an FR4 resin bonded glass fibre board is that the periodicity in the woven glass fibre mesh inserts small regular impedance variations along the track. I've never known it to be a problem, but my narrowest pulse was only 500psec wide, which isn't all that fast. > > Rogers boards tend to be a lot more uniform, but weaker.Use FR4. Have a suitable decoupling capacitor right next to the FET switch. Augment the decoupling with very short connections to a relatively large power plane - ideally several interleaved ground and power planes to make a distributed interleaved capacitor. Use multiple vias to get a low inductance connection to the power plane(s) and lots of vias to stitch all the ground areas together. Place the vias slightly randomly to avoid creating regular structures. Most of the power supply inductance will then be right next to the switch, so use the widest tracks you can along with the thinnest layer spacing for highest capacitance. John
Reply by ●April 25, 20232023-04-25
On 25-04-2023 14:16, Anthony William Sloman wrote:> On Tuesday, April 25, 2023 at 9:31:22 PM UTC+10, Klaus Vestergaard Kragelund wrote: >> Hi >> >> We have a GaN FET that is dumping voltage into a capacitor. The GaN >> drain is connected to 50V, and the capacitor is connected on the source >> of the FET. Sort of like this: >> >> https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg >> >> "To load" is connected to a small 50pF capacitor to ground. >> >> We need to pump current into it very fast for reasons I cannot disclose. >> So we turn the high side FET on in about 500ps, and charge the >> capacitor. Pretty basic :-) >> >> We need maximum current into the capacitor, so we are looking to >> reducing parasitics and losses. >> >> One guy on the team is worried about loss and reflections, treating the >> line from the supply, through the FET and going to the capacitor to >> ground as a transmission line. Wanting to use best possible PCB material >> for low loss (Rogers 4350B), and using ADS to simulate in order to >> optimize the design. He also wants to do it with matched 50ohms >> impedance all the way. >> >> For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed >> is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that >> transmission line impedance comes into play at 1/6 of the wavelength, so >> that's 35mm. So we just need to keep the distance from the decoupling >> caps down to the FET and capacitor path less than 35mm. >> >> The path length is about 10mm. >> >> About losses, if I compare standard FR4 to Rogers 4350B (good material), >> I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss >> at 10mm path length >> >> https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html >> >> Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. >> I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I >> expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low >> resistance. >> >> I am used to do SMPS design, in which we use wide traces, big ground >> plane and place components tight so reflections matter less (the return >> time is less than the rising edge of the waveform). Also, I never match >> impedances for traces. >> >> What would your take be? > > Why the emphasis on getting 50R transmission line impedance? You can't get all that far away from it. but a wider track with a somewhat lower impedance would give you lower losses, >That is my point exactly. With a small distance, no need to do simulation in ADS, and reflections will be kept low.> A potential problem with an FR4 resin bonded glass fibre board is that the periodicity in the woven glass fibre mesh inserts small regular impedance variations along the track. I've never known it to be a problem, but my narrowest pulse was only 500psec wide, which isn't all that fast.Yes, and there is also a small effect on how uniform the copper is. When it is rolled on, there are mountains and valleys, so the HF signal will travel longer for small skindepts. The info I have from the manufacturer is that the valleys are max 10% of the copper thickness. So wont add much resistance either.> > Rogers boards tend to be a lot more uniform, but weaker. >
Reply by ●April 25, 20232023-04-25
On 25-04-2023 14:44, John Walliker wrote:> On Tuesday, 25 April 2023 at 13:16:55 UTC+1, Anthony William Sloman wrote: >> On Tuesday, April 25, 2023 at 9:31:22 PM UTC+10, Klaus Vestergaard Kragelund wrote: >>> Hi >>> >>> We have a GaN FET that is dumping voltage into a capacitor. The GaN >>> drain is connected to 50V, and the capacitor is connected on the source >>> of the FET. Sort of like this: >>> >>> https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg >>> >>> "To load" is connected to a small 50pF capacitor to ground. >>> >>> We need to pump current into it very fast for reasons I cannot disclose. >>> So we turn the high side FET on in about 500ps, and charge the >>> capacitor. Pretty basic :-) >>> >>> We need maximum current into the capacitor, so we are looking to >>> reducing parasitics and losses. >>> >>> One guy on the team is worried about loss and reflections, treating the >>> line from the supply, through the FET and going to the capacitor to >>> ground as a transmission line. Wanting to use best possible PCB material >>> for low loss (Rogers 4350B), and using ADS to simulate in order to >>> optimize the design. He also wants to do it with matched 50ohms >>> impedance all the way. >>> >>> For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed >>> is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that >>> transmission line impedance comes into play at 1/6 of the wavelength, so >>> that's 35mm. So we just need to keep the distance from the decoupling >>> caps down to the FET and capacitor path less than 35mm. >>> >>> The path length is about 10mm. >>> >>> About losses, if I compare standard FR4 to Rogers 4350B (good material), >>> I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss >>> at 10mm path length >>> >>> https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html >>> >>> Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. >>> I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I >>> expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low >>> resistance. >>> >>> I am used to do SMPS design, in which we use wide traces, big ground >>> plane and place components tight so reflections matter less (the return >>> time is less than the rising edge of the waveform). Also, I never match >>> impedances for traces. >>> >>> What would your take be? >> Why the emphasis on getting 50R transmission line impedance? You can't get all that far away from it. but a wider track with a somewhat lower impedance would give you lower losses, >> >> A potential problem with an FR4 resin bonded glass fibre board is that the periodicity in the woven glass fibre mesh inserts small regular impedance variations along the track. I've never known it to be a problem, but my narrowest pulse was only 500psec wide, which isn't all that fast. >> >> Rogers boards tend to be a lot more uniform, but weaker. > > Use FR4. Have a suitable decoupling capacitor right next to the FET switch. Augment > the decoupling with very short connections to a relatively large power plane - ideally several > interleaved ground and power planes to make a distributed interleaved capacitor. Use > multiple vias to get a low inductance connection to the power plane(s) and lots of vias to > stitch all the ground areas together. Place the vias slightly randomly to avoid creating regular > structures. Most of the power supply inductance will then be right next to the switch, so use the > widest tracks you can along with the thinnest layer spacing for highest capacitance.Yes, that's how I plan to do it. A big ground plane in several layers, components tight, and placed in a circle to reduce path length even more. And then a small 2mm trace on the path. As you say multiple vias, since one via adds 1nH in itself. If possible no vias in the signal path since then I would need image vias also.
Reply by ●April 25, 20232023-04-25
On Tue, 25 Apr 2023 13:31:13 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:>Hi > >We have a GaN FET that is dumping voltage into a capacitor. The GaN >drain is connected to 50V, and the capacitor is connected on the source >of the FET. Sort of like this: > >https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg > >"To load" is connected to a small 50pF capacitor to ground. > >We need to pump current into it very fast for reasons I cannot disclose. >So we turn the high side FET on in about 500ps, and charge the >capacitor. Pretty basic :-)Where do you get a gate driver that can turn on a GaN fet in 500 ps? I need that! A little inductance in series with the gate could help some. The gate resistor will slow things down. Actually, I need to drive a capacitive load, an optical thing, to maybe 25 volts in 1 ns. Up and down! At 100 MHz! I can't disclose the application. Even I'm not allowed to know the application. Something related to war, maybe. I like to use the small EPC parts, the tiny 4-ball things, for stuff like this, but I;ve never seen, in real life, the sorts of speeds I see in Spice.> >We need maximum current into the capacitor, so we are looking to >reducing parasitics and losses. > >One guy on the team is worried about loss and reflections, treating the >line from the supply, through the FET and going to the capacitor to >ground as a transmission line. Wanting to use best possible PCB material >for low loss (Rogers 4350B), and using ADS to simulate in order to >optimize the design. He also wants to do it with matched 50ohms >impedance all the way.The PCB dielectric won't matter. The part and trace parasitics sure will.> >For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed >is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that >transmission line impedance comes into play at 1/6 of the wavelength, so >that's 35mm. So we just need to keep the distance from the decoupling >caps down to the FET and capacitor path less than 35mm. > >The path length is about 10mm.Envision copper pours, lots of paralleled caps, and very short traces. Inductive peaking of the load could help.> >About losses, if I compare standard FR4 to Rogers 4350B (good material), >I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss >at 10mm path length > >https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html > >Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. >I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I >expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low >resistance. > >I am used to do SMPS design, in which we use wide traces, big ground >plane and place components tight so reflections matter less (the return >time is less than the rising edge of the waveform). Also, I never match >impedances for traces. > >What would your take be?50 ohms and 50 pF is a time constant of 2.5 ns. So forget making anything 50 ohms. Your "50 ohm" guy is driven by convention and not thinking. That happens a lot.> >Regards > >Klaus
Reply by ●April 25, 20232023-04-25
On Tue, 25 Apr 2023 14:58:31 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:>On 25-04-2023 14:16, Anthony William Sloman wrote: >> On Tuesday, April 25, 2023 at 9:31:22?PM UTC+10, Klaus Vestergaard Kragelund wrote: >>> Hi >>> >>> We have a GaN FET that is dumping voltage into a capacitor. The GaN >>> drain is connected to 50V, and the capacitor is connected on the source >>> of the FET. Sort of like this: >>> >>> https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg >>> >>> "To load" is connected to a small 50pF capacitor to ground. >>> >>> We need to pump current into it very fast for reasons I cannot disclose. >>> So we turn the high side FET on in about 500ps, and charge the >>> capacitor. Pretty basic :-) >>> >>> We need maximum current into the capacitor, so we are looking to >>> reducing parasitics and losses. >>> >>> One guy on the team is worried about loss and reflections, treating the >>> line from the supply, through the FET and going to the capacitor to >>> ground as a transmission line. Wanting to use best possible PCB material >>> for low loss (Rogers 4350B), and using ADS to simulate in order to >>> optimize the design. He also wants to do it with matched 50ohms >>> impedance all the way. >>> >>> For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed >>> is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that >>> transmission line impedance comes into play at 1/6 of the wavelength, so >>> that's 35mm. So we just need to keep the distance from the decoupling >>> caps down to the FET and capacitor path less than 35mm. >>> >>> The path length is about 10mm. >>> >>> About losses, if I compare standard FR4 to Rogers 4350B (good material), >>> I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss >>> at 10mm path length >>> >>> https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html >>> >>> Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. >>> I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I >>> expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low >>> resistance. >>> >>> I am used to do SMPS design, in which we use wide traces, big ground >>> plane and place components tight so reflections matter less (the return >>> time is less than the rising edge of the waveform). Also, I never match >>> impedances for traces. >>> >>> What would your take be? >> >> Why the emphasis on getting 50R transmission line impedance? You can't get all that far away from it. but a wider track with a somewhat lower impedance would give you lower losses, >> > >That is my point exactly. With a small distance, no need to do >simulation in ADS, and reflections will be kept low. > >> A potential problem with an FR4 resin bonded glass fibre board is that the periodicity in the woven glass fibre mesh inserts small regular impedance variations along the track. I've never known it to be a problem, but my narrowest pulse was only 500psec wide, which isn't all that fast. > >Yes, and there is also a small effect on how uniform the copper is. When >it is rolled on, there are mountains and valleys, so the HF signal will >travel longer for small skindepts. The info I have from the manufacturer >is that the valleys are max 10% of the copper thickness. So wont add >much resistance either. >> >> Rogers boards tend to be a lot more uniform, but weaker. >>You can ignore dielectric losses and trace resistance/skin effects in what must be a tiny structure. We do much faster stuff on FR4. This is a modulator, one of 48, for a largish laser. It's all FR4. https://www.dropbox.com/s/29ttap9urihhep1/T500_Top_Final.jpg?raw=1
Reply by ●April 25, 20232023-04-25
On Wednesday, April 26, 2023 at 12:31:35 AM UTC+10, John Larkin wrote:> On Tue, 25 Apr 2023 13:31:13 +0200, Klaus Vestergaard Kragelund > <klau...@hotmail.com> wrote: > > >Hi > > > >We have a GaN FET that is dumping voltage into a capacitor. The GaN > >drain is connected to 50V, and the capacitor is connected on the source > >of the FET. Sort of like this: > > > >https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg > > > >"To load" is connected to a small 50pF capacitor to ground. > > > >We need to pump current into it very fast for reasons I cannot disclose. > >So we turn the high side FET on in about 500ps, and charge the > >capacitor. Pretty basic :-) > Where do you get a gate driver that can turn on a GaN fet in 500 ps? I > need that! A little inductance in series with the gate could help > some. The gate resistor will slow things down. > > Actually, I need to drive a capacitive load, an optical thing, to > maybe 25 volts in 1 ns. Up and down! At 100 MHz! > > I can't disclose the application. Even I'm not allowed to know the > application. Something related to war, maybe. > > I like to use the small EPC parts, the tiny 4-ball things, for stuff > like this, but I've never seen, in real life, the sorts of speeds I > see in Spice.That's probably because you don't bother to put in the small lead inductances that matter at those sorts of speeds.> >We need maximum current into the capacitor, so we are looking to reducing parasitics and losses. > > > >One guy on the team is worried about loss and reflections, treating the > >line from the supply, through the FET and going to the capacitor to > >ground as a transmission line. Wanting to use best possible PCB material > >for low loss (Rogers 4350B), and using ADS to simulate in order to > >optimize the design. He also wants to do it with matched 50ohms > >impedance all the way.> The PCB dielectric won't matter. The part and trace parasitics sure will.The PCB dielectric can matter. The parasitics can be modelled in Spice, but it's tedious work.> >For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed > >is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that > >transmission line impedance comes into play at 1/6 of the wavelength, so > >that's 35mm. So we just need to keep the distance from the decoupling > >caps down to the FET and capacitor path less than 35mm. > > > >The path length is about 10mm. > Envision copper pours, lots of paralleled caps, and very short traces. > > Inductive peaking of the load could help. > > > >About losses, if I compare standard FR4 to Rogers 4350B (good material), > >I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss > >at 10mm path length > > > >https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html > > > >Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. > >I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I > >expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low > >resistance. > > > >I am used to do SMPS design, in which we use wide traces, big ground > >plane and place components tight so reflections matter less (the return > >time is less than the rising edge of the waveform). Also, I never match > >impedances for traces. > > > >What would your take be? > > 50 ohms and 50 pF is a time constant of 2.5 ns. So forget making anything 50 ohms.A 50R transmission line can be terminated with a 50R resistor. If the 50pF is distributed along the transmission line the rules are different.> Your "50 ohm" guy is driven by convention and not thinking. That happens a lot.It's relatively easy to get a transmission line to have an impedance of 50R, and relatively easy to work on them. Going to the trouble of setting up something different does make life more complicated. Thinking about that isn't "not thinking". -- Bill Sloman, Sydhney
Reply by ●April 25, 20232023-04-25
On 25-04-2023 16:31, John Larkin wrote:> On Tue, 25 Apr 2023 13:31:13 +0200, Klaus Vestergaard Kragelund > <klauskvik@hotmail.com> wrote: > >> Hi >> >> We have a GaN FET that is dumping voltage into a capacitor. The GaN >> drain is connected to 50V, and the capacitor is connected on the source >> of the FET. Sort of like this: >> >> https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg >> >> "To load" is connected to a small 50pF capacitor to ground. >> >> We need to pump current into it very fast for reasons I cannot disclose. >> So we turn the high side FET on in about 500ps, and charge the >> capacitor. Pretty basic :-) > > Where do you get a gate driver that can turn on a GaN fet in 500 ps? I > need that! A little inductance in series with the gate could help > some. The gate resistor will slow things down. >LMG1020 https://www.ti.com/product/LMG1020 2 ohms gate resistor> Actually, I need to drive a capacitive load, an optical thing, to > maybe 25 volts in 1 ns. Up and down! At 100 MHz!It's going to have a lot of charge losses, depending on the parasitics of course ;-)> > I can't disclose the application. Even I'm not allowed to know the > application. Something related to war, maybe. > > I like to use the small EPC parts, the tiny 4-ball things, for stuff > like this, but I;ve never seen, in real life, the sorts of speeds I > see in Spice. > > >> >> We need maximum current into the capacitor, so we are looking to >> reducing parasitics and losses. >> >> One guy on the team is worried about loss and reflections, treating the >> line from the supply, through the FET and going to the capacitor to >> ground as a transmission line. Wanting to use best possible PCB material >> for low loss (Rogers 4350B), and using ADS to simulate in order to >> optimize the design. He also wants to do it with matched 50ohms >> impedance all the way. > > The PCB dielectric won't matter. The part and trace parasitics sure > will. > >> >> For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed >> is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that >> transmission line impedance comes into play at 1/6 of the wavelength, so >> that's 35mm. So we just need to keep the distance from the decoupling >> caps down to the FET and capacitor path less than 35mm. >> >> The path length is about 10mm. > > Envision copper pours, lots of paralleled caps, and very short traces. > > Inductive peaking of the load could help. > > > >> >> About losses, if I compare standard FR4 to Rogers 4350B (good material), >> I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss >> at 10mm path length >> >> https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html >> >> Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. >> I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I >> expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low >> resistance. >> >> I am used to do SMPS design, in which we use wide traces, big ground >> plane and place components tight so reflections matter less (the return >> time is less than the rising edge of the waveform). Also, I never match >> impedances for traces. >> >> What would your take be? > > 50 ohms and 50 pF is a time constant of 2.5 ns. So forget making > anything 50 ohms. > > Your "50 ohm" guy is driven by convention and not thinking. That > happens a lot. > >Yeah, my opinion also. Just wanted to hear other input before getting into the nitty gritty with him. He's a good guy, just a little too focused on impedance matching
Reply by ●April 25, 20232023-04-25
On Tuesday, April 25, 2023 at 11:24:11 AM UTC-4, Klaus Vestergaard Kragelund wrote:> On 25-04-2023 16:31, John Larkin wrote: > > On Tue, 25 Apr 2023 13:31:13 +0200, Klaus Vestergaard Kragelund > > <klau...@hotmail.com> wrote: > > > >> Hi > >> > >> We have a GaN FET that is dumping voltage into a capacitor. The GaN > >> drain is connected to 50V, and the capacitor is connected on the source > >> of the FET. Sort of like this: > >> > >> https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Single-High-Side-Driver_Diagram.jpg_1153011823.jpg > >> > >> "To load" is connected to a small 50pF capacitor to ground. > >> > >> We need to pump current into it very fast for reasons I cannot disclose. > >> So we turn the high side FET on in about 500ps, and charge the > >> capacitor. Pretty basic :-) > > > > Where do you get a gate driver that can turn on a GaN fet in 500 ps? I > > need that! A little inductance in series with the gate could help > > some. The gate resistor will slow things down. > > > LMG1020 > > https://www.ti.com/product/LMG1020 > > 2 ohms gate resistor > > Actually, I need to drive a capacitive load, an optical thing, to > > maybe 25 volts in 1 ns. Up and down! At 100 MHz! > It's going to have a lot of charge losses, depending on the parasitics > of course ;-) > > > > I can't disclose the application. Even I'm not allowed to know the > > application. Something related to war, maybe. > > > > I like to use the small EPC parts, the tiny 4-ball things, for stuff > > like this, but I;ve never seen, in real life, the sorts of speeds I > > see in Spice. > > > > > >> > >> We need maximum current into the capacitor, so we are looking to > >> reducing parasitics and losses. > >> > >> One guy on the team is worried about loss and reflections, treating the > >> line from the supply, through the FET and going to the capacitor to > >> ground as a transmission line. Wanting to use best possible PCB material > >> for low loss (Rogers 4350B), and using ADS to simulate in order to > >> optimize the design. He also wants to do it with matched 50ohms > >> impedance all the way. > > > > The PCB dielectric won't matter. The part and trace parasitics sure > > will. > > > >> > >> For a 500ps pulse, the equivalent bandwidth is 700MHz. Propagation speed > >> is 150E6 m/s in FR4, so wavelength is 21cm. Normal rule is that > >> transmission line impedance comes into play at 1/6 of the wavelength, so > >> that's 35mm. So we just need to keep the distance from the decoupling > >> caps down to the FET and capacitor path less than 35mm. > >> > >> The path length is about 10mm. > > > > Envision copper pours, lots of paralleled caps, and very short traces. > > > > Inductive peaking of the load could help. > > > > > > > >> > >> About losses, if I compare standard FR4 to Rogers 4350B (good material), > >> I get 0.06dB/in loss for FR4, and 0.01dB/in for 4350B. So really no loss > >> at 10mm path length > >> > >> https://www.intel.com/content/www/us/en/docs/programmable/683624/current/loss-tangent-and-dissipation-factor.html > >> > >> Additionally, if I use Saturn calculator, for a 2mm wide trace of 10mm. > >> I get 1.5mOhms. Skin depth is 2.5um (7%) on a 35um copper trace, so I > >> expect ac resistance to be about 20mOhm (1.5mOhm/7%). Still very low > >> resistance. > >> > >> I am used to do SMPS design, in which we use wide traces, big ground > >> plane and place components tight so reflections matter less (the return > >> time is less than the rising edge of the waveform). Also, I never match > >> impedances for traces. > >> > >> What would your take be? > > > > 50 ohms and 50 pF is a time constant of 2.5 ns. So forget making > > anything 50 ohms. > > > > Your "50 ohm" guy is driven by convention and not thinking. That > > happens a lot. > > > > > Yeah, my opinion also. Just wanted to hear other input before getting > into the nitty gritty with him. He's a good guy, just a little too > focused on impedance matchingI agree. I've only ever seen impedance matching in signal propagation, not power distribution. In power distribution, it's more a matter of reducing losses and resonances. However, one of the classic mistakes in PDS is assuming you need to treat each power cap as a discrete device, connected to the chip with wires. So people focus on "loop impedance" and such. In reality, the power planes form a transmission line, supplying current to/from the capacitor with distance from the chip being a very small factor. In fact, power planes form resonant structures based on the distances to the edges where reflections occur. But yeah, there's no real math to show treating your 2 x 10 mm connection needs to be analyzed as a transmission line. The point of a transmission line would be to match impedances. What is the impedance of your capacitor? Wouldn't you want to match that to the transmission line, when doing such an analysis? I can't imagine why 50 ohms would be the magic number. This is a case where the loop inductance would be significant, and that means the path from the decoupling cap on the FET drain to the load capacitor. After all, that's where the power is going to come from... that, and the power planes. Why 10 mm? Is that as close as you can get them? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
