This is a 200 watt isolating dc/dc converter: https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 Some idiot who shall not be named figured that we could start it up by ramping up the drive pulse widths from the FPGA, starting very small and eventually making square waves. But even small pulses pull hundreds of amps and have side effects like deconfiguring the FPGA. The fix is to hack in a small board to ramp up the +48 supply, and leave the drive a square wave. https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0
soft-start blunder
Started by ●December 14, 2022
Reply by ●December 14, 20222022-12-14
On Wednesday, December 14, 2022 at 12:02:00 PM UTC-5, John Larkin wrote:> This is a 200 watt isolating dc/dc converter: > > https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 > > Some idiot who shall not be named figured that we could start it up by > ramping up the drive pulse widths from the FPGA, starting very small > and eventually making square waves. But even small pulses pull > hundreds of amps and have side effects like deconfiguring the FPGA.That's actually the best approach BUT you have to be able kill the transformer drive, either both H or both L, otherwise the core keeps integrating voltage and accumulating flux. Doesn't look like you have that capability.> > The fix is to hack in a small board to ramp up the +48 supply, and > leave the drive a square wave. > > https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 > > https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0
Reply by ●December 14, 20222022-12-14
On 14/12/2022 6:44 pm, Fred Bloggs wrote:> > That's actually the best approach BUT you have to be able kill the transformer drive, either both H or both L, otherwise the core keeps integrating voltage and accumulating flux. Doesn't look like you have that capability. >Do the capacitors in series with the primary help prevent that? piglet
Reply by ●December 14, 20222022-12-14
On Wed, 14 Dec 2022 19:43:51 +0000, piglet <erichpwagner@hotmail.com> wrote:>On 14/12/2022 6:44 pm, Fred Bloggs wrote: >> >> That's actually the best approach BUT you have to be able kill the transformer drive, either both H or both L, otherwise the core keeps integrating voltage and accumulating flux. Doesn't look like you have that capability. >> > >Do the capacitors in series with the primary help prevent that? > >pigletThey are there to keep DC current out of the transformer primary. If the half-bridge duty cycles were slightly different, we could have some net DC voltage, and the effective loop resistance is milliohms.
Reply by ●December 14, 20222022-12-14
piglet <erichpwagner@hotmail.com> wrote:> On 14/12/2022 6:44 pm, Fred Bloggs wrote: >> >> That's actually the best approach BUT you have to be able kill the >> transformer drive, either both H or both L, otherwise the core keeps >> integrating voltage and accumulating flux. Doesn't look like you have >> that capability. >> > > Do the capacitors in series with the primary help prevent that? > > pigletSee C10, 2.2uF 250V in the attached file (if it comes through) -- MRM
Reply by ●December 14, 20222022-12-14
Mike Monett VE3BTI <spamme@not.com> wrote:> piglet <erichpwagner@hotmail.com> wrote: > >> On 14/12/2022 6:44 pm, Fred Bloggs wrote: >>> >>> That's actually the best approach BUT you have to be able kill the >>> transformer drive, either both H or both L, otherwise the core keeps >>> integrating voltage and accumulating flux. Doesn't look like you have >>> that capability. >>> >> >> Do the capacitors in series with the primary help prevent that? >> >> piglet > > See C10, 2.2uF 250V in the attached file (if it comes through)Nope, it didn't make it. Sorry -- MRM
Reply by ●December 14, 20222022-12-14
On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:> >This is a 200 watt isolating dc/dc converter: > >https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 > >Some idiot who shall not be named figured that we could start it up by >ramping up the drive pulse widths from the FPGA, starting very small >and eventually making square waves. But even small pulses pull >hundreds of amps and have side effects like deconfiguring the FPGA. > >The fix is to hack in a small board to ramp up the +48 supply, and >leave the drive a square wave. > >https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0For some reason, this simulation shows a -45V Vgs after the positive 7.5V or so Vgs and then ramps back to zero V. Might want a zener Vgs limit. Did you think about adding a simple-ish current limiting stop to the PWM with small value FET source resistor feedback ? Peak current mode. boB> >https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >
Reply by ●December 14, 20222022-12-14
On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:> >This is a 200 watt isolating dc/dc converter: > >https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 > >Some idiot who shall not be named figured that we could start it up by >ramping up the drive pulse widths from the FPGA, starting very small >and eventually making square waves. But even small pulses pull >hundreds of amps and have side effects like deconfiguring the FPGA. > >The fix is to hack in a small board to ramp up the +48 supply, and >leave the drive a square wave. > >https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 > >https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >PWMing a capacitive energy transfer is the actual 'hack', but FPGA deconfiguration is a symptoom that won't go away, just because it was avoided, this time. Need to harden your housekeeping supply and power rail sequencing strategy. RL
Reply by ●December 14, 20222022-12-14
On Wed, 14 Dec 2022 14:49:50 -0800, boB <boB@K7IQ.com> wrote:>On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote: > >> >>This is a 200 watt isolating dc/dc converter: >> >>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >> >>Some idiot who shall not be named figured that we could start it up by >>ramping up the drive pulse widths from the FPGA, starting very small >>and eventually making square waves. But even small pulses pull >>hundreds of amps and have side effects like deconfiguring the FPGA. >> >>The fix is to hack in a small board to ramp up the +48 supply, and >>leave the drive a square wave. >> >>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 > > >For some reason, this simulation shows a -45V Vgs after the positive >7.5V or so Vgs and then ramps back to zero V. Might want a zener Vgs >limit. >Good point. I tested a fet and the gate started conducting around 50 volts and failed after a few seconds. Lots of fets have gate zeners but this one doesn't.>Did you think about adding a simple-ish current limiting stop to the >PWM with small value FET source resistor feedback ? Peak current mode.That might be awkward, given the board layout. This board actually has two of those forward converters, and I can soft-start both with the single ramper thing in the common 48v supply.
Reply by ●December 14, 20222022-12-14
On Wednesday, December 14, 2022 at 9:02:00 AM UTC-8, John Larkin wrote:> Some idiot who shall not be named figured that we could start it up by > ramping up the drive pulse widths from the FPGA, starting very small > and eventually making square waves. But even small pulses pull > hundreds of amps and have side effects like deconfiguring the FPGA.Doesn't sound like a bad idea, really. Have you played with frequency, or just the duty cycle? If a very short duty cycle and very low initial frequency still hose the FPGA, the problem is going to be unwanted coupling somewhere, probably between different power buses. -- john, KE5FX
