Hi all, another circuit fumble on my part. I copied this circuit fragment from whit3rd... part of thread is pasted in below. Here's the circuit I built. https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0 I ground the base of Q2 and added R3 so that it would start out with the HV turned off. D1 was added because I was worried about the zenering Q2's base. (opamp has +/- 15V rails.) Here's a scope shot of the output (AC coupled Chan. 1) and the emitter (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec. https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0 I tried adding R's and or C's here and there in hunt and peck fashion. but without much change. The cycle time is mostly set by the output cap (0.1 uF) and load resistor (100k ohm) Sooo.... Am I doing something stupid, is there some way to fix it, or should I scrap it and start with something else? Thanks George H. *** previous post******** Subject: Re: Abusing the LM386 From: whit3rd <whi...@gmail.com>> Thanks, I need pretty tight control. Some fraction of a volt out of 300. > My brute farce idea looks like this. > https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0A series pass transistor is a less heat-producing option: the level translator Q1 needs HV rating, but the pass transistor Q2 is just to take off the ripple, so 100V should be plenty: <https://www.digikey.com/schemeit/project/hv-in-series-pass-NIHCG7O300F0/> You can embellish it, of course; a collector series resistor//capacitor will share the heatload with Q1, and a source series resistor will limit shortcircuit current. Vbb* (R2/R1) is the gate drive limit. Optos are slow, it's better to draw the milliamp or so from the HV, at 300V. I think. Different, though, if it were 3 kV.
HV control
Started by ●May 10, 2018
Reply by ●May 10, 20182018-05-10
On Thursday, May 10, 2018 at 1:57:30 PM UTC-4, George Herold wrote:> Hi all, another circuit fumble on my part. > I copied this circuit fragment from whit3rd... part of thread is pasted in > below. Here's the circuit I built. > > https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0 > > I ground the base of Q2 and added R3 so that it would start out with the > HV turned off. D1 was added because I was worried about the zenering > Q2's base. (opamp has +/- 15V rails.) > > Here's a scope shot of the output (AC coupled Chan. 1) and the emitter > (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec. > > https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0 > > I tried adding R's and or C's here and there in hunt and peck fashion. > but without much change. The cycle time is mostly set by the output > cap (0.1 uF) and load resistor (100k ohm) > > Sooo.... Am I doing something stupid, is there some way to fix it, or > should I scrap it and start with something else? > > Thanks > George H. > > > > *** previous post******** > > Subject: Re: Abusing the LM386 > From: whit3rd <whi...@gmail.com> > > > Thanks, I need pretty tight control. Some fraction of a volt out of 300. > > My brute farce idea looks like this. > > https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0 > > A series pass transistor is a less heat-producing option: the level > translator Q1 needs HV rating, but the pass transistor Q2 is just to > take off the ripple, so 100V should be plenty: > > <https://www.digikey.com/schemeit/project/hv-in-series-pass-NIHCG7O300F0/> > > You can embellish it, of course; a collector series resistor//capacitor will > share the heatload with Q1, and a source series resistor will limit > shortcircuit current. Vbb* (R2/R1) is the gate drive limit. > > Optos are slow, it's better to draw the milliamp or so from the HV, at 300V. I think. > Different, though, if it were 3 kV.Ughh, I should have been looking at the opamp output. It's railed at +15 and then drops to -15 for ~a few us... I need a more gentle touch somewhere. George H.
Reply by ●May 10, 20182018-05-10
On Thursday, May 10, 2018 at 2:46:12 PM UTC-4, George Herold wrote:> On Thursday, May 10, 2018 at 1:57:30 PM UTC-4, George Herold wrote: > > Hi all, another circuit fumble on my part. > > I copied this circuit fragment from whit3rd... part of thread is pasted in > > below. Here's the circuit I built. > > > > https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0 > > > > I ground the base of Q2 and added R3 so that it would start out with the > > HV turned off. D1 was added because I was worried about the zenering > > Q2's base. (opamp has +/- 15V rails.) > > > > Here's a scope shot of the output (AC coupled Chan. 1) and the emitter > > (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec. > > > > https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0 > > > > I tried adding R's and or C's here and there in hunt and peck fashion. > > but without much change. The cycle time is mostly set by the output > > cap (0.1 uF) and load resistor (100k ohm) > > > > Sooo.... Am I doing something stupid, is there some way to fix it, or > > should I scrap it and start with something else? > > > > Thanks > > George H. > > > > > > > > *** previous post******** > > > > Subject: Re: Abusing the LM386 > > From: whit3rd <whi...@gmail.com> > > > > > Thanks, I need pretty tight control. Some fraction of a volt out of 300. > > > My brute farce idea looks like this. > > > https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0 > > > > A series pass transistor is a less heat-producing option: the level > > translator Q1 needs HV rating, but the pass transistor Q2 is just to > > take off the ripple, so 100V should be plenty: > > > > <https://www.digikey.com/schemeit/project/hv-in-series-pass-NIHCG7O300F0/> > > > > You can embellish it, of course; a collector series resistor//capacitor will > > share the heatload with Q1, and a source series resistor will limit > > shortcircuit current. Vbb* (R2/R1) is the gate drive limit. > > > > Optos are slow, it's better to draw the milliamp or so from the HV, at 300V. I think. > > Different, though, if it were 3 kV. > > Ughh, I should have been looking at the opamp output. It's railed at +15 > and then drops to -15 for ~a few us... > I need a more gentle touch somewhere. > > George H.Snap, I put down the wrong part number for the pfet. It's a VP2450 GH
Reply by ●May 10, 20182018-05-10
You need to close the ac loop and bypass the FET So a cap from the opamp output to the inv input should make it stable Cheers Klaus
Reply by ●May 10, 20182018-05-10
On Thursday, May 10, 2018 at 3:56:36 PM UTC-4, Klaus Kragelund wrote:> You need to close the ac loop and bypass the FET > > So a cap from the opamp output to the inv input should make it stable > > Cheers > > KlausThanks Klaus, I'm pretty sure I tired that. I've got it working now... I ran the npn as common emitter and not common base. That 'flipped' the gain on my opamp, and I stabilized the thing with ~100pF from out to invert input as you suggest. I'm not sure why that didn't work in the other configuration. George H.
Reply by ●May 10, 20182018-05-10
On 05/10/18 13:57, George Herold wrote:> > Hi all, another circuit fumble on my part. > I copied this circuit fragment from whit3rd... part of thread is pasted in > below. Here's the circuit I built. > > https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0 > > I ground the base of Q2 and added R3 so that it would start out with the > HV turned off. D1 was added because I was worried about the zenering > Q2's base. (opamp has +/- 15V rails.) > > Here's a scope shot of the output (AC coupled Chan. 1) and the emitter > (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec. > > https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0 > > I tried adding R's and or C's here and there in hunt and peck fashion. > but without much change. The cycle time is mostly set by the output > cap (0.1 uF) and load resistor (100k ohm) > > Sooo.... Am I doing something stupid, is there some way to fix it, or > should I scrap it and start with something else? > > Thanks > George H. > > > > *** previous post******** > > Subject: Re: Abusing the LM386 > From: whit3rd <whi...@gmail.com> > >> Thanks, I need pretty tight control. Some fraction of a volt out of 300. >> My brute farce idea looks like this. >> https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0 > > A series pass transistor is a less heat-producing option: the level > translator Q1 needs HV rating, but the pass transistor Q2 is just to > take off the ripple, so 100V should be plenty: > > <https://www.digikey.com/schemeit/project/hv-in-series-pass-NIHCG7O300F0/> > > You can embellish it, of course; a collector series resistor//capacitor will > share the heatload with Q1, and a source series resistor will limit > shortcircuit current. Vbb* (R2/R1) is the gate drive limit. > > Optos are slow, it's better to draw the milliamp or so from the HV, at 300V. I think. > Different, though, if it were 3 kV. >Well, you don't have any active pull-down. Looks about like what I'd expect--the output droops about a volt in 250 us, so with 0.1 uF on the output, the load current seems to be about 400 uA. Coincidentally, I'm just doing the BOM for a -250V adjustable APD supply, based on a couple of gate drivers, a 1:1:1 gate transformer, and a 4-stage Cockroft-Walton. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●May 10, 20182018-05-10
On Thu, 10 May 2018 10:57:25 -0700 (PDT), George Herold <gherold@teachspin.com> wrote:> >Hi all, another circuit fumble on my part. >I copied this circuit fragment from whit3rd... part of thread is pasted in >below. Here's the circuit I built. > >https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0 > >I ground the base of Q2 and added R3 so that it would start out with the >HV turned off. D1 was added because I was worried about the zenering >Q2's base. (opamp has +/- 15V rails.) > >Here's a scope shot of the output (AC coupled Chan. 1) and the emitter >(chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec. > >https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0 > >I tried adding R's and or C's here and there in hunt and peck fashion. >but without much change. The cycle time is mostly set by the output >cap (0.1 uF) and load resistor (100k ohm) > >Sooo.... Am I doing something stupid, is there some way to fix it, or >should I scrap it and start with something else? > >Thanks >George H. > > > >*** previous post******** > >Subject: Re: Abusing the LM386 >From: whit3rd <whi...@gmail.com> > >> Thanks, I need pretty tight control. Some fraction of a volt out of 300. >> My brute farce idea looks like this. >> https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0 > >A series pass transistor is a less heat-producing option: the level >translator Q1 needs HV rating, but the pass transistor Q2 is just to >take off the ripple, so 100V should be plenty:Assuming it's avalanche rated.> ><https://www.digikey.com/schemeit/project/hv-in-series-pass-NIHCG7O300F0/> > >You can embellish it, of course; a collector series resistor//capacitor will >share the heatload with Q1, and a source series resistor will limit >shortcircuit current. Vbb* (R2/R1) is the gate drive limit. > >Optos are slow, it's better to draw the milliamp or so from the HV, at 300V. I think. >Different, though, if it were 3 kV.Is that a protected-gate mosfet? Some conditions could put 300 volts s-g. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●May 10, 20182018-05-10
George Herold <gherold@teachspin.com> wrote:> Hi all, another circuit fumble on my part. > I copied this circuit fragment from whit3rd... part of thread is pasted > in below. Here's the circuit I built.> https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0> I ground the base of Q2 and added R3 so that it would start out with the > HV turned off. D1 was added because I was worried about the zenering > Q2's base. (opamp has +/- 15V rails.)> Here's a scope shot of the output (AC coupled Chan. 1) and the emitter > (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec.> https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0> I tried adding R's and or C's here and there in hunt and peck fashion. > but without much change. The cycle time is mostly set by the output > cap (0.1 uF) and load resistor (100k ohm)> Sooo.... Am I doing something stupid, is there some way to fix it, or > should I scrap it and start with something else?> Thanks > George H.You are running the op amp wide open. Too much gain. Remove R4 (10k) from the positive input of the op amp. Insert it in series with the negative input. Add an integrating cap from the output pin to the negative input. Look at the step response. Start with 1uF, reduce the value until it starts to fail. Maybe add a small resistor (1k) in series with the cap if you want a faster response. This circuit would be ideal to analyze in LTspice.
Reply by ●May 10, 20182018-05-10
1. Vref has a series resistor, and you put an R+C from opamp output to -in, right? :-o 2. You've got a gain of 1.5 with the level shifter, which is alright. As others mentioned, Q1 could stand a zener. 3. No current limiting whatsoever. In fact... 4. The PMOS is wide freaking open. What gain is it operating at? Who knows! Datasheet looks like it's down in the subthreshold region, where Id ~ exp(Vgs-Vpo), maybe 100mS tops, at the current shown. But it goes way up from there at higher Id, and there's nothing to prevent excessive Id. If the gain is 100mS and the load is, say, 200V / 10mA = 20k, the gain is around 2000. Add to that, the single pole of 0.1uF * 20kR = 2ms, and you've got 2000 times more gain, and less than 0 degrees of phase margin, around that poor opamp! (Remember, you only have 90 degrees to spare, and you lose all of those where the 0.1uF looks like an ideal integrator.) One more crinkle: match up the opamp's output range with the level shifter's range. If it's swinging +/-15V, divide it down to -15V instead of 0V, so that Q2's emitter range is -7.5 to 0V (or rather, the Thevenin output from the divider). Or slightly up to ensure an off-biased state. Using the same principle (matching operating ranges), Q1 should have a source resistor (fixing its gain ~constant, except near cutoff), and R1 could have some idle bias in it so there's minimal deadband coming up from cutoff. As long as you don't mind a fairly high dropout voltage (about 10V for R1-R3 as shown), current limiting is also automatic: it's never higher than (V(R1) + Vgs(th)) over (source resistor). A zener, to enforce V(R1) maximum, provides further assurance of this. With these changes, it's easy to see the block diagram equivalent: Q1-Q2 is a transconductance source, current proportional to opamp output; the 0.1 and the load is the "plant", a simple single-order one, so an R+C compensation network allows full freedom to set a 2nd order control loop of desired damping. Oh, check the gate-R1 time constant, too. If it's too slow, you have another pole in the loop (and don't forget Miller effect!), and you won't be able to stabilize it anywhere near as fast as the output capacitance would suggest. Make sure this is less than 1/3 the load or controller time constant. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/ "George Herold" <gherold@teachspin.com> wrote in message news:f086a724-cd0e-45dc-ad46-7cfa3bc8cc45@googlegroups.com...> > Hi all, another circuit fumble on my part. > I copied this circuit fragment from whit3rd... part of thread is pasted in > below. Here's the circuit I built. > > https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0 > > I ground the base of Q2 and added R3 so that it would start out with the > HV turned off. D1 was added because I was worried about the zenering > Q2's base. (opamp has +/- 15V rails.) > > Here's a scope shot of the output (AC coupled Chan. 1) and the emitter > (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec. > > https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0 > > I tried adding R's and or C's here and there in hunt and peck fashion. > but without much change. The cycle time is mostly set by the output > cap (0.1 uF) and load resistor (100k ohm) > > Sooo.... Am I doing something stupid, is there some way to fix it, or > should I scrap it and start with something else? > > Thanks > George H. > > > > *** previous post******** > > Subject: Re: Abusing the LM386 > From: whit3rd <whi...@gmail.com> > >> Thanks, I need pretty tight control. Some fraction of a volt out of >> 300. >> My brute farce idea looks like this. >> https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0 > > A series pass transistor is a less heat-producing option: the level > translator Q1 needs HV rating, but the pass transistor Q2 is just to > take off the ripple, so 100V should be plenty: > > <https://www.digikey.com/schemeit/project/hv-in-series-pass-NIHCG7O300F0/> > > You can embellish it, of course; a collector series resistor//capacitor > will > share the heatload with Q1, and a source series resistor will limit > shortcircuit current. Vbb* (R2/R1) is the gate drive limit. > > Optos are slow, it's better to draw the milliamp or so from the HV, at > 300V. I think. > Different, though, if it were 3 kV.
Reply by ●May 10, 20182018-05-10
George Herold <gherold@teachspin.com> wrote:> On Thursday, May 10, 2018 at 3:56:36 PM UTC-4, Klaus Kragelund wrote: >> You need to close the ac loop and bypass the FET>> So a cap from the opamp output to the inv input should make it stable>> Cheers>> Klaus> Thanks Klaus, I'm pretty sure I tired that. > I've got it working now... I ran the npn as common emitter and > not common base. That 'flipped' the gain on my opamp, and I > stabilized the thing with ~100pF from out to invert input as > you suggest. I'm not sure why that didn't work in the other > configuration.> George H.This is exactly the kind of thing well suited for LTspice. You can try different configurations much faster than with hand soldering. You can see the open loop gain and margins which you cannot see on a breadboard. You can view the step response which is difficult on a breadbard. You can look for overstressed components which may be difficult with an oscilloscope. You can see glitches that may be impossible on a scope. LTspice is an amazing tool. It has a huge learning curve, but there is an abundance of help available. It is an excellent way to document circuits so 6 months later when you have forgotten how something works, you can refresh instantly. You can also post your circuits to sed and gain significant suggestions on improvements or changes. You can solve problems much faster and gain a deeper insight into how a circuit works than with any other method.
