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Serial Peripheral Interface. Master/Slave with FIFO

Started by Ali23 5 months ago1 replylatest reply 5 months ago28 views

Dear Forum participants,

I am working on an implementation SPI hardware interface in VIVADO. I have already read a lot of basic information about it.

My plan

The bus is configured as a 3 wire interface as far: clkdata_in and cs ( clock, input data and chip select, respectively). I add two FIFO ( one receives 8 bits and sends to the second one) block and blocks for a bit counter and bit selection. If the second FIFO is full, bit selection block will start a filling with a new 8 bits.

Have I smth missed? What should I add to this realisation?

Does anyone have a reference how SPI could be realised for receive data ?



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Reply by denniscMay 27, 2021

Try a Google search for "Verilog SPI slave". The first few hits lead to example SPI implementations.