wide edge decoder

I've read several references to this, but no definition. What is it?

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Defund the Thought Police 

On Sunday, January 1, 2023 at 10:48:43 PM UTC-5, Tom Del Rosso wrote:
> I've read several references to this, but no definition. What is it? 
> 
> -- 
> Defund the Thought Police

Wide Edge Decoders
Dedicated circuitry boosts the performance of wide decoding functions . When the address or data field is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000E-family CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. An XC4000E FPGA has four programmable decoders located on each edge of the device. The inputs to each decoder are any of the I1 signals on that edge plus one local interconnect per CLB row or column. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to the AND term in typical PAL devices.

http://xilinx.pe.kr/_xilinx/html/ref/fpga4000.html#:~:text=Goto%20TOP-,Wide%20Edge%20Decoders,are%20thus%20slower%20than%20PALs.

On Monday, January 2, 2023 at 12:33:59 PM UTC-5, Fred Bloggs wrote:
> On Sunday, January 1, 2023 at 10:48:43 PM UTC-5, Tom Del Rosso wrote: 
> > I've read several references to this, but no definition. What is it? 
> > 
> > -- 
> > Defund the Thought Police
> Wide Edge Decoders 
> Dedicated circuitry boosts the performance of wide decoding functions . When the address or data field is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000E-family CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. An XC4000E FPGA has four programmable decoders located on each edge of the device. The inputs to each decoder are any of the I1 signals on that edge plus one local interconnect per CLB row or column. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to the AND term in typical PAL devices. 
> 
> http://xilinx.pe.kr/_xilinx/html/ref/fpga4000.html#:~:text=Goto%20TOP-,Wide%20Edge%20Decoders,are%20thus%20slower%20than%20PALs.

That's a blast from the past.  I had forgotten all about them.  I still remember the internal tristate drivers and "long lines", even though they haven't been in a new FPGA design, for probably 20 years. 

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Rick C.

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