On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>s�ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> wrote: >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> > >> >> My question was, why make a sine wave if the final result is a digital >> >> clock? >> > >> >Do you want the digital clock edges to be synchronous with an existing source, or >> >asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component. >> Of course. The analog components are dac, filter, comparator. >> >> I want a programmable internal trigger rate for a pulse generator. >> >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >> up to Nyquist. But it gets messy at low frequencies where the dac is >> incremented infrequently and the filter doesn't do much. > >if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff >That has problems too. We were thinking that you could gain-up and clip the sine wave to increase the zero-cross slope. The logical end of that is to make a trapezoid with a steep rise. The DAC lsb increments rarely at low frequencies, so magically include some lower phase accumulator bits to effectively increase the DAC sample rate on that steep slope. Digitally interpolate. One way to get low trigger rates, which we do now, is synthesize an octave or so at the high end of the DDS and divide after the comparator. That has uglies if the DDS is slow to program, like an SPI interface. It's not so awful if we make our own DDS in an FPGA, so we can change the DDS frequency and the divisor (almost) simultaneously. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
DDS questions
Started by ●August 7, 2022
Reply by ●August 7, 20222022-08-07
Reply by ●August 7, 20222022-08-07
On Sun, 7 Aug 2022 22:37:41 +0200, Gerhard Hoffmann <dk4xp@arcor.de> wrote:>Am 07.08.22 um 21:53 schrieb John Larkin: >> On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de> >> wrote: >> >>> Am 07.08.22 um 19:57 schrieb John Larkin: >>> >>> >>>> My question was, why make a sine wave if the final result is a digital >>>> clock? >>> >>> You can get by with a counter if you are happy with an exact subharmonic >>> of the clock source. >>> >>> Trying to build a DDS without a sine table is like shooting >>> oneself into both feet and then enjoying the feeling as the >>> proud winner of the filtering wheelchair championchip. >> >> What advantage does a sine table have over making a sawtooth directly >> from the MSBs of the phase accumulator? The sine conversion just adds >> errors, seems to me. >> >> Near the zero crossing, the filter can't tell them apart. The >> comparator isn't very smart. > >A sine is nowhere steeper than at the zero crossing. >The essence of the Collins paper is that it takes several >pairs of (filter + amplifier) in cascade, not a dumb comparator. > >Talking of comparators, I just got quite disappointing results >from an ADCMP580, CML. > >~70 ps rise and fall time, should be half of that, typ. > >rising edge, falling edge is abt. the same: >< >https://www.flickr.com/photos/137684711@N07/52270474769/in/dateposted-public/You are signal averaging. Could the problem be jitter?> > > >entire cycle: >< >https://www.flickr.com/photos/137684711@N07/52269244147/in/dateposted-public/ > > > > >GerhardMy inventory report includes the 580, with the note DECIDED TO NOT USE PART. I can't remember why. We do use the 582. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 7, 20222022-08-07
søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > >sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >> wrote: > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >> > > >> >> My question was, why make a sine wave if the final result is a digital > >> >> clock? > >> > > >> >Do you want the digital clock edges to be synchronous with an existing source, or > >> >asynchronous? Mathematically, the creation of an asynchronous clock is > >> >not gonna happen in clocked logic circuitry, it has to have an analog component. > >> Of course. The analog components are dac, filter, comparator. > >> > >> I want a programmable internal trigger rate for a pulse generator. > >> > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >> up to Nyquist. But it gets messy at low frequencies where the dac is > >> incremented infrequently and the filter doesn't do much. > > > >if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff > > > That has problems too. > > We were thinking that you could gain-up and clip the sine wave to > increase the zero-cross slope. The logical end of that is to make a > trapezoid with a steep rise.keep decreasing the rise time and you get back to a squarewave a sine is probably some kind of optimum> The DAC lsb increments rarely at low frequencies, so magically include > some lower phase accumulator bits to effectively increase the DAC > sample rate on that steep slope. Digitally interpolate.but if the DAC can't run any faster or have any more bits, how?
Reply by ●August 7, 20222022-08-07
On Sunday, August 7, 2022 at 1:52:07 PM UTC-7, John Larkin wrote:> The DAC lsb increments rarely at low frequencies, so magically include > some lower phase accumulator bits to effectively increase the DAC > sample rate on that steep slope. Digitally interpolate.That's actually a good way to visualize the problem. You don't care about the peak, you care about the zero crossings. At frequencies where the LSBs toggle less often, the resulting phase error will corrupt the zero crossing points at low offset frequencies. You can't fix this with a filter, only with a DAC. Try it and you'll see (as I did, back when the HI5731 DAC was the SotA and I didn't have one in the parts drawer.) The ugliness of the output that you will get from the MSB by itself is hard to exaggerate. -- john, KE5FX
Reply by ●August 7, 20222022-08-07
On Sun, 7 Aug 2022 14:53:39 -0700 (PDT), "John Miles, KE5FX" <jmiles@gmail.com> wrote:>On Sunday, August 7, 2022 at 1:52:07 PM UTC-7, John Larkin wrote: >> The DAC lsb increments rarely at low frequencies, so magically include >> some lower phase accumulator bits to effectively increase the DAC >> sample rate on that steep slope. Digitally interpolate. > >That's actually a good way to visualize the problem. You don't care >about the peak, you care about the zero crossings. At frequencies >where the LSBs toggle less often, the resulting phase error will corrupt >the zero crossing points at low offset frequencies. You can't fix this >with a filter, only with a DAC. > >Try it and you'll see (as I did, back when the HI5731 DAC was the SotA >and I didn't have one in the parts drawer.) The ugliness of the output >that you will get from the MSB by itself is hard to exaggerate. > >-- john, KE5FXAnywhere near Nyquist, the DAC output is ghastly. It looks like random noise, hard to see anything coherent on a scope. But after a good filter, it becomes a beautiful sine wave. If you flip the impulse response of a lowpass filter (like doing convolution) it shows how much the filter remembers, how much it looks back in time. My proposed sawtooth has a sharp jump that a sine wave doesn't. If the filter has forgotten the jump, the sawtooth is ideal. If not, the soft history of a sine wave might be better. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 7, 20222022-08-07
On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:> ... My proposed sawtooth has a sharp jump that a sine wave > doesn't. If the filter has forgotten the jump, the sawtooth is ideal. > If not, the soft history of a sine wave might be better.But, doesn't the 'sharp jump' have synchrony with a clock edge? And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered power supply? The sinewave is cleaner to drive, and less insistent on knowledge of dispersion in the dielectric materials. As others have pointed out, that's why wiring time delays are precise only with sinewaves: no hook there.
Reply by ●August 7, 20222022-08-07
On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote: > >> ... My proposed sawtooth has a sharp jump that a sine wave >> doesn't. If the filter has forgotten the jump, the sawtooth is ideal. >> If not, the soft history of a sine wave might be better. > >But, doesn't the 'sharp jump' have synchrony with a clock edge?Sure. The dds DAC is clocked by the main clock. Every dac output point is clocked.>And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered >power supply? The sinewave is cleaner to drive, and less insistent on knowledge >of dispersion in the dielectric materials. As others have pointed out, >that's why wiring time delays are precise only with sinewaves: no hook there.We are in the picosecond timing business. We use sub-ns edges for clocks and events. We don't use sine waves! -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 7, 20222022-08-07
On Sunday, August 7, 2022 at 4:52:07 PM UTC-4, John Larkin wrote:> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > >sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >> wrote: > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >> > > >> >> My question was, why make a sine wave if the final result is a digital > >> >> clock? > >> > > >> >Do you want the digital clock edges to be synchronous with an existing source, or > >> >asynchronous? Mathematically, the creation of an asynchronous clock is > >> >not gonna happen in clocked logic circuitry, it has to have an analog component. > >> Of course. The analog components are dac, filter, comparator. > >> > >> I want a programmable internal trigger rate for a pulse generator. > >> > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >> up to Nyquist. But it gets messy at low frequencies where the dac is > >> incremented infrequently and the filter doesn't do much. > > > >if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff > > > That has problems too. > > We were thinking that you could gain-up and clip the sine wave to > increase the zero-cross slope. The logical end of that is to make a > trapezoid with a steep rise.Making the trapezoid from the NCO output is not the same as making a sine wave and filtering. The "logical end" of that is actually generating a square wave with all the attendant jitter. So the trapezoid would increase the jitter and be harder to filter than the sine wave.> The DAC lsb increments rarely at low frequencies, so magically include > some lower phase accumulator bits to effectively increase the DAC > sample rate on that steep slope. Digitally interpolate.You must have enough phase bits to prevent phase noise since this produces, hard to filter (meaning impossible) close in spurs.> One way to get low trigger rates, which we do now, is synthesize an > octave or so at the high end of the DDS and divide after the > comparator. That has uglies if the DDS is slow to program, like an SPI > interface. It's not so awful if we make our own DDS in an FPGA, so we > can change the DDS frequency and the divisor (almost) simultaneously.Yup. Is there some reason you can't piggy back on the SPI protocol to add bits to control your octave divider? -- Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209
Reply by ●August 7, 20222022-08-07
On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:> We are in the picosecond timing business. We use sub-ns edges for > clocks and events. We don't use sine waves!Around here, picosecond-level errors mean that somebody (i.e., me) is going to have a bad day at the (proverbial) office. :) -- john, KE5FX
Reply by ●August 7, 20222022-08-07
On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote: > >> ... My proposed sawtooth has a sharp jump that a sine wave >> doesn't. If the filter has forgotten the jump, the sawtooth is ideal. >> If not, the soft history of a sine wave might be better. > >But, doesn't the 'sharp jump' have synchrony with a clock edge? >And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered >power supply? The sinewave is cleaner to drive, and less insistent on knowledge >of dispersion in the dielectric materials. As others have pointed out, >that's why wiring time delays are precise only with sinewaves: no hook there.The power supply isn't an issue. All sorts of things are whacking the power supply. But if we make a sawtooth that ramps from -V to +V, and we filter that, the big negative spike happens at the input clock rate, so wobbles the zero crossing and makes jitter. The filter isn't perfect so doesn't forget the big negative step in half the sawtooth time. So move the comparator trigger level up, to 0.9V instead of zero, and that gives the filter almost twice the time to forget. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
