DDS questions

On Sun, 7 Aug 2022 19:07:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

>Am 07.08.22 um 15:55 schrieb John Larkin:
>
>> Why do the sine lookup? The ms D bits of the accumulator are a
>> triangle waveform. Why not DAC and filter that? The lowpass filter
>> wouldn't know... it would interpolate as usual.
>> 
>> Why not use some clever VHDL and make a trapezoid with faster rise
>> time, especially at low frequencies where time quantization and
>> comparator errors make a lot of period jitter and the filter doesn't
>> interpolate.
>> 
>> If one just takes the MSB of the phase accumulator, you have a
>> programmable-frequency clock without all that other junk. But its
>> period is quantized to the clock, which gets totally ugly at high
>> frequencies. I wonder if some clever math could make that output
>> always some perfect multiple of, say 1 Hz or 1 mHz.
>
>There was a DDS from Stanford Telecom (Standard? T.) that was
>BCD and that thusly could produce exact mHz from 10 MHz etc.

We discussed a radix-10 phase accumulator. That's not awful.

>
>Just using the MSB would inherit awful phase modulation / noise.

The MSB is the exact average programmed frequency but has one clock of
p-p jitter. 

>
>I have published a sine table on opencores.org with a
>DDS as test bed. It stores only one quarter of the circle and
>mirrors the rest. Table size is generic and taken automagically
>from the connected busses. 0 up to 10 pipeline registers may be
>selected and are strategically inserted as food for the register
>balancer.
>
>Without any work it ran at 230 MHz on a Spartan6 eval board,
>just by asking for 250 MHz. I needed only 200 MHz.
>Sine and cosine are available at no extra table cost to feed
>the multipliers of a complex mixer.
>
>It is pure VHDL that does not lock you into a silicon vendor.
>
>< https://opencores.org/projects/sincos   >
>
>Cordic was ruled out for me because of its delays.
>It is hard to get a digital Costas loop stable when
>it takes a year for the oscillator to follow and it's
>staggering around in the mean time after a frequency change.
>
>Cheers, Gerhard
>
>

My question was, why make a sine wave if the final result is a digital
clock?



-- 

John Larkin         Highland Technology, Inc   trk

The cork popped merrily, and Lord Peter rose to his feet.  
"Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

> My question was, why make a sine wave if the final result is a digital 
> clock?

Do you want the digital clock edges  to be synchronous with an existing source, or
asynchronous?  Mathematically, the creation of an asynchronous clock is 
not gonna happen in clocked logic circuitry, it has to have an analog component.

Am 07.08.22 um 19:57 schrieb John Larkin:


> My question was, why make a sine wave if the final result is a digital
> clock?

You can get by with a counter if you are happy with an exact subharmonic 
of the clock source.

Trying to build a DDS without a sine table is like shooting
oneself into both feet and then enjoying the feeling as the
proud winner of the filtering wheelchair championchip.

I said it here 2 or 3 years ago that the cleanest time stamp
is a sine zero crossing and maybe a qualifier.
No dispersion, minimum noise bandwidth.


Least jitter sine -> square conversion:

Oliver Collins, Member, IEEE
The Design of Low Jitter Hard Limiters
IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 44, NO. 5, MAY 1996

It resurfaces now & then in the time nuts list on febo.com.


 >> Cheers, Gerhard

On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:
>
>> My question was, why make a sine wave if the final result is a digital 
>> clock?
>
>Do you want the digital clock edges  to be synchronous with an existing source, or
>asynchronous?  Mathematically, the creation of an asynchronous clock is 
>not gonna happen in clocked logic circuitry, it has to have an analog component.

Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn't do much.

-- 

John Larkin         Highland Technology, Inc   trk

The cork popped merrily, and Lord Peter rose to his feet.  
"Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

>Am 07.08.22 um 19:57 schrieb John Larkin:
>
>
>> My question was, why make a sine wave if the final result is a digital
>> clock?
>
>You can get by with a counter if you are happy with an exact subharmonic 
>of the clock source.
>
>Trying to build a DDS without a sine table is like shooting
>oneself into both feet and then enjoying the feeling as the
>proud winner of the filtering wheelchair championchip.

What advantage does a sine table have over making a sawtooth directly
from the MSBs of the phase accumulator? The sine conversion just adds
errors, seems to me.

Near the zero crossing, the filter can't tell them apart. The
comparator isn't very smart.



-- 

John Larkin         Highland Technology, Inc   trk

The cork popped merrily, and Lord Peter rose to his feet.  
"Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

On Sunday, August 7, 2022 at 3:53:55 PM UTC-4, John Larkin wrote:
> On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk...@arcor.de> 
> wrote:
> >Am 07.08.22 um 19:57 schrieb John Larkin: 
> > 
> > 
> >> My question was, why make a sine wave if the final result is a digital 
> >> clock? 
> > 
> >You can get by with a counter if you are happy with an exact subharmonic 
> >of the clock source. 
> > 
> >Trying to build a DDS without a sine table is like shooting 
> >oneself into both feet and then enjoying the feeling as the 
> >proud winner of the filtering wheelchair championchip.
> What advantage does a sine table have over making a sawtooth directly 
> from the MSBs of the phase accumulator? The sine conversion just adds 
> errors, seems to me. 
> 
> Near the zero crossing, the filter can't tell them apart. The 
> comparator isn't very smart.

What a myopic view.  The most difficult part of designing a DDS, is the phase truncation error which produces close in spurs, which can not be effectively filtered.  

Whatever.  In many ways, Larkin is like many others here who come for expert advice, then ignore it when they don't understand it.  It would be so much more productive if he would ask relevant questions instead of trying to think in terms that don't apply like localizing the action of a filter to a small segment of the waveform, when filters are typically IIR and so reflect a history of the signal.  

-- 

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> 
> wrote:
> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: 
> > 
> >> My question was, why make a sine wave if the final result is a digital 
> >> clock? 
> > 
> >Do you want the digital clock edges to be synchronous with an existing source, or 
> >asynchronous? Mathematically, the creation of an asynchronous clock is 
> >not gonna happen in clocked logic circuitry, it has to have an analog component.
> Of course. The analog components are dac, filter, comparator. 
> 
> I want a programmable internal trigger rate for a pulse generator. 
> 
> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, 
> up to Nyquist. But it gets messy at low frequencies where the dac is 
> incremented infrequently and the filter doesn't do much.

Sounds like an application for dithering.  

-- 

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209 

søndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> 
> wrote:
> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: 
> > 
> >> My question was, why make a sine wave if the final result is a digital 
> >> clock? 
> > 
> >Do you want the digital clock edges to be synchronous with an existing source, or 
> >asynchronous? Mathematically, the creation of an asynchronous clock is 
> >not gonna happen in clocked logic circuitry, it has to have an analog component.
> Of course. The analog components are dac, filter, comparator. 
> 
> I want a programmable internal trigger rate for a pulse generator. 
> 
> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, 
> up to Nyquist. But it gets messy at low frequencies where the dac is 
> incremented infrequently and the filter doesn't do much.

if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff 

Am 07.08.22 um 21:53 schrieb John Larkin:
> On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
> wrote:
> 
>> Am 07.08.22 um 19:57 schrieb John Larkin:
>>
>>
>>> My question was, why make a sine wave if the final result is a digital
>>> clock?
>>
>> You can get by with a counter if you are happy with an exact subharmonic
>> of the clock source.
>>
>> Trying to build a DDS without a sine table is like shooting
>> oneself into both feet and then enjoying the feeling as the
>> proud winner of the filtering wheelchair championchip.
> 
> What advantage does a sine table have over making a sawtooth directly
> from the MSBs of the phase accumulator? The sine conversion just adds
> errors, seems to me.
> 
> Near the zero crossing, the filter can't tell them apart. The
> comparator isn't very smart.

A sine is nowhere steeper than at the zero crossing.
The essence of the Collins paper is that it takes several
pairs of (filter + amplifier) in cascade, not a dumb comparator.

Talking of comparators, I just got quite disappointing results
from an ADCMP580, CML.

~70 ps rise and fall time, should be half of that, typ.

rising edge, falling edge is abt. the same:
< 
https://www.flickr.com/photos/137684711@N07/52270474769/in/dateposted-public/ 
   >

entire cycle:
< 
https://www.flickr.com/photos/137684711@N07/52269244147/in/dateposted-public/ 
  >


Gerhard

Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

> The essence of the Collins paper is that it takes several
> pairs of (filter + amplifier) in cascade, not a dumb comparator.

I forgot:

The filters have to be tighter from stage to stage.
There is an optimum.
In the time nuts archives, there is a spreadsheet
that computes the number of stages, gain per stage
and bandwidth.

> Gerhard