This uses an FPGA LVDS input as a comparator, and one external RC, to make an ADC. Just need an algorithm to process the flop output. A simpler ADC should be possible. Version 4 SHEET 1 880 680 WIRE -16 0 -112 0 WIRE 48 0 -16 0 WIRE 160 0 48 0 WIRE 416 0 240 0 WIRE 480 0 416 0 WIRE 528 0 480 0 WIRE 416 48 416 0 WIRE -112 64 -112 0 WIRE 96 112 64 112 WIRE 128 112 96 112 WIRE -112 160 -112 128 WIRE 64 160 64 112 WIRE -16 176 -16 0 WIRE 16 176 -16 176 WIRE -48 224 -112 224 WIRE 16 224 -48 224 WIRE -112 256 -112 224 WIRE 64 272 64 240 WIRE 272 288 208 288 WIRE 368 288 368 224 WIRE 368 288 272 288 WIRE 416 288 416 224 WIRE 480 288 416 288 WIRE 512 288 480 288 WIRE 208 336 208 288 WIRE 416 336 416 288 WIRE -112 384 -112 336 WIRE 208 448 208 416 WIRE 416 448 416 416 FLAG 416 448 0 FLAG 208 448 0 FLAG 64 272 0 FLAG 96 112 R FLAG -112 384 0 FLAG -112 160 0 FLAG 272 288 D FLAG 480 288 CLK FLAG 480 0 N FLAG 48 0 F FLAG -48 224 IN SYMBOL voltage -112 240 R0 WINDOW 0 48 44 Left 2 WINDOW 3 41 78 Left 2 SYMATTR InstName V1 SYMATTR Value 0.75 SYMBOL Digital\\dflop 320 144 R270 WINDOW 0 40 -49 VRight 2 SYMATTR InstName A1 SYMBOL voltage 416 320 R0 WINDOW 0 56 49 Left 2 WINDOW 3 45 90 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value PULSE(0 1 0 0 0 1u 10u 1e6) SYMBOL bv 208 320 R0 WINDOW 0 -97 53 Left 2 WINDOW 3 -212 93 Left 2 SYMATTR InstName B1 SYMATTR Value V=1+tanh(V(R)) SYMBOL e 64 144 R0 WINDOW 0 53 50 Left 2 WINDOW 3 54 84 Left 2 SYMATTR InstName Elvds SYMATTR Value 1000 SYMBOL res 256 -16 R90 WINDOW 0 65 53 VBottom 2 WINDOW 3 69 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10K SYMBOL cap -128 64 R0 WINDOW 0 46 12 Left 2 WINDOW 3 45 48 Left 2 SYMATTR InstName C1 SYMATTR Value 1� TEXT 558 200 Left 2 !.tran 10m TEXT 512 80 Left 2 ;Cheap FPGA ADC TEXT 528 128 Left 2 ;JL Jan 17 2022 -- I yam what I yam - Popeye
cheap ADC
Started by ●January 20, 2022
Reply by ●January 20, 20222022-01-20
torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com:> This uses an FPGA LVDS input as a comparator, and one external RC, to > make an ADC. Just need an algorithm to process the flop output. > > A simpler ADC should be possible. >more than one way to do it, one is basically successive approximation with a pwm dac another is delta-sigma with RC as "integrator" that might have an advantage in that the comparator doesn't follow the input signal it is always ~1/2 Vcc Version 4 SHEET 1 1316 680 WIRE -96 -992 -176 -992 WIRE -176 -960 -176 -992 WIRE 496 -832 -320 -832 WIRE -96 -752 -96 -992 WIRE -96 -752 -128 -752 WIRE -128 -720 -128 -752 WIRE -96 -720 -96 -752 WIRE -320 -688 -320 -752 WIRE -304 -688 -320 -688 WIRE -144 -688 -304 -688 WIRE -16 -672 -64 -672 WIRE -144 -656 -480 -656 WIRE -16 -656 -16 -672 WIRE 192 -656 -16 -656 WIRE 192 -640 192 -656 WIRE 272 -640 192 -640 WIRE 496 -640 496 -832 WIRE 496 -640 432 -640 WIRE 752 -640 496 -640 WIRE 912 -640 832 -640 WIRE -304 -624 -304 -688 WIRE 272 -592 208 -592 WIRE -128 -576 -128 -624 WIRE -96 -576 -96 -624 WIRE -96 -576 -128 -576 WIRE 912 -576 912 -640 WIRE -304 -528 -304 -560 WIRE 208 -512 208 -592 WIRE 912 -464 912 -512 WIRE 208 -368 208 -432 WIRE -96 -224 -176 -224 WIRE -176 -192 -176 -224 WIRE 496 -64 -320 -64 WIRE -96 16 -96 -224 WIRE -96 16 -128 16 WIRE -128 48 -128 16 WIRE -96 48 -96 16 WIRE -144 80 -176 80 WIRE -16 96 -64 96 WIRE -480 112 -480 -656 WIRE -416 112 -480 112 WIRE -320 112 -320 16 WIRE -320 112 -336 112 WIRE -304 112 -320 112 WIRE -144 112 -304 112 WIRE -16 112 -16 96 WIRE 192 112 -16 112 WIRE -480 128 -480 112 WIRE 192 128 192 112 WIRE 272 128 192 128 WIRE 752 128 432 128 WIRE 912 128 832 128 WIRE -304 144 -304 112 WIRE 272 176 208 176 WIRE 496 176 496 -64 WIRE 496 176 448 176 WIRE -128 192 -128 144 WIRE -96 192 -96 144 WIRE -96 192 -128 192 WIRE 912 192 912 128 WIRE -304 240 -304 208 WIRE 208 256 208 176 WIRE -176 272 -176 80 WIRE 912 304 912 256 WIRE -480 384 -480 208 WIRE 208 400 208 336 FLAG -480 384 0 FLAG 272 224 0 FLAG 208 400 0 FLAG -304 240 0 FLAG 912 304 0 FLAG -176 -112 0 FLAG -128 192 0 FLAG -176 352 0 FLAG 272 -544 0 FLAG 208 -368 0 FLAG -304 -528 0 FLAG 912 -464 0 FLAG -176 -880 0 FLAG -128 -576 0 FLAG -480 -656 Vin FLAG 912 -640 Vout1 FLAG 912 128 Vout2 SYMBOL voltage -480 112 R0 WINDOW 3 -226 54 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value SINE(1.5 1.4 5000) SYMATTR InstName V1 SYMBOL Digital\\dflop 352 80 R0 WINDOW 3 8 12 Left 2 SYMATTR Value vhigh=3 SYMATTR InstName A1 SYMBOL res -320 96 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL res -336 -80 R0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL cap -288 208 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL res 848 112 R90 WINDOW 0 80 54 VBottom 2 WINDOW 3 89 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1K SYMBOL cap 896 192 R0 WINDOW 0 -58 48 Left 2 WINDOW 3 -56 80 Left 2 SYMATTR InstName C3 SYMATTR Value 8n SYMBOL Comparators\\LT1715 -112 96 R0 SYMATTR InstName U1 SYMBOL voltage -176 -208 R0 WINDOW 3 -64 56 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value 5 SYMATTR InstName V2 SYMBOL voltage -176 256 R0 WINDOW 3 -64 56 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value 1.5 SYMATTR InstName V4 SYMBOL Digital\\dflop 352 -688 R0 WINDOW 3 8 12 Left 2 SYMATTR Value vhigh=3 SYMATTR InstName A2 SYMBOL res -336 -848 R0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap -288 -560 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL voltage 208 -528 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V6 SYMATTR Value PULSE(0 3 0 0 0 50n 100n) SYMBOL res 848 -656 R90 WINDOW 0 80 54 VBottom 2 WINDOW 3 89 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 1K SYMBOL cap 896 -576 R0 WINDOW 0 -58 48 Left 2 WINDOW 3 -56 80 Left 2 SYMATTR InstName C4 SYMATTR Value 8n SYMBOL Comparators\\LT1715 -112 -672 R0 SYMATTR InstName U2 SYMBOL voltage -176 -976 R0 WINDOW 3 -64 56 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value 5 SYMATTR InstName V7 SYMBOL voltage 208 240 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(0 3 0 0 0 50n 100n) TEXT -712 488 Left 2 !.tran 5m RECTANGLE Normal 576 480 144 -128 2 RECTANGLE Normal 576 -288 144 -896 2
Reply by ●January 20, 20222022-01-20
On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: >> This uses an FPGA LVDS input as a comparator, and one external RC, to >> make an ADC. Just need an algorithm to process the flop output. >> >> A simpler ADC should be possible. >> > >more than one way to do it, one is basically successive approximation with a pwm dac >another is delta-sigma with RC as "integrator" that might have an advantage in that the >comparator doesn't follow the input signal it is always ~1/2 VccThat's certainly better; the FPGA LVDS receivers are mediocre comparators. But the game was to minimize the number of external parts. I'll be digitizing a thermistor on a heat sink, so it's not a precision thing. If we go with an available Lattice FPGA, it doesn't have an ADC. Some sort of delta-sigma signal processing would be interesting. I could use an LM71, SPI temp sensor, which is just not as interesting.> > >Version 4 >SHEET 1 1316 680 >WIRE -96 -992 -176 -992 >WIRE -176 -960 -176 -992 >WIRE 496 -832 -320 -832 >WIRE -96 -752 -96 -992 >WIRE -96 -752 -128 -752 >WIRE -128 -720 -128 -752 >WIRE -96 -720 -96 -752 >WIRE -320 -688 -320 -752 >WIRE -304 -688 -320 -688 >WIRE -144 -688 -304 -688 >WIRE -16 -672 -64 -672 >WIRE -144 -656 -480 -656 >WIRE -16 -656 -16 -672 >WIRE 192 -656 -16 -656 >WIRE 192 -640 192 -656 >WIRE 272 -640 192 -640 >WIRE 496 -640 496 -832 >WIRE 496 -640 432 -640 >WIRE 752 -640 496 -640 >WIRE 912 -640 832 -640 >WIRE -304 -624 -304 -688 >WIRE 272 -592 208 -592 >WIRE -128 -576 -128 -624 >WIRE -96 -576 -96 -624 >WIRE -96 -576 -128 -576 >WIRE 912 -576 912 -640 >WIRE -304 -528 -304 -560 >WIRE 208 -512 208 -592 >WIRE 912 -464 912 -512 >WIRE 208 -368 208 -432 >WIRE -96 -224 -176 -224 >WIRE -176 -192 -176 -224 >WIRE 496 -64 -320 -64 >WIRE -96 16 -96 -224 >WIRE -96 16 -128 16 >WIRE -128 48 -128 16 >WIRE -96 48 -96 16 >WIRE -144 80 -176 80 >WIRE -16 96 -64 96 >WIRE -480 112 -480 -656 >WIRE -416 112 -480 112 >WIRE -320 112 -320 16 >WIRE -320 112 -336 112 >WIRE -304 112 -320 112 >WIRE -144 112 -304 112 >WIRE -16 112 -16 96 >WIRE 192 112 -16 112 >WIRE -480 128 -480 112 >WIRE 192 128 192 112 >WIRE 272 128 192 128 >WIRE 752 128 432 128 >WIRE 912 128 832 128 >WIRE -304 144 -304 112 >WIRE 272 176 208 176 >WIRE 496 176 496 -64 >WIRE 496 176 448 176 >WIRE -128 192 -128 144 >WIRE -96 192 -96 144 >WIRE -96 192 -128 192 >WIRE 912 192 912 128 >WIRE -304 240 -304 208 >WIRE 208 256 208 176 >WIRE -176 272 -176 80 >WIRE 912 304 912 256 >WIRE -480 384 -480 208 >WIRE 208 400 208 336 >FLAG -480 384 0 >FLAG 272 224 0 >FLAG 208 400 0 >FLAG -304 240 0 >FLAG 912 304 0 >FLAG -176 -112 0 >FLAG -128 192 0 >FLAG -176 352 0 >FLAG 272 -544 0 >FLAG 208 -368 0 >FLAG -304 -528 0 >FLAG 912 -464 0 >FLAG -176 -880 0 >FLAG -128 -576 0 >FLAG -480 -656 Vin >FLAG 912 -640 Vout1 >FLAG 912 128 Vout2 >SYMBOL voltage -480 112 R0 >WINDOW 3 -226 54 Left 2 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR Value SINE(1.5 1.4 5000) >SYMATTR InstName V1 >SYMBOL Digital\\dflop 352 80 R0 >WINDOW 3 8 12 Left 2 >SYMATTR Value vhigh=3 >SYMATTR InstName A1 >SYMBOL res -320 96 R90 >WINDOW 0 0 56 VBottom 2 >WINDOW 3 32 56 VTop 2 >SYMATTR InstName R1 >SYMATTR Value 10k >SYMBOL res -336 -80 R0 >SYMATTR InstName R2 >SYMATTR Value 10k >SYMBOL cap -288 208 R180 >WINDOW 0 24 56 Left 2 >WINDOW 3 24 8 Left 2 >SYMATTR InstName C1 >SYMATTR Value 10n >SYMBOL res 848 112 R90 >WINDOW 0 80 54 VBottom 2 >WINDOW 3 89 56 VTop 2 >SYMATTR InstName R4 >SYMATTR Value 1K >SYMBOL cap 896 192 R0 >WINDOW 0 -58 48 Left 2 >WINDOW 3 -56 80 Left 2 >SYMATTR InstName C3 >SYMATTR Value 8n >SYMBOL Comparators\\LT1715 -112 96 R0 >SYMATTR InstName U1 >SYMBOL voltage -176 -208 R0 >WINDOW 3 -64 56 Left 2 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR Value 5 >SYMATTR InstName V2 >SYMBOL voltage -176 256 R0 >WINDOW 3 -64 56 Left 2 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR Value 1.5 >SYMATTR InstName V4 >SYMBOL Digital\\dflop 352 -688 R0 >WINDOW 3 8 12 Left 2 >SYMATTR Value vhigh=3 >SYMATTR InstName A2 >SYMBOL res -336 -848 R0 >SYMATTR InstName R5 >SYMATTR Value 1k >SYMBOL cap -288 -560 R180 >WINDOW 0 24 56 Left 2 >WINDOW 3 24 8 Left 2 >SYMATTR InstName C2 >SYMATTR Value 10n >SYMBOL voltage 208 -528 R0 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR InstName V6 >SYMATTR Value PULSE(0 3 0 0 0 50n 100n) >SYMBOL res 848 -656 R90 >WINDOW 0 80 54 VBottom 2 >WINDOW 3 89 56 VTop 2 >SYMATTR InstName R6 >SYMATTR Value 1K >SYMBOL cap 896 -576 R0 >WINDOW 0 -58 48 Left 2 >WINDOW 3 -56 80 Left 2 >SYMATTR InstName C4 >SYMATTR Value 8n >SYMBOL Comparators\\LT1715 -112 -672 R0 >SYMATTR InstName U2 >SYMBOL voltage -176 -976 R0 >WINDOW 3 -64 56 Left 2 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR Value 5 >SYMATTR InstName V7 >SYMBOL voltage 208 240 R0 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR InstName V3 >SYMATTR Value PULSE(0 3 0 0 0 50n 100n) >TEXT -712 488 Left 2 !.tran 5m >RECTANGLE Normal 576 480 144 -128 2 >RECTANGLE Normal 576 -288 144 -896 2-- I yam what I yam - Popeye
Reply by ●January 21, 20222022-01-21
On Thursday, January 20, 2022 at 2:51:20 PM UTC-5, lang...@fonz.dk wrote:> torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: > > This uses an FPGA LVDS input as a comparator, and one external RC, to > > make an ADC. Just need an algorithm to process the flop output. > > > > A simpler ADC should be possible. > > > more than one way to do it, one is basically successive approximation with a pwm dac > another is delta-sigma with RC as "integrator" that might have an advantage in that the > comparator doesn't follow the input signal it is always ~1/2 VccThat is important in an FPGA because the differential inputs are not rail to rail. In fact, they are rated to work over a very limited range. I'm not sure how well they will serve in this application. A good comparator is rated for offset voltage. The spec on an LVDS mode input in an FPGA has a very loose spec for that. Given that the input circuit is basically a voltage divider it works to increase the significance of input offset relative to the input signal. If you are trying to set an alarm for some condition with a loose input spec for accuracy or offset, then this can work fine. It only costs 3 pins on the FPGA. I worked on a design that used 8 such ADCs. Rather than use resistors to set the reference point I used another output with a 50/50 duty cycle to get an accurate Vcc/2 point that follows the rail without resistors removing some source of error and could be shared with all the ADCs. It also allowed you to adjust the reference voltage if there became a need to make an adjustment. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●January 21, 20222022-01-21
<fd3jugh4hv2mlbl9dfchcql4cf93udatav@4ax.com> a ecrit>This uses an FPGA LVDS input as a comparator, and one external RC, to >make an ADC. Just need an algorithm to process the flop output. > >A simpler ADC should be possible. >WINDOW 0 46 12 Left 2 >I yam what I yam - PopeyeProbiblie bEst iz too juice a FLIR IR camarade wiz Anna Log outpud ant prozes ze vidio on 1 FPGAYE pin. Ze moost rat airraids r ze hot test Tom
Reply by ●January 21, 20222022-01-21
fredag den 21. januar 2022 kl. 03.08.06 UTC+1 skrev jla...@highlandsniptechnology.com:> On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: > >> This uses an FPGA LVDS input as a comparator, and one external RC, to > >> make an ADC. Just need an algorithm to process the flop output. > >> > >> A simpler ADC should be possible. > >> > > > >more than one way to do it, one is basically successive approximation with a pwm dac > >another is delta-sigma with RC as "integrator" that might have an advantage in that the > >comparator doesn't follow the input signal it is always ~1/2 Vcc > That's certainly better; the FPGA LVDS receivers are mediocre > comparators. But the game was to minimize the number of external > parts. I'll be digitizing a thermistor on a heat sink, so it's not a > precision thing. > > If we go with an available Lattice FPGA, it doesn't have an ADC. > > Some sort of delta-sigma signal processing would be interesting. > > I could use an LM71, SPI temp sensor, which is just not as > interesting.even simpler tmp05/tmp06 which is pwm output so all you need is a counter in the fpga or for easy mounting on a heat sink, https://dk.farnell.com/smartec/smt172-220/temperature-sensor-1deg-c-to-220/dp/2543396
Reply by ●January 21, 20222022-01-21
On 21/01/2022 12.41, Lasse Langwadt Christensen wrote:> fredag den 21. januar 2022 kl. 03.08.06 UTC+1 skrev jla...@highlandsniptechnology.com: >> On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen >> <lang...@fonz.dk> wrote: >> >>> torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: >>>> This uses an FPGA LVDS input as a comparator, and one external RC, to >>>> make an ADC. Just need an algorithm to process the flop output. >>>> >>>> A simpler ADC should be possible. >>>> >>> >>> more than one way to do it, one is basically successive approximation with a pwm dac >>> another is delta-sigma with RC as "integrator" that might have an advantage in that the >>> comparator doesn't follow the input signal it is always ~1/2 Vcc >> That's certainly better; the FPGA LVDS receivers are mediocre >> comparators. But the game was to minimize the number of external >> parts. I'll be digitizing a thermistor on a heat sink, so it's not a >> precision thing. >> >> If we go with an available Lattice FPGA, it doesn't have an ADC. >> >> Some sort of delta-sigma signal processing would be interesting. >> >> I could use an LM71, SPI temp sensor, which is just not as >> interesting. > > even simpler tmp05/tmp06 which is pwm output so all you need is a counter in the fpga > > or for easy mounting on a heat sink, https://dk.farnell.com/smartec/smt172-220/temperature-sensor-1deg-c-to-220/dp/2543396Who in their right mind comes up with a device name "tmp05"? ;-)
Reply by ●January 21, 20222022-01-21
On Fri, 21 Jan 2022 03:41:56 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>fredag den 21. januar 2022 kl. 03.08.06 UTC+1 skrev jla...@highlandsniptechnology.com: >> On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen >> <lang...@fonz.dk> wrote: >> >> >torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: >> >> This uses an FPGA LVDS input as a comparator, and one external RC, to >> >> make an ADC. Just need an algorithm to process the flop output. >> >> >> >> A simpler ADC should be possible. >> >> >> > >> >more than one way to do it, one is basically successive approximation with a pwm dac >> >another is delta-sigma with RC as "integrator" that might have an advantage in that the >> >comparator doesn't follow the input signal it is always ~1/2 Vcc >> That's certainly better; the FPGA LVDS receivers are mediocre >> comparators. But the game was to minimize the number of external >> parts. I'll be digitizing a thermistor on a heat sink, so it's not a >> precision thing. >> >> If we go with an available Lattice FPGA, it doesn't have an ADC. >> >> Some sort of delta-sigma signal processing would be interesting. >> >> I could use an LM71, SPI temp sensor, which is just not as >> interesting. > >even simpler tmp05/tmp06 which is pwm output so all you need is a counter in the fpga > >or for easy mounting on a heat sink, https://dk.farnell.com/smartec/smt172-220/temperature-sensor-1deg-c-to-220/dp/254339674 cookies! A record! That would be a good way to couple thermally to the heat sink. We have LM35 in stock, in TO220, too, but that would require an ADC and probebly an opamp, which isn't bad. I want to simulate the mosfet junction temperatures in realtime, and the heatsink temp is part of that math. -- I yam what I yam - Popeye
Reply by ●January 21, 20222022-01-21
On Friday, January 21, 2022 at 6:42:00 AM UTC-5, lang...@fonz.dk wrote:> fredag den 21. januar 2022 kl. 03.08.06 UTC+1 skrev jla...@highlandsniptechnology.com: > > On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen > > <lang...@fonz.dk> wrote: > > > > >torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: > > >> This uses an FPGA LVDS input as a comparator, and one external RC, to > > >> make an ADC. Just need an algorithm to process the flop output. > > >> > > >> A simpler ADC should be possible. > > >> > > > > > >more than one way to do it, one is basically successive approximation with a pwm dac > > >another is delta-sigma with RC as "integrator" that might have an advantage in that the > > >comparator doesn't follow the input signal it is always ~1/2 Vcc > > That's certainly better; the FPGA LVDS receivers are mediocre > > comparators. But the game was to minimize the number of external > > parts. I'll be digitizing a thermistor on a heat sink, so it's not a > > precision thing. > > > > If we go with an available Lattice FPGA, it doesn't have an ADC. > > > > Some sort of delta-sigma signal processing would be interesting. > > > > I could use an LM71, SPI temp sensor, which is just not as > > interesting. > even simpler tmp05/tmp06 which is pwm output so all you need is a counter in the fpga > > or for easy mounting on a heat sink, https://dk.farnell.com/smartec/smt172-220/temperature-sensor-1deg-c-to-220/dp/2543396Isn't the FPGA the place where you put arbitrarily complex logic? Why try to minimize it? The filter typically used in the ADC you indicated above is often an integrate and dump, otherwise known as a counter. The filter characteristics are such that frequency multiples of half the sample rate are on nulls. This helps with the antialias filtering, but to get a sharper response near the half sample rate requires a FIR filter or similar. In fact, best is a filter that compensates with some boost to compensate for the integrate and dump roll off. A design example I saw from Lattice included both an integrate and dump followed by a FIR filter. However, I believe the FIR coefficients were all just 1, so after decimation it was also an integrate and dump equivalent. I suppose you could add any coefficients you wished. It was only a app note after all. Often the application does not require any significant filtering and the integrate and dump is simply the way of increasing the resolution from 1 bit to N bits by counting 2^N input samples. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
Reply by ●January 22, 20222022-01-22
lørdag den 22. januar 2022 kl. 04.28.58 UTC+1 skrev gnuarm.del...@gmail.com:> On Friday, January 21, 2022 at 6:42:00 AM UTC-5, lang...@fonz.dk wrote: > > fredag den 21. januar 2022 kl. 03.08.06 UTC+1 skrev jla...@highlandsniptechnology.com: > > > On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen > > > <lang...@fonz.dk> wrote: > > > > > > >torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev jla...@highlandsniptechnology.com: > > > >> This uses an FPGA LVDS input as a comparator, and one external RC, to > > > >> make an ADC. Just need an algorithm to process the flop output. > > > >> > > > >> A simpler ADC should be possible. > > > >> > > > > > > > >more than one way to do it, one is basically successive approximation with a pwm dac > > > >another is delta-sigma with RC as "integrator" that might have an advantage in that the > > > >comparator doesn't follow the input signal it is always ~1/2 Vcc > > > That's certainly better; the FPGA LVDS receivers are mediocre > > > comparators. But the game was to minimize the number of external > > > parts. I'll be digitizing a thermistor on a heat sink, so it's not a > > > precision thing. > > > > > > If we go with an available Lattice FPGA, it doesn't have an ADC. > > > > > > Some sort of delta-sigma signal processing would be interesting. > > > > > > I could use an LM71, SPI temp sensor, which is just not as > > > interesting. > > even simpler tmp05/tmp06 which is pwm output so all you need is a counter in the fpga > > > > or for easy mounting on a heat sink, https://dk.farnell.com/smartec/smt172-220/temperature-sensor-1deg-c-to-220/dp/2543396 > Isn't the FPGA the place where you put arbitrarily complex logic? Why try to minimize it?why spend time to implement a SPI, use three/four pins, or logic and extra parts to fudge an ADC and calibrate that when you can get a calibrated part that only need a single pin and very simple logic
