Is this right? 1125MHz 14-bit dual channel acquisition

On a sunny day (Thu, 4 Nov 2021 12:44:00 -0700 (PDT)) it happened Lasse
Langwadt Christensen <langwadt@fonz.dk> wrote in
<fd40cc59-e84f-48a3-80c6-5e570c491e8cn@googlegroups.com>:

>torsdag den 4. november 2021 kl. 20.08.49 UTC+1 skrev Jan Panteltje:
>> On a sunny day (Thu, 4 Nov 2021 11:39:05 -0700 (PDT)) it happened Lasse 
>> Langwadt Christensen <lang...@fonz.dk> wrote in 
>> <2d811173-922b-4488...@googlegroups.com>:
>> >torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: 
>> >> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> 
>> >> wrote: 
>> >> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: 
>> >> >> Jan Panteltje wrote: 
>> >> > 
>> >> >>> Yes, but why not use 14 fast comparators? 
>> >> >>> I think you have lots of experience with low offset stuff? 
>> >> >>> 
>> >> >> 
>> >> >> What would you use them for? To make it a true flash converter, you 
>> >> >> need 2**14-1 comparators, not 14. 
>> >> > 
>> >> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these 
>> >> >for ultrasonic reactor wall testing. We got an additional 
>> >> >ADC from TRW in a plexiglas cube. One could see the reference 
>> >> >ladder and the comparator string with the bare eye. 
>> >> > 
>> >> > 
>> >> >< 
>> >> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ 
>> >> > > 
>> >> > 
>> >> >It is the large black chip on the blurred board on the bottom right. The 
>> >> >white blob reads "TRW". The rest of the boards is 
>> >> >a real-time averager. 
>> >> > 
>> >> >Some years later I condensed the entire board set to one board 
>> >> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. 
>> >> > 
>> >> >There was an interim solution with Fairchild F100K, but that 
>> >> >ran too hot. 
>> >> > 
>> >> >Cheers, Gerhard 
>> >> > 
>> >> > 
>> >> One of my many former employers made a Camac module 6-bit 50 MHz ADC 
>> >> out of discrete comparators. The model number was, appropriately, 
>> >> SAD-650. 
>> > 
>> >I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins
>> In reverse 
>> on that board I showed there is an R2R DAC on 8 FPGA output pins for video out. 
>> Worked!
>
>sure, DAC is a lot easier
>
>and then there's his kind of "hifi" nonsense
>
>http://www.soundbsessive.com/hifiduino-soekris-r2r-dac/

Yes 24 bit audio at 384 kHz is the minumum you need for true fidelity !

On a sunny day (Thu, 04 Nov 2021 12:31:20 -0700) it happened
jlarkin@highlandsniptechnology.com wrote in
<h3d8og1cfej643rc536c8tmgdu10e73kak@4ax.com>:

>On Thu, 4 Nov 2021 11:39:05 -0700 (PDT), Lasse Langwadt Christensen
><langwadt@fonz.dk> wrote:
>>I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins
>
>There could be cases where just a few bits would do.
>
>One could use external dual LVDS receivers as the comparators. They
>are cheap and fast and pretty good.
>
>Again, no pipeline delay.

Or have the R2R DAC drive a comparator and do successive approximation.
With high speed FPGA and not so many steps needed it could be fast.
I did something like that long ago, I like successive approximation.

On Thu, 04 Nov 2021 20:11:09 GMT, Jan Panteltje
<pNaOnStPeAlMtje@yahoo.com> wrote:

>On a sunny day (Thu, 4 Nov 2021 12:44:00 -0700 (PDT)) it happened Lasse
>Langwadt Christensen <langwadt@fonz.dk> wrote in
><fd40cc59-e84f-48a3-80c6-5e570c491e8cn@googlegroups.com>:
>
>>torsdag den 4. november 2021 kl. 20.08.49 UTC+1 skrev Jan Panteltje:
>>> On a sunny day (Thu, 4 Nov 2021 11:39:05 -0700 (PDT)) it happened Lasse 
>>> Langwadt Christensen <lang...@fonz.dk> wrote in 
>>> <2d811173-922b-4488...@googlegroups.com>:
>>> >torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: 
>>> >> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> 
>>> >> wrote: 
>>> >> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: 
>>> >> >> Jan Panteltje wrote: 
>>> >> > 
>>> >> >>> Yes, but why not use 14 fast comparators? 
>>> >> >>> I think you have lots of experience with low offset stuff? 
>>> >> >>> 
>>> >> >> 
>>> >> >> What would you use them for? To make it a true flash converter, you 
>>> >> >> need 2**14-1 comparators, not 14. 
>>> >> > 
>>> >> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these 
>>> >> >for ultrasonic reactor wall testing. We got an additional 
>>> >> >ADC from TRW in a plexiglas cube. One could see the reference 
>>> >> >ladder and the comparator string with the bare eye. 
>>> >> > 
>>> >> > 
>>> >> >< 
>>> >> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ 
>>> >> > > 
>>> >> > 
>>> >> >It is the large black chip on the blurred board on the bottom right. The 
>>> >> >white blob reads "TRW". The rest of the boards is 
>>> >> >a real-time averager. 
>>> >> > 
>>> >> >Some years later I condensed the entire board set to one board 
>>> >> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. 
>>> >> > 
>>> >> >There was an interim solution with Fairchild F100K, but that 
>>> >> >ran too hot. 
>>> >> > 
>>> >> >Cheers, Gerhard 
>>> >> > 
>>> >> > 
>>> >> One of my many former employers made a Camac module 6-bit 50 MHz ADC 
>>> >> out of discrete comparators. The model number was, appropriately, 
>>> >> SAD-650. 
>>> > 
>>> >I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins
>>> In reverse 
>>> on that board I showed there is an R2R DAC on 8 FPGA output pins for video out. 
>>> Worked!
>>
>>sure, DAC is a lot easier
>>
>>and then there's his kind of "hifi" nonsense
>>
>>http://www.soundbsessive.com/hifiduino-soekris-r2r-dac/
>
>Yes 24 bit audio at 384 kHz is the minumum you need for true fidelity !

With CMOS gate drivers and 0.05% resistors!



-- 

Father Brown's figure remained quite dark and still; 
but in that instant he had lost his head. His head was
always most valuable when he had lost it.



  

On Thu, 04 Nov 2021 20:11:16 GMT, Jan Panteltje
<pNaOnStPeAlMtje@yahoo.com> wrote:

>On a sunny day (Thu, 04 Nov 2021 12:31:20 -0700) it happened
>jlarkin@highlandsniptechnology.com wrote in
><h3d8og1cfej643rc536c8tmgdu10e73kak@4ax.com>:
>
>>On Thu, 4 Nov 2021 11:39:05 -0700 (PDT), Lasse Langwadt Christensen
>><langwadt@fonz.dk> wrote:
>>>I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins
>>
>>There could be cases where just a few bits would do.
>>
>>One could use external dual LVDS receivers as the comparators. They
>>are cheap and fast and pretty good.
>>
>>Again, no pipeline delay.
>
>Or have the R2R DAC drive a comparator and do successive approximation.
>With high speed FPGA and not so many steps needed it could be fast.
>I did something like that long ago, I like successive approximation.

We do delta-sigma DACs in an FPGA. Add a feedback loop! Join the
slowest-possible-ADC competition.

There's also a hybrid DAC, a few bits of ladder, but d-s dithered to
higher resolution. Worst of both worlds.

One could do a cheap single-slope ADC with an LVDS input. The entire
ADC would become one R and one C. Shared across multiple channels.



-- 

Father Brown's figure remained quite dark and still; 
but in that instant he had lost his head. His head was
always most valuable when he had lost it.



  

torsdag den 4. november 2021 kl. 21.42.06 UTC+1 skrev jla...@highlandsniptechnology.com:
> On Thu, 04 Nov 2021 20:11:16 GMT, Jan Panteltje 
> <pNaOnSt...@yahoo.com> wrote: 
> 
> >On a sunny day (Thu, 04 Nov 2021 12:31:20 -0700) it happened 
> >jla...@highlandsniptechnology.com wrote in 
> ><h3d8og1cfej643rc5...@4ax.com>: 
> > 
> >>On Thu, 4 Nov 2021 11:39:05 -0700 (PDT), Lasse Langwadt Christensen 
> >><lang...@fonz.dk> wrote: 
> >>>I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins 
> >> 
> >>There could be cases where just a few bits would do. 
> >> 
> >>One could use external dual LVDS receivers as the comparators. They 
> >>are cheap and fast and pretty good. 
> >> 
> >>Again, no pipeline delay. 
> > 
> >Or have the R2R DAC drive a comparator and do successive approximation. 
> >With high speed FPGA and not so many steps needed it could be fast. 
> >I did something like that long ago, I like successive approximation.
> We do delta-sigma DACs in an FPGA. Add a feedback loop! Join the 
> slowest-possible-ADC competition. 
> 
> There's also a hybrid DAC, a few bits of ladder, but d-s dithered to 
> higher resolution. Worst of both worlds. 

you can also do d-s down to a few bits and the do those bits with PWM
reducing the switching rate
 
> One could do a cheap single-slope ADC with an LVDS input. The entire 
> ADC would become one R and one C. Shared across multiple channels.
> -- 

or https://intentionallogic.com/wp-content/uploads/2018/01/adc_schematic.png

or you could do a real d-s, needs an integrator but it keeps the comparator threshold at VCC/2

On a sunny day (Thu, 04 Nov 2021 13:41:58 -0700) it happened
jlarkin@highlandsniptechnology.com wrote in
<n1h8oglu80akem52umph5eh01fv6nf8hbg@4ax.com>:

>On Thu, 04 Nov 2021 20:11:16 GMT, Jan Panteltje
><pNaOnStPeAlMtje@yahoo.com> wrote:
>
>>On a sunny day (Thu, 04 Nov 2021 12:31:20 -0700) it happened
>>jlarkin@highlandsniptechnology.com wrote in
>><h3d8og1cfej643rc536c8tmgdu10e73kak@4ax.com>:
>>
>>>On Thu, 4 Nov 2021 11:39:05 -0700 (PDT), Lasse Langwadt Christensen
>>><langwadt@fonz.dk> wrote:
>>>>I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins
>>>
>>>There could be cases where just a few bits would do.
>>>
>>>One could use external dual LVDS receivers as the comparators. They
>>>are cheap and fast and pretty good.
>>>
>>>Again, no pipeline delay.
>>
>>Or have the R2R DAC drive a comparator and do successive approximation.
>>With high speed FPGA and not so many steps needed it could be fast.
>>I did something like that long ago, I like successive approximation.
>
>We do delta-sigma DACs in an FPGA. Add a feedback loop! Join the
>slowest-possible-ADC competition.
>
>There's also a hybrid DAC, a few bits of ladder, but d-s dithered to
>higher resolution. Worst of both worlds.
>
>One could do a cheap single-slope ADC with an LVDS input. The entire
>ADC would become one R and one C. Shared across multiple channels.

When doing the successive approximation it is a good idea to have a sample and hold circuit,
so 1 extra output pin from the FPGA, to keep the voltage constant when checking,