On Thu, 04 Nov 2021 14:58:27 GMT, Jan Panteltje <pNaOnStPeAlMtje@yahoo.com> wrote:>I wrote >>Yes, but why not use 14 fast comparators? > >mean 2^14 of course :-) > >I mean with milions of things on a chip these days..People used to make true-flash ADCs, at 6 bits or so. There was a "half-flash" ADC with 8 or 10, I think; each comparator generated two bits. The problem was power. The nice thing was low pipeline delay. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Is this right? 1125MHz 14-bit dual channel acquisition
Started by ●November 1, 2021
Reply by ●November 4, 20212021-11-04
Reply by ●November 4, 20212021-11-04
On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk4xp@arcor.de> wrote:>Am 04.11.21 um 15:54 schrieb Phil Hobbs: >> Jan Panteltje wrote: > >>> Yes, but why not use 14 fast comparators? >>> I think you have lots of experience with low offset stuff? >>> >> >> What would you use them for?� To make it a true flash converter, you >> need 2**14-1 comparators, not 14. > >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these >for ultrasonic reactor wall testing. We got an additional >ADC from TRW in a plexiglas cube. One could see the reference >ladder and the comparator string with the bare eye. > > >< >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ > > > >It is the large black chip on the blurred board on the bottom right. The >white blob reads "TRW". The rest of the boards is >a real-time averager. > >Some years later I condensed the entire board set to one board >with some Xilinx FPGAs. It had a pipeline 20 stages deep. > >There was an interim solution with Fairchild F100K, but that >ran too hot. > >Cheers, Gerhard > >One of my many former employers made a Camac module 6-bit 50 MHz ADC out of discrete comparators. The model number was, appropriately, SAD-650. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Reply by ●November 4, 20212021-11-04
Gerhard Hoffmann wrote:> Am 04.11.21 um 15:54 schrieb Phil Hobbs: >> Jan Panteltje wrote: > >>> Yes, but why not use 14 fast comparators? >>> I think you have lots of experience with low offset stuff? >>> >> >> What would you use them for?� To make it a true flash converter, you >> need 2**14-1 comparators, not 14. > > Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these > for ultrasonic reactor wall testing. We got an additional > ADC from TRW in a plexiglas cube. One could see the reference > ladder and the comparator string with the bare eye. > > > < > https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ > ��� > > > It is the large black chip on the blurred board on the bottom right. The > white blob reads "TRW". The rest of the boards is > a real-time averager. > > Some years later I condensed the entire board set to one board > with some Xilinx FPGAs. It had a pipeline 20 stages deep. > > There was an interim solution with Fairchild F100K, but that > ran too hot. > > Cheers, Gerhard > > >You gotta really want to do something like that. ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●November 4, 20212021-11-04
torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com:> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> > wrote: > >Am 04.11.21 um 15:54 schrieb Phil Hobbs: > >> Jan Panteltje wrote: > > > >>> Yes, but why not use 14 fast comparators? > >>> I think you have lots of experience with low offset stuff? > >>> > >> > >> What would you use them for? To make it a true flash converter, you > >> need 2**14-1 comparators, not 14. > > > >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these > >for ultrasonic reactor wall testing. We got an additional > >ADC from TRW in a plexiglas cube. One could see the reference > >ladder and the comparator string with the bare eye. > > > > > >< > >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ > > > > > > >It is the large black chip on the blurred board on the bottom right. The > >white blob reads "TRW". The rest of the boards is > >a real-time averager. > > > >Some years later I condensed the entire board set to one board > >with some Xilinx FPGAs. It had a pipeline 20 stages deep. > > > >There was an interim solution with Fairchild F100K, but that > >ran too hot. > > > >Cheers, Gerhard > > > > > One of my many former employers made a Camac module 6-bit 50 MHz ADC > out of discrete comparators. The model number was, appropriately, > SAD-650.I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins
Reply by ●November 4, 20212021-11-04
On a sunny day (Thu, 4 Nov 2021 11:39:05 -0700 (PDT)) it happened Lasse Langwadt Christensen <langwadt@fonz.dk> wrote in <2d811173-922b-4488-8cfd-f40206fcf663n@googlegroups.com>:>torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: >> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> >> wrote: >> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: >> >> Jan Panteltje wrote: >> > >> >>> Yes, but why not use 14 fast comparators? >> >>> I think you have lots of experience with low offset stuff? >> >>> >> >> >> >> What would you use them for? To make it a true flash converter, you >> >> need 2**14-1 comparators, not 14. >> > >> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these >> >for ultrasonic reactor wall testing. We got an additional >> >ADC from TRW in a plexiglas cube. One could see the reference >> >ladder and the comparator string with the bare eye. >> > >> > >> >< >> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ >> > > >> > >> >It is the large black chip on the blurred board on the bottom right. The >> >white blob reads "TRW". The rest of the boards is >> >a real-time averager. >> > >> >Some years later I condensed the entire board set to one board >> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. >> > >> >There was an interim solution with Fairchild F100K, but that >> >ran too hot. >> > >> >Cheers, Gerhard >> > >> > >> One of my many former employers made a Camac module 6-bit 50 MHz ADC >> out of discrete comparators. The model number was, appropriately, >> SAD-650. > >I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pinsIn reverse on that board I showed there is an R2R DAC on 8 FPGA output pins for video out. Worked!
Reply by ●November 4, 20212021-11-04
On Thu, 4 Nov 2021 11:39:05 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: >> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> >> wrote: >> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: >> >> Jan Panteltje wrote: >> > >> >>> Yes, but why not use 14 fast comparators? >> >>> I think you have lots of experience with low offset stuff? >> >>> >> >> >> >> What would you use them for? To make it a true flash converter, you >> >> need 2**14-1 comparators, not 14. >> > >> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these >> >for ultrasonic reactor wall testing. We got an additional >> >ADC from TRW in a plexiglas cube. One could see the reference >> >ladder and the comparator string with the bare eye. >> > >> > >> >< >> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ >> > > >> > >> >It is the large black chip on the blurred board on the bottom right. The >> >white blob reads "TRW". The rest of the boards is >> >a real-time averager. >> > >> >Some years later I condensed the entire board set to one board >> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. >> > >> >There was an interim solution with Fairchild F100K, but that >> >ran too hot. >> > >> >Cheers, Gerhard >> > >> > >> One of my many former employers made a Camac module 6-bit 50 MHz ADC >> out of discrete comparators. The model number was, appropriately, >> SAD-650. > >I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pinsThere could be cases where just a few bits would do. One could use external dual LVDS receivers as the comparators. They are cheap and fast and pretty good. Again, no pipeline delay. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Reply by ●November 4, 20212021-11-04
jlarkin@highlandsniptechnology.com wrote:> On Thu, 04 Nov 2021 14:58:27 GMT, Jan Panteltje > <pNaOnStPeAlMtje@yahoo.com> wrote: > >> I wrote >>> Yes, but why not use 14 fast comparators? >> >> mean 2^14 of course :-) >> >> I mean with milions of things on a chip these days.. > > People used to make true-flash ADCs, at 6 bits or so. There was a > "half-flash" ADC with 8 or 10, I think; each comparator generated two > bits. > > The problem was power. The nice thing was low pipeline delay. > > >Long ago, I used to use a nice TRW 8-bit true flash (1038B6C, 20 MS/s) that was even second-sourced. It came in a 28-pin wide CERDIP. The other main issue with flash converters (besides the horrible resolution vs. power and die size issue) was sloppy aperture time, on account of the capacitive coupling from the signal to the (high-Z) resistor string at the comparator inputs. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●November 4, 20212021-11-04
torsdag den 4. november 2021 kl. 20.08.49 UTC+1 skrev Jan Panteltje:> On a sunny day (Thu, 4 Nov 2021 11:39:05 -0700 (PDT)) it happened Lasse > Langwadt Christensen <lang...@fonz.dk> wrote in > <2d811173-922b-4488...@googlegroups.com>: > >torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: > >> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> > >> wrote: > >> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: > >> >> Jan Panteltje wrote: > >> > > >> >>> Yes, but why not use 14 fast comparators? > >> >>> I think you have lots of experience with low offset stuff? > >> >>> > >> >> > >> >> What would you use them for? To make it a true flash converter, you > >> >> need 2**14-1 comparators, not 14. > >> > > >> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these > >> >for ultrasonic reactor wall testing. We got an additional > >> >ADC from TRW in a plexiglas cube. One could see the reference > >> >ladder and the comparator string with the bare eye. > >> > > >> > > >> >< > >> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ > >> > > > >> > > >> >It is the large black chip on the blurred board on the bottom right. The > >> >white blob reads "TRW". The rest of the boards is > >> >a real-time averager. > >> > > >> >Some years later I condensed the entire board set to one board > >> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. > >> > > >> >There was an interim solution with Fairchild F100K, but that > >> >ran too hot. > >> > > >> >Cheers, Gerhard > >> > > >> > > >> One of my many former employers made a Camac module 6-bit 50 MHz ADC > >> out of discrete comparators. The model number was, appropriately, > >> SAD-650. > > > >I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins > In reverse > on that board I showed there is an R2R DAC on 8 FPGA output pins for video out. > Worked!sure, DAC is a lot easier and then there's his kind of "hifi" nonsense http://www.soundbsessive.com/hifiduino-soekris-r2r-dac/
Reply by ●November 4, 20212021-11-04
On Thu, 04 Nov 2021 12:31:20 -0700, jlarkin@highlandsniptechnology.com wrote:>On Thu, 4 Nov 2021 11:39:05 -0700 (PDT), Lasse Langwadt Christensen ><langwadt@fonz.dk> wrote: > >>torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: >>> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> >>> wrote: >>> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: >>> >> Jan Panteltje wrote: >>> > >>> >>> Yes, but why not use 14 fast comparators? >>> >>> I think you have lots of experience with low offset stuff? >>> >>> >>> >> >>> >> What would you use them for? To make it a true flash converter, you >>> >> need 2**14-1 comparators, not 14. >>> > >>> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these >>> >for ultrasonic reactor wall testing. We got an additional >>> >ADC from TRW in a plexiglas cube. One could see the reference >>> >ladder and the comparator string with the bare eye. >>> > >>> > >>> >< >>> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ >>> > > >>> > >>> >It is the large black chip on the blurred board on the bottom right. The >>> >white blob reads "TRW". The rest of the boards is >>> >a real-time averager. >>> > >>> >Some years later I condensed the entire board set to one board >>> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. >>> > >>> >There was an interim solution with Fairchild F100K, but that >>> >ran too hot. >>> > >>> >Cheers, Gerhard >>> > >>> > >>> One of my many former employers made a Camac module 6-bit 50 MHz ADC >>> out of discrete comparators. The model number was, appropriately, >>> SAD-650. >> >>I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins > >There could be cases where just a few bits would do. > >One could use external dual LVDS receivers as the comparators. They >are cheap and fast and pretty good. > >Again, no pipeline delay.We have used the LVDS inputs of an FPGA as real comparators, but ground bounce noise and crosstalk keeps that from working at the millivolt level. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Reply by ●November 4, 20212021-11-04
On Thu, 4 Nov 2021 12:44:00 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 4. november 2021 kl. 20.08.49 UTC+1 skrev Jan Panteltje: >> On a sunny day (Thu, 4 Nov 2021 11:39:05 -0700 (PDT)) it happened Lasse >> Langwadt Christensen <lang...@fonz.dk> wrote in >> <2d811173-922b-4488...@googlegroups.com>: >> >torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev jla...@highlandsniptechnology.com: >> >> On Thu, 4 Nov 2021 16:32:38 +0100, Gerhard Hoffmann <dk...@arcor.de> >> >> wrote: >> >> >Am 04.11.21 um 15:54 schrieb Phil Hobbs: >> >> >> Jan Panteltje wrote: >> >> > >> >> >>> Yes, but why not use 14 fast comparators? >> >> >>> I think you have lots of experience with low offset stuff? >> >> >>> >> >> >> >> >> >> What would you use them for? To make it a true flash converter, you >> >> >> need 2**14-1 comparators, not 14. >> >> > >> >> >Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these >> >> >for ultrasonic reactor wall testing. We got an additional >> >> >ADC from TRW in a plexiglas cube. One could see the reference >> >> >ladder and the comparator string with the bare eye. >> >> > >> >> > >> >> >< >> >> >https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ >> >> > > >> >> > >> >> >It is the large black chip on the blurred board on the bottom right. The >> >> >white blob reads "TRW". The rest of the boards is >> >> >a real-time averager. >> >> > >> >> >Some years later I condensed the entire board set to one board >> >> >with some Xilinx FPGAs. It had a pipeline 20 stages deep. >> >> > >> >> >There was an interim solution with Fairchild F100K, but that >> >> >ran too hot. >> >> > >> >> >Cheers, Gerhard >> >> > >> >> > >> >> One of my many former employers made a Camac module 6-bit 50 MHz ADC >> >> out of discrete comparators. The model number was, appropriately, >> >> SAD-650. >> > >> >I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins >> In reverse >> on that board I showed there is an R2R DAC on 8 FPGA output pins for video out. >> Worked! > >sure, DAC is a lot easier > >and then there's his kind of "hifi" nonsense > >http://www.soundbsessive.com/hifiduino-soekris-r2r-dac/ > > > > > > >The high-end audio people are lunatics. Golden ears get expensive. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
