FPGA sensitivities

On Fri, 25 Sep 2020 12:16:07 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

>
>
>I have a time-critical thing where the signal passes through an XC7A15
>FPGA and does a fair lot of stuff inside. I measured delay vs some
>voltages:
>
>1.8 aux   no measurable DC effect
> 
>3.3 vccio no measurable DC effect
>
>2.5 vccio ditto (key io's are LVDS in this bank)
>
>+1 core   -10 ps per millivolt!
>
>If I vary the trigger frequency, I can see the delay heterodyning
>against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track
>that down.
>
>A spritz of freeze spray on the chip had practically no effect on
>delay through the chip, on a scope at 100 ps/div.
>
>I expected sensitivity to core voltage, so we'll make sure we have a
>serious, analog-quality voltage regulator next rev.
>
>The temperature thing surprised me. I was used to CMOS having a
>serious positive delay TC. Maybe modern FPGAs have some sort of
>temperature compensation designed in?
>
>We also have a ZYNQ on this board that crashes the ARM core
>erratically, especially when the chip is hot. It might crash in maybe
>a half hour MTBF if the chip reports 55C internally; the FPGA part
>keeps going. At powerup boot from an SD card, it will always configure
>the PL FPGA side, but will then fail to run our application if the
>chip is hot. We're playing with DRAM and CPU clock rates to see if
>that has much effect.
>
>

Fixed both problems.

Jitter: replaced the 1.8V Vccaux switcher with a linear regulator.

Temperature-dependant crashing: I found an oscillation on the Zynq 1v
core power supply, about 100 mV p-p and 80 KHz. Putting a lot more
capacitance at the switcher output kills that and makes the crash go
away. The regulator design followed a chart in the LTM8078 data sheet.
A Spice sim with the original values looks stable, no oscillation and
a clean load-step recovery.

There are other indications that ADI's Spice model of the LTM8078 is
less than perfect. I think ADI is struggling to add a lot of new parts
to the LT Spice libraries. Mike E in an interview suggested that
rushing them out was compromising quality. Then he quit.

Glad I fixed this this way. Guys were snooping the AXIbus and Linux at
great expense and no progress.

mandag den 5. oktober 2020 kl. 22.06.28 UTC+2 skrev John Larkin:
> On Fri, 25 Sep 2020 12:16:07 -0700, John Larkin
> <jlarkin@highland_atwork_technology.com> wrote:
> 
> >
> >
> >I have a time-critical thing where the signal passes through an XC7A15
> >FPGA and does a fair lot of stuff inside. I measured delay vs some
> >voltages:
> >
> >1.8 aux   no measurable DC effect
> > 
> >3.3 vccio no measurable DC effect
> >
> >2.5 vccio ditto (key io's are LVDS in this bank)
> >
> >+1 core   -10 ps per millivolt!
> >
> >If I vary the trigger frequency, I can see the delay heterodyning
> >against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track
> >that down.
> >
> >A spritz of freeze spray on the chip had practically no effect on
> >delay through the chip, on a scope at 100 ps/div.
> >
> >I expected sensitivity to core voltage, so we'll make sure we have a
> >serious, analog-quality voltage regulator next rev.
> >
> >The temperature thing surprised me. I was used to CMOS having a
> >serious positive delay TC. Maybe modern FPGAs have some sort of
> >temperature compensation designed in?
> >
> >We also have a ZYNQ on this board that crashes the ARM core
> >erratically, especially when the chip is hot. It might crash in maybe
> >a half hour MTBF if the chip reports 55C internally; the FPGA part
> >keeps going. At powerup boot from an SD card, it will always configure
> >the PL FPGA side, but will then fail to run our application if the
> >chip is hot. We're playing with DRAM and CPU clock rates to see if
> >that has much effect.
> >
> >
> 
> Fixed both problems.
> 
> Jitter: replaced the 1.8V Vccaux switcher with a linear regulator.
> 

I believe the mixed mode clock manger and pll in the PL is powered from Vccaux

On Mon, 5 Oct 2020 13:20:26 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>mandag den 5. oktober 2020 kl. 22.06.28 UTC+2 skrev John Larkin:
>> On Fri, 25 Sep 2020 12:16:07 -0700, John Larkin
>> <jlarkin@highland_atwork_technology.com> wrote:
>> 
>> >
>> >
>> >I have a time-critical thing where the signal passes through an XC7A15
>> >FPGA and does a fair lot of stuff inside. I measured delay vs some
>> >voltages:
>> >
>> >1.8 aux   no measurable DC effect
>> > 
>> >3.3 vccio no measurable DC effect
>> >
>> >2.5 vccio ditto (key io's are LVDS in this bank)
>> >
>> >+1 core   -10 ps per millivolt!
>> >
>> >If I vary the trigger frequency, I can see the delay heterodyning
>> >against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track
>> >that down.
>> >
>> >A spritz of freeze spray on the chip had practically no effect on
>> >delay through the chip, on a scope at 100 ps/div.
>> >
>> >I expected sensitivity to core voltage, so we'll make sure we have a
>> >serious, analog-quality voltage regulator next rev.
>> >
>> >The temperature thing surprised me. I was used to CMOS having a
>> >serious positive delay TC. Maybe modern FPGAs have some sort of
>> >temperature compensation designed in?
>> >
>> >We also have a ZYNQ on this board that crashes the ARM core
>> >erratically, especially when the chip is hot. It might crash in maybe
>> >a half hour MTBF if the chip reports 55C internally; the FPGA part
>> >keeps going. At powerup boot from an SD card, it will always configure
>> >the PL FPGA side, but will then fail to run our application if the
>> >chip is hot. We're playing with DRAM and CPU clock rates to see if
>> >that has much effect.
>> >
>> >
>> 
>> Fixed both problems.
>> 
>> Jitter: replaced the 1.8V Vccaux switcher with a linear regulator.
>> 
>
>I believe the mixed mode clock manger and pll in the PL is powered from Vccaux

I did a static sensitivity test on the critical-path FPGA. It showed
essentially zero through-chip delay vs Vccaux. It was super sensitive
to core voltage. But the +1 core supply was LDO'ed from the noisy 1.8,
so maybe some noise sneaked through there.

I'm going to rip out some switchers and use a chain of LDOs to make
the various supplies for the critical XC7A15 FPGA. The Zynq is not in
the picoseconds-time-critical path.

+5  ldo to 3.3 for i/o banks
3.3 ldo to 2.5 for the bank that does LVDS
2.5 ldo to 1.8 for aux
1.8 ldo to 1.0 for core

in one long string.

We're using ST1L08 regs, super low dropout, good filtering, small and
cheap.