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Cute dpot hack for increased resolution

Started by Phil Hobbs July 22, 2020
On Sunday, July 26, 2020 at 8:03:57 PM UTC-4, jla...@highlandsniptechnology.com wrote:
> On Sun, 26 Jul 2020 17:50:10 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > > >On 2020-07-26 17:34, bloggs.fredbloggs.fred@gmail.com wrote: > >> On Wednesday, July 22, 2020 at 6:43:57 PM UTC-4, Phil Hobbs wrote: > >>> So I'm doing a simplified version of the differential laser noise > >>> canceller, which in the spherical cow universe looks like it does very > >>> well out to about 10 MHz, thanks to the amazing properties of BFP640s > >>> and some new photodiodes with reduced series resistance. (At least > >>> according to Hamamatsu.) > >>> > >>> One thing I need for this is an adjustable resistance with good > >>> bandwidth. The fastest dpot I can find is the AD5273BRJZ1 (1k, 64 > >>> steps, ~6 MHz bandwidth at half scale). > >>> > >>> The resolution is too coarse for my application, but as it's pretty well > >>> set-and-forget, I don't mind some algorithmic complexity. > >>> > >>> Turns out that if you make a sort of Darlington connection, with one > >>> dpot connected as a rheostat in series with the wiper of the other > >>> (which is connected to one end), you can get the approximate resolution > >>> of a 10-11 bit dpot. > >>> > >>> 1k > >>> 0-*----R1R1R1---------------0 > >>> | A > >>> | *-------*-----* > >>> | | | > >>> | V | 5k > >>> *------------R2R2R2--* > >>> > >>> It works best if R2 is about 5 times R1, but the bandwidth may be better > >>> if I stick with the 1k version. > >>> > >>> Neglecting switch resistance, calculating the total resistance as a > >>> function of the codes, sorting into a single 1-D array to get a > >>> monotonically increasing resistance function, and taking the first > >>> finite difference reveals a step size nearly always less than 0.1% > >>> except near the low-resistance end, which I don't care much about. > >>> > >>> There's a plot at > >>> <https://electrooptical.net/static/oldsite/www/sed/FightingDPOTs.png> > >>> > >>> Fun. > > > >> This kind of thing has been around forever. Fig 6 shows a 6-bit to 12-bit enhancement. > >> > >> https://www.analog.com/media/en/technical-documentation/application-notes/AN-582.pdf?doc=an-1291.pdf > > > >Sure, there are lots of approaches. The one I described is new to me, > >and isn't in the app note you cite. Its main disadvantage is that > >finding the right setting is relatively complicated, but on the plus > >side it gets you almost 2N bits' resolution and is essentially immune to > >moderate DNL in the dpots. > > > >The combination of settability and bandwidth exceeds anything available > >in a single device. That's pretty important to me, because the > >besetting sin of dpots and MDACs is that they're dog slow. > > > >Cheers > > > >Phil Hobbs > > Use a multiplier! > > I think there are a few fast MDACs too. > > You could have fun combining a few digitally controlled RF attenuator > chips.
I wonder if an R-2R ladder can be used for this with a handful of analog switches. I would do the math, but I'm not in the mood at the moment. It would be a fun exercise to work out a spread sheet to calculate results... but still not enough energy to do it tonight. Someone refresh my memory, does he need an actual three terminal pot or just a variable resistance? -- Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209
On 27/07/2020 01:11, Phil Hobbs wrote:
> On 2020-07-26 09:53, Chris Jones wrote: >> On 26/07/2020 04:10, Phil Hobbs wrote: >>> On 2020-07-25 11:40, Chris Jones wrote: >>>> On 25/07/2020 04:38, Phil Hobbs wrote: >>>>> On 2020-07-24 10:22, Chris Jones wrote: >>>>>> On 24/07/2020 23:10, Phil Hobbs wrote: >>>>>>> On 2020-07-24 07:43, Chris Jones wrote: >>>>>>>> On 24/07/2020 16:32, Phil Hobbs wrote: >>>>>>>>> On 2020-07-23 22:16, Chris Jones wrote: >>>>>>>>>> On 24/07/2020 09:14, Phil Hobbs wrote: >>>>>>>>>>> On 2020-07-23 16:25, Ricketty C wrote: >>>>>>>>>>>> On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, >>>>>>>>>>>> pcdh...@gmail.com wrote: >>>>>>>>>>>>>> I guess I'm not following what this gains?&Acirc;&nbsp; You >>>>>>>>>>>>>> get lots more steps, but >you don't know any more >>>>>>>>>>>>>> about where they are. What am I missing? >>>>>>>>>>>>> >>>>>>>>>>>>> What it gets me is a combination of settability and >>>>>>>>>>>>> bandwidth that I can't get in any single part at >>>>>>>>>>>>> any price. I'll dump in a bit of pseudorandom DNL >>>>>>>>>>>>> and see if that causes any issues. I don't expect >>>>>>>>>>>>> it to--it'll get homogenized much like the regular >>>>>>>>>>>>> steps. >>>>>>>>>>>>> >>>>>>>>>>>>> For an iterative adjustment (think LC filter >>>>>>>>>>>>> tuning) I can get close by setting the fine pot to >>>>>>>>>>>>> 0, adjusting the coarse pot, then walking the two >>>>>>>>>>>>> together to find the optimum. Near full scale the >>>>>>>>>>>>> possible search range is wider, but I don't think >>>>>>>>>>>>> it'll take too long provided that I'm willing to >>>>>>>>>>>>> settle for "good enough" rather than a global optimum. >>>>>>>>>>>>> >>>>>>>>>>>>> There are two mildly-interacting adjustments, but >>>>>>>>>>>>> the response surface is simple--no local minima. >>>>>>>>>>>>> >>>>>>>>>>>>> It's for taking out the effect of extrinsic emitter >>>>>>>>>>>>> resistance in the BJT diff pair that's the heart of >>>>>>>>>>>>> the circuit. It works by applying a signal to one >>>>>>>>>>>>> of the bases that cancels out the effective emitter >>>>>>>>>>>>> degeneration and so restores the desired Ebers-Moll >>>>>>>>>>>>> behaviour at higher photocurrents. >>>>>>>>>>>>> >>>>>>>>>>>>> If I feel like getting fancy, once I've found the right >>>>>>>>>>>>> neighbourhood I can give the turd a final >>>>>>>>>>>>> polish to get a bit closer. ;) >>>>>>>>>>>>> >>>>>>>>>>>>> There are non-negligible effects such as the tempco >>>>>>>>>>>>> of wiper resistance that limit how good this >>>>>>>>>>>>> approach can be. Sure beats a trimpot on a motor >>>>>>>>>>>>> though! >>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> Ok, so this circuit is not a real time control loop >>>>>>>>>>>> as much as it is like a successive approximation. >>>>>>>>>>>> You don't mind the value varying unpredictably as >>>>>>>>>>>> long as it eventually reaches a setting. >>>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> Right.&Acirc;&nbsp; It'll be done only occasionally, since R_E of a >>>>>>>>>>> BJT is a weak function of everything.&Acirc;&nbsp; In a diff pair, >>>>>>>>>>> R_E produces degeneration, which tends to make the >>>>>>>>>>> current split by the ratios of the R_E values, whereas >>>>>>>>>>> we want it to do the Ebers-Moll thing and split >>>>>>>>>>> strictly as exp(delta V_BE/kT):1.&Acirc;&nbsp; R_E degeneration >>>>>>>>>>> generally dominates the error budget at higher >>>>>>>>>>> photocurrents. >>>>>>>>>>> >>>>>>>>>>> If transistors Q1 and Q2 have resistances R_E1 and >>>>>>>>>>> R_E2, then the required voltage is >>>>>>>>>>> >>>>>>>>>>> dV_BEcor = I_E2 * R_E2&Acirc;&nbsp; - I_E1 * R_E1. >>>>>>>>>>> >>>>>>>>>>> Since V_B1 is controlled by a feedback loop trying to >>>>>>>>>>> make the total DC current from two or more photodiodes >>>>>>>>>>> cancel out, the correction voltage gets applied to the >>>>>>>>>>> base of Q2. Since the resistances are nearly constant, >>>>>>>>>>> rapid adjustment of the correction law is not >>>>>>>>>>> required. >>>>>>>>>>> >>>>>>>>>>> However, the unwanted degeneration applies at AC as >>>>>>>>>>> well as DC, and the attainable benefit is limited by >>>>>>>>>>> phase shift and amplitude error in the correction >>>>>>>>>>> voltage.&Acirc;&nbsp; Thus I do need to form the correction in >>>>>>>>>>> analogue with as high a bandwidth as reasonably >>>>>>>>>>> possible. >>>>>>>>>>> >>>>>>>>>>> There'll be a cal table in flash, which will probably >>>>>>>>>>> rely on the AD5273's decent DNL to interpolate >>>>>>>>>>> relatively coarsely between steps--aiming for, say, >>>>>>>>>>> 8-bit accuracy. That's potentially enough to reduce the >>>>>>>>>>> degeneration effect by 50 dB in the spherical cow >>>>>>>>>>> universe. >>>>>>>>>>> >>>>>>>>>>> Then there'll be a magic pushbutton on the box so that >>>>>>>>>>> users in lab settings can tell it that their experiment >>>>>>>>>>> is all set up, so please optimize the noise >>>>>>>>>>> cancellation for these exact conditions.&Acirc;&nbsp; Nobody will >>>>>>>>>>> mind if that takes 5 seconds or so.&Acirc;&nbsp; (The command will >>>>>>>>>>> be available electronically as well--USB serial or >>>>>>>>>>> maybe a dedicated control line.) >>>>>>>>>>> >>>>>>>>>>> The magic BFP640, with its ~1-kV Early voltage, >>>>>>>>>>> excellent saturation behaviour, and ultralow C_CB, >>>>>>>>>>> allows all sorts of cute tricks. I'm dorking V_CE on >>>>>>>>>>> one side of the diff pair in real time to force the >>>>>>>>>>> power dissipation of Q1 and Q2 to be equal irrespective >>>>>>>>>>> of the splitting ratio (within limits). >>>>>>>>>>> >>>>>>>>>>> With some routed slots to control local temperature >>>>>>>>>>> gradients, it looks like I can get performance >>>>>>>>>>> equivalent to a 40-GHz monolithic dual. (We'll see how >>>>>>>>>>> spherical the cows are in real life--I've seen some >>>>>>>>>>> pretty fat ones.) ;) >>>>>>>>>>> >>>>>>>>>>> Fun. >>>>>>>>>>> >>>>>>>>>>> Cheers >>>>>>>>>>> >>>>>>>>>>> Phil Hobbs >>>>>>>>>>> >>>>>>>>>>> (Who's stocking up on BFP640s as he did on BF862s) >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> By the way, I don't know if you've seen this, but google >>>>>>>>>> and skywater fab are open-sourcing the PDK for a 0.13um >>>>>>>>>> CMOS process, and google is paying for some free shuttle >>>>>>>>>> runs, subject to certain rules including that all designs >>>>>>>>>> be open-sourced too. >>>>>>>>>> >>>>>>>>>> If you can think of anything that you really wish you >>>>>>>>>> could get on a chip, and that can be made in CMOS, and >>>>>>>>>> that is useful to you but not secret enough to not want >>>>>>>>>> to publish the design, now is the time! Shuttle run in >>>>>>>>>> November and you get hundreds of parts back, so maybe >>>>>>>>>> enough for a low-volume product. Lots of people are >>>>>>>>>> playing with the tools so quite likely someone else would >>>>>>>>>> lay it out for fun if you didn't have time. >>>>>>>>>> >>>>>>>>>> There is a link to the slack workspace here, with many >>>>>>>>>> more details: >>>>>>>>>> >>>>>>>>>> https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4 >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>> >>>>>>>>> Sounds like a good opportunity for sure.&Acirc;&nbsp; If somebody would >>>>>>>>> do that with a decent low-noise analogue bipolar process >>>>>>>>> (say 0.5 um) I'd be all over it. >>>>>>>>> >>>>>>>>> Cheers >>>>>>>>> >>>>>>>>> Phil Hobbs >>>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> I'd welcome ideas anyway. Even if there is only a small >>>>>>>> chance of it working in CMOS, it might be worth trying, maybe >>>>>>>> even just on the corner of someone else's chip. >>>>>>>> >>>>>>>> I'm mostly interested in trying something that takes little >>>>>>>> effort but that could not be replicated easily using >>>>>>>> off-the-shelf parts. Maybe a trigger comparator + adjustable >>>>>>>> delay + sampler with several channels, for a sampling scope >>>>>>>> frontend. Even just a beefy inverter in 0.13um might make a >>>>>>>> nice fast edge generator for testing scope risetime, >>>>>>>> especially as it'll be a flipchip chipscale package thing so >>>>>>>> no bondwires. If there is a usable bipolar then I might do a >>>>>>>> bandgap reference / LDO and see what noise performance I can >>>>>>>> get from burning a few mA rather than the few uA that they >>>>>>>> usually allow themselves. I quite likely won't have time >>>>>>>> though. >>>>>>>> >>>>>>> >>>>>>> Well, a high-bandwidth dpot/attenuator comes to mind. >>>>>>> Something around 1-2k and 8 bits, maybe an R-2R thing.&Acirc;&nbsp; If the >>>>>>> switches were as good as the TMUX1511's, it could be pretty >>>>>>> swoopy. >>>>>> >>>>>> The best bandwidth would come from using 0.13um (behaving more >>>>>> like 0.18um I hear) NMOS-only switches but they are nominally >>>>>> 1.8V devices so might not be useful for some of your purposes >>>>>> (and driving the gates would get tricky if you need to use much >>>>>> of that range). How much swing will your DPOT see, and do you >>>>>> really want a true pot or just a variable resisor (rheostat)? >>>>>> What is the DC bias on it? >>>>> >>>>> I'd be willing to be very flexible in exchange for, say, 100 MHz >>>>> BW. The present application needs to put about +-20 mV across an >>>>> ohm or two or five, to compensate the R_E degeneration in the diff >>>>> pair of a laser noise canceller.&Acirc;&nbsp; (Less is better since the BFP640 >>>>> has only about 3 ohms R_B, and it's a shame to waste that sort of >>>>> noise performance.) >>>>> >>>>>> >>>>>> If you wanted a variable resistor with one side grounded then the >>>>>> &Acirc;&nbsp;NMOS might work very well. If you could show me where it will be >>>>>> &Acirc;&nbsp;used, I might have other ideas that are more optimal than a >>>>>> general purpose DPOT. I'm pretty sure I won't come up with a >>>>>> general purpose DPOT better than the two remaining semiconductor >>>>>> companies can do, but I might be able to think of something that >>>>>> solves your circuit problem better. >>>>> >>>>> The circuit is basically Figure 3 in >>>>> <https://electrooptical.net/static/media/uploads/Projects/LaserNoiseCanceller/noisecan.pdf> >>>>> >>>>> >>>>> >>>>> with the modifications of Figures 12 (R_E cancellation) and 19 >>>>> (differential/high power version that reduces the current in the >>>>> diff pair).&Acirc;&nbsp; (There's also some mildly complicated bootstrapping >>>>> and cascoding going on, because I can't get fast PNPs anymore, but >>>>> that's for another thread.) >>>>> >>>>> Sticking with Figure 3, overall feedback forces the current through >>>>> D1 to be the same as the collector current of Q2. (In principle, >>>>> this is true at all frequencies regardless of the loop >>>>> bandwidth--that's why the circuit works.)&Acirc;&nbsp; In Figure 12, the >>>>> correction voltage comes directly from Q1's collector current and a >>>>> mirrored version of the tail current of the pair, scaled by a >>>>> couple of low-value trimpots.&Acirc;&nbsp; That's pretty simple and works >>>>> pretty well, as long as the user is a circuits guy with some vague >>>>> clue as to how it all works. >>>>> >>>>> In the current circuit, I'm forcing the dissipation of Q1 to equal >>>>> that of Q2 dorking its V_CE with a DAC controlling another BFP640 >>>>> cascode transistor.&Acirc;&nbsp; That's where the effectively-infinite Early >>>>> voltage comes in handy.&Acirc;&nbsp; With a C-shaped cutout in the board and a >>>>> nice symmetric layout, that ought to keep the transistors within >>>>> 0.1 C of each other. If so, that will basically eliminate >>>>> temperature differences as a limiting factor, just as if I had a >>>>> 40-GHz monolithic dual NPN. >>>>> >>>>> Since I need to control VC(Q1), I can't just dump IC(Q1) into the >>>>> compensation network.&Acirc;&nbsp; (I also can't get an electronically >>>>> controllable equivalent to a 10-ohm trimpot.)&Acirc;&nbsp; Anyway, D1 needs >>>>> some reverse bias. >>>>> >>>>> Soooo, instead I'm using floating ADA4817 TIAs: one in the >>>>> collector of the cascode to measure IC(Q1)) and one in the cathode >>>>> of D1 to measure IC(Q2).&Acirc;&nbsp; I'm forming the correction term by a >>>>> 499-ohm resistor in one TIA and one of these compound dpot gizmos >>>>> in the other.&Acirc;&nbsp; An LM6171 and four 0.025% resistors are doing the >>>>> diff amp honours to do the subtraction and shift the difference >>>>> signal to near ground.&Acirc;&nbsp; (If I could get a 100-MHz instrumentation >>>>> amp that handled 30-V supplies, I'd use that instead.) >>>>> >>>>> After the diff amp, there's a 499/100 ohm voltage divider, followed >>>>> by another of these dpot gizmos running off +-2.5V to divide that >>>>> voltage down to the +-20 mV level.&Acirc;&nbsp; The divider protects the dpots >>>>> from overvoltage, >>>> So far so good, I think I understand up to here... >>>> >>>>> and besides there's a bias current in D1's bootstrap circuit that I >>>>> need to cancel out--the current goes into the 499-ohm TIA so I need >>>>> a 499 ohm load to cancel it.) >>>> Ok now I am confused about this bit. >>> >>> The bootstraps/cascodes are Darlington-connected BFP640s, each with a >>> 5-ohm bead in series with the base.&Acirc;&nbsp; The beads turn them from twitchy >>> magic Ferraris into boring magic Hondas--they keep their 500 beta, 1 kV >>> Early voltage, 0.3 nV 1-Hz flatband noise, and 0.6 ohm R_E, but become >>> nice and stable although probably 20x slower.&Acirc;&nbsp; However, the combo's >>> rolloff is roughly quadratic rather than linear below about 500 MHz, so >>> from DC to VHF they're nearly indistinguishable from the untouched magic >>> microwave transistor. >>> >>> In the present application, I'm aiming for accuracies of around 1 part >>> in 10**4 over a 100:1 range of photocurrent, 50 uA to 5 mA.&Acirc;&nbsp; (The >>> complete instrument won't be quite that good--this is the budget per >>> photodiode.)&Acirc;&nbsp; So the bootstraps and cascodes are Darlingtons with >>> additional external bias for the driver transistor to keep the bandwidth >>> from going into the tank at low photocurrent.(*)&Acirc;&nbsp; For a normal >>> photodiode bootstrap, where we measure the end that goes to the TIA and >>> jiggle the end that goes to the bias supply, there's no issue--we don't >>> care about mixing the photocurrent and bias current on that end of the >>> device. >>> >>> However, since there are no fast PNPs available anymore, we have to >>> bootstrap D1 with NPNs cascode-style: measure the anode and jiggle the >>> cathode.&Acirc;&nbsp; That means that we have to get our photocurrent measurement >>> from the collectors of the Darlington.&Acirc;&nbsp; Since both collectors connect to >>> the TIA input, the external bias current for the driver transistor >>> corrupts the TIA's output. >>> >>> That bias comes via a 10k resistor connected someplace near ground, so >>> since I chose that TIA to be the one with the fixed 499-ohm resistor, >>> the output is in error by about 499 ohms * Vbias/10k ohms. >>> Conveniently, that TIA connects to the - input of the diff amp, so the >>> bias current makes the diff amp's output go too low. >>> >>> Thus by hanging a 499 ohm resistor in series with the diff amp output, I >>> can null out the offset by simply connecting the other end of the 10k >>> resistor to the far&Acirc;&nbsp; end of the 499 ohms.&Acirc;&nbsp; As the diff amp output >>> changes, the bias current will change a little, but Kirchhoff says it'll >>> stay nulled.&Acirc;&nbsp; ;) This is true regardless of the 499 / 100 ohm >>> divider--it works at any ratio. >>> >>>>> A rheostat with one end near ground but not actually connected >>>>> there would do fine in both places >>>> In the place where the 20 Ohm pot is shown in the circuit of fig. 12 >>>> I guess one end really would be grounded, unless I misunderstand. >>>> >>>> In the other DPOT location, I understand this to be the feedback >>>> resistor of the TIA that senses the current in Q1. I it seems to me >>>> that this one is biased up at whatever voltage you need for achieving >>>> the right amount of heating in Q1, so it would not be possible for >>>> the second DPOT to reside on the same die as the first DPOT that >>>> feeds the base of Q1, which is sad. >>> >>> Yeah, their supplies are offset by like 18V from each other, but I'm >>> totally happy using two chips.&Acirc;&nbsp; If I wind up wiring VSS of the dpot to >>> the TIA input it'd have to be a single anyway. >>> >>> &Acirc;&nbsp;&Acirc;&nbsp;> So, maybe there isn't a dpot on the base of Q1 >>>> but a fixed resistive divider, and do the scaling elsewhere... >>>> >>>> Do both floating ADA4817 TIAs opamps share the same voltage on their >>>> &Acirc;&nbsp;non-inverting inputs? >>> >>> Yes. They're both connected to a 'floating ground' hung 5V below the >>> main VCC rail.&Acirc;&nbsp; Their VEE pins are a couple of volts below that.&Acirc;&nbsp; Both >>> rails courtesy of that TCA0372 I was whining about on another thread. ;) >>> >>>> Otherwise I don't understand how the LM6171 and four 0.025% resistor >>>> diff amp would manage the subtraction without further complication. >>>> If the TIAs are biased up at the same voltage, then I guess both TIAs >>>> could use the new wideband DPOTs/rheostats and could float up there >>>> together on the same die. >>> >>> I think that would probably work fine, as long as the bottom end of >>> the rheostats were separate rather than connecting directly to VSS. >>> >>> Since the input transistor of the D1 Darlington is above the >>> floating ground and the voltage drop doesn't vary rapidly, I could >>> probably get rid of the bias current effect adequately using another >>> dpot and software to distribute it between the two TIAs correctly. >>> >>>> So the gains of both TIAs would be adjusted separately and the the >>>> results of that would get subtracted and shifted down by the diff amp >>>> and scaled by a fixed resistive divider to feed the base of Q1. I am >>>> guessing that in this case you would want a ~500 Ohm value rheostat >>>> for each TIA, but might have to go for a lower value in order to >>>> limit the voltage at the end of the rheostat. >>> I'm totally happy bootstrapping the supplies in any way necessary, so >>> as long as the cold ends of the rheostats aren't both grounded, we're >>> good. >>> >>>> >>>>> and I could live with 2V supplies if I had to.&Acirc;&nbsp; If I really had to, >>>>> I could run the dpot's ground pin into the TIA and fix up the >>>>> quiescent current afterwards. >>>> Do you mean the wiper, or the VSS? VSS of the dpot thing could be >>>> driven by whatever sets the non-inverting input of the TIA opamps, I >>>> think. >>>> >>>> One part I don't understand is the correction of bootstrap bias >>>> current that you mentioned. If only usenet had a whiteboard. >>> >>> I hope I've explained it adequately.&Acirc;&nbsp; I'll happily post a schematic >>> fragment if needed. >> I'm afraid I am still very confused, after trying quite hard to >> interpret your explanation in the context of Fig. 3 from your link. I >> appreciate that you have put a lot of work into the explanation, and I >> was going to point out each part that I didn't understand, but I think >> re-explaining all of that in text would perhaps not be an efficient >> use of your time. >> >> I think part of it is that avoiding the PNP probably makes the circuit >> fairly different from Fig. 3, and part of it is that I am imagining >> that there are three TIAs (the main one for the subtracted >> photocurrents that produces the final output, and one for monitoring >> the collector current of each transistor in the diff pair that does >> the current splitting), but it is not always clear to me in each case >> which TIA you are referring to above. >> >> If you could post a schematic, that would be very efficient, however I >> would understand if you prefer not to do that unless privately under >> formal or informal NDA, in which case I've sent you an e-mail by which >> we could arrange that if necessary. >> >> Curiousity aside, for implementing a fast DPOT the main thing I think >> I am missing is an understanding of how the bias current (of the >> Darlington) gets subtracted out, and how the diffamp is connected. >> Given that the tempco of the dpot resistors (and initial tolerance) is >> likely to be truly awful, there might be an advantage in implementing >> the two input resistors of the diffamp on-chip using the exact same >> awful tempco as the DPOT, to take out the gain drift. It may not >> matter that the voltage on one end of those unswitched resistors goes >> well outside the rails, as long as I am allowed to get creative with >> the ESD protection cells. >> >>> >>>> Also this whole circuit would be great in a fast complementary >>>> bipolar process like XFCB3. Oh well. >>>> >>>> Stuck with CMOS, it is tempting to also try some sort of multiplying >>>> current DAC to scale the comparison photodiode current until it is >>>> equal to the signal photodiode current. Getting enough resolution for >>>> good cancellation, and over a wide bandwidth sounds very hard though. >>>> Also it would only ever work for cases where the ratio of the >>>> photocurrents is pretty constant over a measurement run. >>> >>> It's generally pretty well that way. >> >> Most of the ideas that I have come up with involve a fast PNP >> somewhere. I wonder how good a 0.13um PMOS is, and if there is a way >> to use it that does not rely on decent "Early voltage" (or the fet >> equivalent), nor care about 1/f noise. >> >> > > Sorry for the obscurity.&Acirc;&nbsp; I posted the relevant part of the circuit at > <https://electrooptical.net/static/oldsite/www/sed/cloud9detail.png>. > (The name is a parody of New Focus's 'Nirvana', which I never did like.) > > There aren't any ref des yet--I assign them while I'm doing the BOM, > which helps prevent missing or duplicated designators. > > The VFG ('floating ground') and VFN('floating negative') come from the > TCA0372. > > The bias current that needs cancelling is tagged ITAIL and is around 1 mA. > > The flags DUMPM, VC1, VC2, VB1, VB2, VDISS, and VE are for the R_E and > power dissipation compensation facilities.
Thanks, that helped a lot. In the worst case, what current does each TIA need to deal with? What bandwidth do you get from the LM6171 stage with the 10k resistors? I wonder whether you'd be able to use an AD8130 instead, and get rid of the 0.025% resistors. (The TIAs would need lower resistor values to keep the signal small enough I guess.) If the AD8130 had low enough input current and current noise, perhaps you could just put the two high bandwidth custom DPOTs as plain resistive loads fed from the collectors of the BFP640s, instead of putting them into TIAs. That would save two opamps but would throw away the nice possibility of correcting the dpot resistor tempco that I mentioned last time. I'd better go and sleep but I'll have another think when I get a chance.
On 2020-07-27 10:54, Chris Jones wrote:
> On 27/07/2020 01:11, Phil Hobbs wrote: >> On 2020-07-26 09:53, Chris Jones wrote: >>> On 26/07/2020 04:10, Phil Hobbs wrote: >>>> On 2020-07-25 11:40, Chris Jones wrote: >>>>> On 25/07/2020 04:38, Phil Hobbs wrote: >>>>>> On 2020-07-24 10:22, Chris Jones wrote: >>>>>>> On 24/07/2020 23:10, Phil Hobbs wrote: >>>>>>>> On 2020-07-24 07:43, Chris Jones wrote: >>>>>>>>> On 24/07/2020 16:32, Phil Hobbs wrote: >>>>>>>>>> On 2020-07-23 22:16, Chris Jones wrote: >>>>>>>>>>> On 24/07/2020 09:14, Phil Hobbs wrote: >>>>>>>>>>>> On 2020-07-23 16:25, Ricketty C wrote: >>>>>>>>>>>>> On Thursday, July 23, 2020 at 7:39:36 AM >>>>>>>>>>>>> UTC-4, pcdh...@gmail.com wrote: >>>>>>>>>>>>>>> I guess I'm not following what this >>>>>>>>>>>>>>> gains? You get lots more steps, but >>>>>>>>>>>>>>> >you don't know any more about where they >>>>>>>>>>>>>>> are. What am I missing? >>>>>>>>>>>>>> >>>>>>>>>>>>>> What it gets me is a combination of >>>>>>>>>>>>>> settability and bandwidth that I can't get >>>>>>>>>>>>>> in any single part at any price. I'll dump >>>>>>>>>>>>>> in a bit of pseudorandom DNL and see if >>>>>>>>>>>>>> that causes any issues. I don't expect it >>>>>>>>>>>>>> to--it'll get homogenized much like the >>>>>>>>>>>>>> regular steps. >>>>>>>>>>>>>> >>>>>>>>>>>>>> For an iterative adjustment (think LC >>>>>>>>>>>>>> filter tuning) I can get close by setting >>>>>>>>>>>>>> the fine pot to 0, adjusting the coarse >>>>>>>>>>>>>> pot, then walking the two together to find >>>>>>>>>>>>>> the optimum. Near full scale the possible >>>>>>>>>>>>>> search range is wider, but I don't think >>>>>>>>>>>>>> it'll take too long provided that I'm >>>>>>>>>>>>>> willing to settle for "good enough" rather >>>>>>>>>>>>>> than a global optimum. >>>>>>>>>>>>>> >>>>>>>>>>>>>> There are two mildly-interacting >>>>>>>>>>>>>> adjustments, but the response surface is >>>>>>>>>>>>>> simple--no local minima. >>>>>>>>>>>>>> >>>>>>>>>>>>>> It's for taking out the effect of >>>>>>>>>>>>>> extrinsic emitter resistance in the BJT >>>>>>>>>>>>>> diff pair that's the heart of the circuit. >>>>>>>>>>>>>> It works by applying a signal to one of the >>>>>>>>>>>>>> bases that cancels out the effective >>>>>>>>>>>>>> emitter degeneration and so restores the >>>>>>>>>>>>>> desired Ebers-Moll behaviour at higher >>>>>>>>>>>>>> photocurrents. >>>>>>>>>>>>>> >>>>>>>>>>>>>> If I feel like getting fancy, once I've >>>>>>>>>>>>>> found the right neighbourhood I can give >>>>>>>>>>>>>> the turd a final polish to get a bit >>>>>>>>>>>>>> closer. ;) >>>>>>>>>>>>>> >>>>>>>>>>>>>> There are non-negligible effects such as >>>>>>>>>>>>>> the tempco of wiper resistance that limit >>>>>>>>>>>>>> how good this approach can be. Sure beats >>>>>>>>>>>>>> a trimpot on a motor though! >>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> Ok, so this circuit is not a real time >>>>>>>>>>>>> control loop as much as it is like a >>>>>>>>>>>>> successive approximation. You don't mind the >>>>>>>>>>>>> value varying unpredictably as long as it >>>>>>>>>>>>> eventually reaches a setting. >>>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> Right. It'll be done only occasionally, since >>>>>>>>>>>> R_E of a BJT is a weak function of everything. >>>>>>>>>>>> In a diff pair, R_E produces degeneration, >>>>>>>>>>>> which tends to make the current split by the >>>>>>>>>>>> ratios of the R_E values, whereas we want it >>>>>>>>>>>> to do the Ebers-Moll thing and split strictly >>>>>>>>>>>> as exp(delta V_BE/kT):1. R_E degeneration >>>>>>>>>>>> generally dominates the error budget at higher >>>>>>>>>>>> photocurrents. >>>>>>>>>>>> >>>>>>>>>>>> If transistors Q1 and Q2 have resistances R_E1 >>>>>>>>>>>> and R_E2, then the required voltage is >>>>>>>>>>>> >>>>>>>>>>>> dV_BEcor = I_E2 * R_E2 - I_E1 * R_E1. >>>>>>>>>>>> >>>>>>>>>>>> Since V_B1 is controlled by a feedback loop >>>>>>>>>>>> trying to make the total DC current from two >>>>>>>>>>>> or more photodiodes cancel out, the correction >>>>>>>>>>>> voltage gets applied to the base of Q2. Since >>>>>>>>>>>> the resistances are nearly constant, rapid >>>>>>>>>>>> adjustment of the correction law is not >>>>>>>>>>>> required. >>>>>>>>>>>> >>>>>>>>>>>> However, the unwanted degeneration applies at >>>>>>>>>>>> AC as well as DC, and the attainable benefit >>>>>>>>>>>> is limited by phase shift and amplitude error >>>>>>>>>>>> in the correction voltage. Thus I do need to >>>>>>>>>>>> form the correction in analogue with as high a >>>>>>>>>>>> bandwidth as reasonably possible. >>>>>>>>>>>> >>>>>>>>>>>> There'll be a cal table in flash, which will >>>>>>>>>>>> probably rely on the AD5273's decent DNL to >>>>>>>>>>>> interpolate relatively coarsely between >>>>>>>>>>>> steps--aiming for, say, 8-bit accuracy. That's >>>>>>>>>>>> potentially enough to reduce the degeneration >>>>>>>>>>>> effect by 50 dB in the spherical cow universe. >>>>>>>>>>>> >>>>>>>>>>>> Then there'll be a magic pushbutton on the box >>>>>>>>>>>> so that users in lab settings can tell it that >>>>>>>>>>>> their experiment is all set up, so please >>>>>>>>>>>> optimize the noise cancellation for these >>>>>>>>>>>> exact conditions. Nobody will mind if that >>>>>>>>>>>> takes 5 seconds or so. (The command will be >>>>>>>>>>>> available electronically as well--USB serial or >>>>>>>>>>>> maybe a dedicated control line.) >>>>>>>>>>>> >>>>>>>>>>>> The magic BFP640, with its ~1-kV Early voltage, >>>>>>>>>>>> excellent saturation behaviour, and ultralow >>>>>>>>>>>> C_CB, allows all sorts of cute tricks. I'm >>>>>>>>>>>> dorking V_CE on one side of the diff pair in >>>>>>>>>>>> real time to force the power dissipation of Q1 >>>>>>>>>>>> and Q2 to be equal irrespective of the >>>>>>>>>>>> splitting ratio (within limits). >>>>>>>>>>>> >>>>>>>>>>>> With some routed slots to control local >>>>>>>>>>>> temperature gradients, it looks like I can get >>>>>>>>>>>> performance equivalent to a 40-GHz monolithic >>>>>>>>>>>> dual. (We'll see how spherical the cows are in >>>>>>>>>>>> real life--I've seen some pretty fat ones.) ;) >>>>>>>>>>>> >>>>>>>>>>>> Fun. >>>>>>>>>>>> >>>>>>>>>>>> Cheers >>>>>>>>>>>> >>>>>>>>>>>> Phil Hobbs >>>>>>>>>>>> >>>>>>>>>>>> (Who's stocking up on BFP640s as he did on >>>>>>>>>>>> BF862s) >>>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> By the way, I don't know if you've seen this, >>>>>>>>>>> but google and skywater fab are open-sourcing the >>>>>>>>>>> PDK for a 0.13um CMOS process, and google is >>>>>>>>>>> paying for some free shuttle runs, subject to >>>>>>>>>>> certain rules including that all designs be >>>>>>>>>>> open-sourced too. >>>>>>>>>>> >>>>>>>>>>> If you can think of anything that you really >>>>>>>>>>> wish you could get on a chip, and that can be >>>>>>>>>>> made in CMOS, and that is useful to you but not >>>>>>>>>>> secret enough to not want to publish the design, >>>>>>>>>>> now is the time! Shuttle run in November and you >>>>>>>>>>> get hundreds of parts back, so maybe enough for >>>>>>>>>>> a low-volume product. Lots of people are playing >>>>>>>>>>> with the tools so quite likely someone else would >>>>>>>>>>> lay it out for fun if you didn't have time. >>>>>>>>>>> >>>>>>>>>>> There is a link to the slack workspace here, >>>>>>>>>>> with many more details: >>>>>>>>>>> >>>>>>>>>>> https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4 >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> Sounds like a good opportunity for sure. If >>>>>>>>>> somebody would do that with a decent low-noise >>>>>>>>>> analogue bipolar process (say 0.5 um) I'd be all >>>>>>>>>> over it. >>>>>>>>>> >>>>>>>>>> Cheers >>>>>>>>>> >>>>>>>>>> Phil Hobbs >>>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> I'd welcome ideas anyway. Even if there is only a >>>>>>>>> small chance of it working in CMOS, it might be >>>>>>>>> worth trying, maybe even just on the corner of >>>>>>>>> someone else's chip. >>>>>>>>> >>>>>>>>> I'm mostly interested in trying something that takes >>>>>>>>> little effort but that could not be replicated >>>>>>>>> easily using off-the-shelf parts. Maybe a trigger >>>>>>>>> comparator + adjustable delay + sampler with several >>>>>>>>> channels, for a sampling scope frontend. Even just a >>>>>>>>> beefy inverter in 0.13um might make a nice fast edge >>>>>>>>> generator for testing scope risetime, especially as >>>>>>>>> it'll be a flipchip chipscale package thing so no >>>>>>>>> bondwires. If there is a usable bipolar then I might >>>>>>>>> do a bandgap reference / LDO and see what noise >>>>>>>>> performance I can get from burning a few mA rather >>>>>>>>> than the few uA that they usually allow themselves. >>>>>>>>> I quite likely won't have time though. >>>>>>>>> >>>>>>>> >>>>>>>> Well, a high-bandwidth dpot/attenuator comes to mind. >>>>>>>> Something around 1-2k and 8 bits, maybe an R-2R thing. >>>>>>>> If the switches were as good as the TMUX1511's, it >>>>>>>> could be pretty swoopy. >>>>>>> >>>>>>> The best bandwidth would come from using 0.13um >>>>>>> (behaving more like 0.18um I hear) NMOS-only switches but >>>>>>> they are nominally 1.8V devices so might not be useful >>>>>>> for some of your purposes (and driving the gates would >>>>>>> get tricky if you need to use much of that range). How >>>>>>> much swing will your DPOT see, and do you really want a >>>>>>> true pot or just a variable resisor (rheostat)? What is >>>>>>> the DC bias on it? >>>>>> >>>>>> I'd be willing to be very flexible in exchange for, say, >>>>>> 100 MHz BW. The present application needs to put about >>>>>> +-20 mV across an ohm or two or five, to compensate the >>>>>> R_E degeneration in the diff pair of a laser noise >>>>>> canceller. (Less is better since the BFP640 has only about >>>>>> 3 ohms R_B, and it's a shame to waste that sort of noise >>>>>> performance.) >>>>>> >>>>>>> >>>>>>> If you wanted a variable resistor with one side grounded >>>>>>> then the NMOS might work very well. If you could show me >>>>>>> where it will be used, I might have other ideas that are >>>>>>> more optimal than a general purpose DPOT. I'm pretty >>>>>>> sure I won't come up with a general purpose DPOT better >>>>>>> than the two remaining semiconductor companies can do, >>>>>>> but I might be able to think of something that solves >>>>>>> your circuit problem better. >>>>>> >>>>>> The circuit is basically Figure 3 in >>>>>> <https://electrooptical.net/static/media/uploads/Projects/LaserNoiseCanceller/noisecan.pdf> >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> with the modifications of Figures 12 (R_E cancellation) >>>>>> and 19 (differential/high power version that reduces the >>>>>> current in the diff pair). (There's also some mildly >>>>>> complicated bootstrapping and cascoding going on, because >>>>>> I can't get fast PNPs anymore, but that's for another >>>>>> thread.) >>>>>> >>>>>> Sticking with Figure 3, overall feedback forces the >>>>>> current through D1 to be the same as the collector current >>>>>> of Q2. (In principle, this is true at all frequencies >>>>>> regardless of the loop bandwidth--that's why the circuit >>>>>> works.) In Figure 12, the correction voltage comes >>>>>> directly from Q1's collector current and a mirrored version >>>>>> of the tail current of the pair, scaled by a couple of >>>>>> low-value trimpots. That's pretty simple and works pretty >>>>>> well, as long as the user is a circuits guy with some vague >>>>>> clue as to how it all works. >>>>>> >>>>>> In the current circuit, I'm forcing the dissipation of Q1 >>>>>> to equal that of Q2 dorking its V_CE with a DAC >>>>>> controlling another BFP640 cascode transistor. That's >>>>>> where the effectively-infinite Early voltage comes in >>>>>> handy. With a C-shaped cutout in the board and a nice >>>>>> symmetric layout, that ought to keep the transistors within >>>>>> 0.1 C of each other. If so, that will basically eliminate >>>>>> temperature differences as a limiting factor, just as if I >>>>>> had a 40-GHz monolithic dual NPN. >>>>>> >>>>>> Since I need to control VC(Q1), I can't just dump IC(Q1) >>>>>> into the compensation network. (I also can't get an >>>>>> electronically controllable equivalent to a 10-ohm >>>>>> trimpot.) Anyway, D1 needs some reverse bias. >>>>>> >>>>>> Soooo, instead I'm using floating ADA4817 TIAs: one in the >>>>>> collector of the cascode to measure IC(Q1)) and one in >>>>>> the cathode of D1 to measure IC(Q2). I'm forming the >>>>>> correction term by a 499-ohm resistor in one TIA and one >>>>>> of these compound dpot gizmos in the other. An LM6171 and >>>>>> four 0.025% resistors are doing the diff amp honours to do >>>>>> the subtraction and shift the difference signal to near >>>>>> ground. (If I could get a 100-MHz instrumentation amp >>>>>> that handled 30-V supplies, I'd use that instead.) >>>>>> >>>>>> After the diff amp, there's a 499/100 ohm voltage divider, >>>>>> followed by another of these dpot gizmos running off >>>>>> +-2.5V to divide that voltage down to the +-20 mV level. >>>>>> The divider protects the dpots from overvoltage, >>>>> So far so good, I think I understand up to here... >>>>> >>>>>> and besides there's a bias current in D1's bootstrap >>>>>> circuit that I need to cancel out--the current goes into >>>>>> the 499-ohm TIA so I need a 499 ohm load to cancel it.) >>>>> Ok now I am confused about this bit. >>>> >>>> The bootstraps/cascodes are Darlington-connected BFP640s, each >>>> with a 5-ohm bead in series with the base. The beads turn >>>> them from twitchy magic Ferraris into boring magic Hondas--they >>>> keep their 500 beta, 1 kV Early voltage, 0.3 nV 1-Hz flatband >>>> noise, and 0.6 ohm R_E, but become nice and stable although >>>> probably 20x slower. However, the combo's rolloff is roughly >>>> quadratic rather than linear below about 500 MHz, so from DC to >>>> VHF they're nearly indistinguishable from the untouched magic >>>> microwave transistor. >>>> >>>> In the present application, I'm aiming for accuracies of >>>> around 1 part in 10**4 over a 100:1 range of photocurrent, 50 >>>> uA to 5 mA. (The complete instrument won't be quite that >>>> good--this is the budget per photodiode.) So the bootstraps >>>> and cascodes are Darlingtons with additional external bias for >>>> the driver transistor to keep the bandwidth from going into the >>>> tank at low photocurrent.(*) For a normal photodiode >>>> bootstrap, where we measure the end that goes to the TIA and >>>> jiggle the end that goes to the bias supply, there's no >>>> issue--we don't care about mixing the photocurrent and bias >>>> current on that end of the device. >>>> >>>> However, since there are no fast PNPs available anymore, we >>>> have to bootstrap D1 with NPNs cascode-style: measure the >>>> anode and jiggle the cathode. That means that we have to get >>>> our photocurrent measurement from the collectors of the >>>> Darlington. Since both collectors connect to the TIA input, the >>>> external bias current for the driver transistor corrupts the >>>> TIA's output. >>>> >>>> That bias comes via a 10k resistor connected someplace near >>>> ground, so since I chose that TIA to be the one with the fixed >>>> 499-ohm resistor, the output is in error by about 499 ohms * >>>> Vbias/10k ohms. Conveniently, that TIA connects to the - input >>>> of the diff amp, so the bias current makes the diff amp's >>>> output go too low. >>>> >>>> Thus by hanging a 499 ohm resistor in series with the diff amp >>>> output, I can null out the offset by simply connecting the >>>> other end of the 10k resistor to the far end of the 499 ohms. >>>> As the diff amp output changes, the bias current will change a >>>> little, but Kirchhoff says it'll stay nulled. ;) This is true >>>> regardless of the 499 / 100 ohm divider--it works at any >>>> ratio. >>>> >>>>>> A rheostat with one end near ground but not actually >>>>>> connected there would do fine in both places >>>>> In the place where the 20 Ohm pot is shown in the circuit of >>>>> fig. 12 I guess one end really would be grounded, unless I >>>>> misunderstand. >>>>> >>>>> In the other DPOT location, I understand this to be the >>>>> feedback resistor of the TIA that senses the current in Q1. >>>>> I it seems to me that this one is biased up at whatever >>>>> voltage you need for achieving the right amount of heating in >>>>> Q1, so it would not be possible for the second DPOT to reside >>>>> on the same die as the first DPOT that feeds the base of Q1, >>>>> which is sad. >>>> >>>> Yeah, their supplies are offset by like 18V from each other, >>>> but I'm totally happy using two chips. If I wind up wiring >>>> VSS of the dpot to the TIA input it'd have to be a single >>>> anyway. >>>> >>>>> So, maybe there isn't a dpot on the base of Q1 but a fixed >>>>> resistive divider, and do the scaling elsewhere... >>>>> >>>>> Do both floating ADA4817 TIAs opamps share the same voltage >>>>> on their non-inverting inputs? >>>> >>>> Yes. They're both connected to a 'floating ground' hung 5V >>>> below the main VCC rail. Their VEE pins are a couple of volts >>>> below that. Both rails courtesy of that TCA0372 I was whining >>>> about on another thread. ;) >>>> >>>>> Otherwise I don't understand how the LM6171 and four 0.025% >>>>> resistor diff amp would manage the subtraction without >>>>> further complication. If the TIAs are biased up at the same >>>>> voltage, then I guess both TIAs could use the new wideband >>>>> DPOTs/rheostats and could float up there together on the >>>>> same die. >>>> >>>> I think that would probably work fine, as long as the bottom >>>> end of the rheostats were separate rather than connecting >>>> directly to VSS. >>>> >>>> Since the input transistor of the D1 Darlington is above the >>>> floating ground and the voltage drop doesn't vary rapidly, I >>>> could probably get rid of the bias current effect adequately >>>> using another dpot and software to distribute it between the >>>> two TIAs correctly. >>>> >>>>> So the gains of both TIAs would be adjusted separately and >>>>> the the results of that would get subtracted and shifted >>>>> down by the diff amp and scaled by a fixed resistive divider >>>>> to feed the base of Q1. I am guessing that in this case you >>>>> would want a ~500 Ohm value rheostat for each TIA, but might >>>>> have to go for a lower value in order to limit the voltage >>>>> at the end of the rheostat. >>>> I'm totally happy bootstrapping the supplies in any way >>>> necessary, so as long as the cold ends of the rheostats aren't >>>> both grounded, we're good. >>>> >>>>> >>>>>> and I could live with 2V supplies if I had to. If I >>>>>> really had to, I could run the dpot's ground pin into the >>>>>> TIA and fix up the quiescent current afterwards. >>>>> Do you mean the wiper, or the VSS? VSS of the dpot thing >>>>> could be driven by whatever sets the non-inverting input of >>>>> the TIA opamps, I think. >>>>> >>>>> One part I don't understand is the correction of bootstrap >>>>> bias current that you mentioned. If only usenet had a >>>>> whiteboard. >>>> >>>> I hope I've explained it adequately. I'll happily post a >>>> schematic fragment if needed. >>> I'm afraid I am still very confused, after trying quite hard to >>> interpret your explanation in the context of Fig. 3 from your >>> link. I appreciate that you have put a lot of work into the >>> explanation, and I was going to point out each part that I >>> didn't understand, but I think re-explaining all of that in text >>> would perhaps not be an efficient use of your time. >>> >>> I think part of it is that avoiding the PNP probably makes the >>> circuit fairly different from Fig. 3, and part of it is that I >>> am imagining that there are three TIAs (the main one for the >>> subtracted photocurrents that produces the final output, and one >>> for monitoring the collector current of each transistor in the >>> diff pair that does the current splitting), but it is not always >>> clear to me in each case which TIA you are referring to above. >>> >>> If you could post a schematic, that would be very efficient, >>> however I would understand if you prefer not to do that unless >>> privately under formal or informal NDA, in which case I've sent >>> you an e-mail by which we could arrange that if necessary. >>> >>> Curiousity aside, for implementing a fast DPOT the main thing I >>> think I am missing is an understanding of how the bias current >>> (of the Darlington) gets subtracted out, and how the diffamp is >>> connected. Given that the tempco of the dpot resistors (and >>> initial tolerance) is likely to be truly awful, there might be >>> an advantage in implementing the two input resistors of the >>> diffamp on-chip using the exact same awful tempco as the DPOT, to >>> take out the gain drift. It may not matter that the voltage on >>> one end of those unswitched resistors goes well outside the >>> rails, as long as I am allowed to get creative with the ESD >>> protection cells. >>> >>>> >>>>> Also this whole circuit would be great in a fast >>>>> complementary bipolar process like XFCB3. Oh well. >>>>> >>>>> Stuck with CMOS, it is tempting to also try some sort of >>>>> multiplying current DAC to scale the comparison photodiode >>>>> current until it is equal to the signal photodiode current. >>>>> Getting enough resolution for good cancellation, and over a >>>>> wide bandwidth sounds very hard though. Also it would only >>>>> ever work for cases where the ratio of the photocurrents is >>>>> pretty constant over a measurement run. >>>> >>>> It's generally pretty well that way. >>> >>> Most of the ideas that I have come up with involve a fast PNP >>> somewhere. I wonder how good a 0.13um PMOS is, and if there is a >>> way to use it that does not rely on decent "Early voltage" (or >>> the fet equivalent), nor care about 1/f noise. >>> >>> >> >> Sorry for the obscurity. I posted the relevant part of the >> circuit at >> <https://electrooptical.net/static/oldsite/www/sed/cloud9detail.png>. >> >>
(The name is a parody of New Focus's 'Nirvana', which I never did
>> like.) >> >> There aren't any ref des yet--I assign them while I'm doing the >> BOM, which helps prevent missing or duplicated designators. >> >> The VFG ('floating ground') and VFN('floating negative') come from >> the TCA0372. >> >> The bias current that needs cancelling is tagged ITAIL and is >> around 1 mA. >> >> The flags DUMPM, VC1, VC2, VB1, VB2, VDISS, and VE are for the R_E >> and power dissipation compensation facilities. > > Thanks, that helped a lot. > > In the worst case, what current does each TIA need to deal with?
About 5 mA. Above there the photodiodes' epi resistance starts to be the limiting factor in cancellation--at high enough current density it goes nonlinear, even with large reverse bias.
> What bandwidth do you get from the LM6171 stage with the 10k > resistors? I wonder whether you'd be able to use an AD8130 instead, > and get rid of the 0.025% resistors. (The TIAs would need lower > resistor values to keep the signal small enough I guess.)
The main issue is the >10V reverse bias on the PDs--the 6171 does the level shift as well as the subtraction. I suppose I could float an AD8130 as well, and then just level-shift its output somehow. That might reduce the effect of phase shifts on the individual TIA signals, but would need something like a 6171 anyway. The resistors are actually a quad pack: RES QUAD 10K 0.1% 25PPM THIN 15ppm match TC 0612 ACASA1002S1002P100 Vishay $0.23705 @ qty 1000 The principal error will be an offset due to VFG not cancelling perfectly, so there's an offset control for that. The LM6171's typical CMR is a surprisingly good 110 dB, which is pretty amazing considering its grossly asymmetrical input structure. (It's a CFA with a buffer stage driving the inverting input.)
> If the AD8130 had low enough input current and current noise, > perhaps you could just put the two high bandwidth custom DPOTs as > plain resistive loads fed from the collectors of the BFP640s, instead > of putting them into TIAs.
Interesting idea. They'd need to be pretty low-Z for that to work though.
> That would save two opamps but would throw away the nice possibility > of correcting the dpot resistor tempco that I mentioned last time.
If we could pin out a matched resistor separately, I could have the micro measure it and dork the cancellation to match, or just use it as part of the downstream voltage divider.
> I'd better go and sleep but I'll have another think when I get a > chance.
Thanks, Chris--this is great fun. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On 2020-07-26 20:44, jlarkin@highlandsniptechnology.com wrote:
> On Sun, 26 Jul 2020 20:14:38 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 2020-07-26 20:03, jlarkin@highlandsniptechnology.com wrote: >>> On Sun, 26 Jul 2020 17:50:10 -0400, Phil Hobbs >>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>> >>>> On 2020-07-26 17:34, bloggs.fredbloggs.fred@gmail.com wrote: >>>>> On Wednesday, July 22, 2020 at 6:43:57 PM UTC-4, Phil Hobbs wrote: >>>>>> So I'm doing a simplified version of the differential laser noise >>>>>> canceller, which in the spherical cow universe looks like it does very >>>>>> well out to about 10 MHz, thanks to the amazing properties of BFP640s >>>>>> and some new photodiodes with reduced series resistance. (At least >>>>>> according to Hamamatsu.) >>>>>> >>>>>> One thing I need for this is an adjustable resistance with good >>>>>> bandwidth. The fastest dpot I can find is the AD5273BRJZ1 (1k, 64 >>>>>> steps, ~6 MHz bandwidth at half scale). >>>>>> >>>>>> The resolution is too coarse for my application, but as it's pretty well >>>>>> set-and-forget, I don't mind some algorithmic complexity. >>>>>> >>>>>> Turns out that if you make a sort of Darlington connection, with one >>>>>> dpot connected as a rheostat in series with the wiper of the other >>>>>> (which is connected to one end), you can get the approximate resolution >>>>>> of a 10-11 bit dpot. >>>>>> >>>>>> 1k >>>>>> 0-*----R1R1R1---------------0 >>>>>> | A >>>>>> | *-------*-----* >>>>>> | | | >>>>>> | V | 5k >>>>>> *------------R2R2R2--* >>>>>> >>>>>> It works best if R2 is about 5 times R1, but the bandwidth may be better >>>>>> if I stick with the 1k version. >>>>>> >>>>>> Neglecting switch resistance, calculating the total resistance as a >>>>>> function of the codes, sorting into a single 1-D array to get a >>>>>> monotonically increasing resistance function, and taking the first >>>>>> finite difference reveals a step size nearly always less than 0.1% >>>>>> except near the low-resistance end, which I don't care much about. >>>>>> >>>>>> There's a plot at >>>>>> <https://electrooptical.net/static/oldsite/www/sed/FightingDPOTs.png> >>>>>> >>>>>> Fun. >>>> >>>>> This kind of thing has been around forever. Fig 6 shows a 6-bit to 12-bit enhancement. >>>>> >>>>> https://www.analog.com/media/en/technical-documentation/application-notes/AN-582.pdf?doc=an-1291.pdf >>>> >>>> Sure, there are lots of approaches. The one I described is new to me, >>>> and isn't in the app note you cite. Its main disadvantage is that >>>> finding the right setting is relatively complicated, but on the plus >>>> side it gets you almost 2N bits' resolution and is essentially immune to >>>> moderate DNL in the dpots. >>>> >>>> The combination of settability and bandwidth exceeds anything available >>>> in a single device. That's pretty important to me, because the >>>> besetting sin of dpots and MDACs is that they're dog slow. >> >>> >>> Use a multiplier! >> >> The problem with multipliers is that they're ~40 dB noisier as well as >> 20dB more expensive, and their accuracy is only ~1% or thereabouts. >> Maybe if I knew more about them I could work around that. I'll look at >> the AD offerings again though. >> >>> I think there are a few fast MDACs too. >> >> I'd be super interested in finding them. 6 MHz @ -3dB is the champ >> AFAIK. Eight or nine bits would be good enough, with a bit of fixing up. > > The AD5426 series is 10 MHz. Sort of. I recall some faster ones > somewhere maybe.
Thanks, I'll check it out.
> > >> >>> You could have fun combining a few digitally controlled RF attenuator >>> chips. >> >> I can probably do better using metal film resistors and TMUX1511 quad >> SPSTs. I have a couple of VCA products that do that, but at higher >> resolution it's not that easy to do. > > If you don't need gain monotonicity, you could do cheap things with > analog switches and resistors.
Yeah, that's the TMUX thing. Our 75-MHz low noise VCA product combines a normal powers-of-2 PGA with a 4-bit attenuator that's built like an R-2R network (i.e. a ladder with switches in the shunt branches) except that its gain varies from 1 to 9/16. By picking the resistors properly you can do a good job, though the combination isn't necessarily monotonic at the ends of the range, so it needs calibrating. (The VCA is mainly intended for use with MPPCs to replace PMT modules.) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On 28/07/2020 02:59, Phil Hobbs wrote:
> On 2020-07-27 10:54, Chris Jones wrote: >> On 27/07/2020 01:11, Phil Hobbs wrote: >>> On 2020-07-26 09:53, Chris Jones wrote: >>>> On 26/07/2020 04:10, Phil Hobbs wrote: >>>>> On 2020-07-25 11:40, Chris Jones wrote: >>>>>> On 25/07/2020 04:38, Phil Hobbs wrote: >>>>>>> On 2020-07-24 10:22, Chris Jones wrote: >>>>>>>> On 24/07/2020 23:10, Phil Hobbs wrote: >>>>>>>>> On 2020-07-24 07:43, Chris Jones wrote: >>>>>>>>>> On 24/07/2020 16:32, Phil Hobbs wrote: >>>>>>>>>>> On 2020-07-23 22:16, Chris Jones wrote: >>>>>>>>>>>> On 24/07/2020 09:14, Phil Hobbs wrote: >>>>>>>>>>>>> On 2020-07-23 16:25, Ricketty C wrote: >>>>>>>>>>>>>> On Thursday, July 23, 2020 at 7:39:36 AM UTC-4, >>>>>>>>>>>>>> pcdh...@gmail.com wrote: >>>>>>>>>>>>>>>> I guess I'm not following what this gains?&Acirc;&nbsp; You get lots >>>>>>>>>>>>>>>> more steps, but >>>>>>>>>>>>>>>> >you don't know any more about where they >>>>>>>>>>>>>>>> are. What am I missing? >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> What it gets me is a combination of settability and >>>>>>>>>>>>>>> bandwidth that I can't get in any single part at any >>>>>>>>>>>>>>> price. I'll dump in a bit of pseudorandom DNL and see if >>>>>>>>>>>>>>> that causes any issues. I don't expect it to--it'll get >>>>>>>>>>>>>>> homogenized much like the regular steps. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> For an iterative adjustment (think LC filter tuning) I >>>>>>>>>>>>>>> can get close by setting the fine pot to 0, adjusting the >>>>>>>>>>>>>>> coarse pot, then walking the two together to find the >>>>>>>>>>>>>>> optimum. Near full scale the possible search range is >>>>>>>>>>>>>>> wider, but I don't think it'll take too long provided >>>>>>>>>>>>>>> that I'm willing to settle for "good enough" rather than >>>>>>>>>>>>>>> a global optimum. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> There are two mildly-interacting adjustments, but the >>>>>>>>>>>>>>> response surface is simple--no local minima. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> It's for taking out the effect of >>>>>>>>>>>>>>> extrinsic emitter resistance in the BJT >>>>>>>>>>>>>>> diff pair that's the heart of the circuit. >>>>>>>>>>>>>>> It works by applying a signal to one of the >>>>>>>>>>>>>>> bases that cancels out the effective >>>>>>>>>>>>>>> emitter degeneration and so restores the >>>>>>>>>>>>>>> desired Ebers-Moll behaviour at higher photocurrents. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> If I feel like getting fancy, once I've found the right >>>>>>>>>>>>>>> neighbourhood I can give the turd a final polish to get a >>>>>>>>>>>>>>> bit closer. ;) >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> There are non-negligible effects such as the tempco of >>>>>>>>>>>>>>> wiper resistance that limit how good this approach can >>>>>>>>>>>>>>> be. Sure beats >>>>>>>>>>>>>>> a trimpot on a motor though! >>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> Ok, so this circuit is not a real time control loop as >>>>>>>>>>>>>> much as it is like a successive approximation. You don't >>>>>>>>>>>>>> mind the value varying unpredictably as long as it >>>>>>>>>>>>>> eventually reaches a setting. >>>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> Right.&Acirc;&nbsp; It'll be done only occasionally, since R_E of a BJT >>>>>>>>>>>>> is a weak function of everything. In a diff pair, R_E >>>>>>>>>>>>> produces degeneration, which tends to make the current >>>>>>>>>>>>> split by the ratios of the R_E values, whereas we want it >>>>>>>>>>>>> to do the Ebers-Moll thing and split strictly >>>>>>>>>>>>> as exp(delta V_BE/kT):1.&Acirc;&nbsp; R_E degeneration generally >>>>>>>>>>>>> dominates the error budget at higher >>>>>>>>>>>>> &Acirc;&nbsp;photocurrents. >>>>>>>>>>>>> >>>>>>>>>>>>> If transistors Q1 and Q2 have resistances R_E1 and R_E2, >>>>>>>>>>>>> then the required voltage is >>>>>>>>>>>>> >>>>>>>>>>>>> dV_BEcor = I_E2 * R_E2&Acirc;&nbsp; - I_E1 * R_E1. >>>>>>>>>>>>> >>>>>>>>>>>>> Since V_B1 is controlled by a feedback loop trying to make >>>>>>>>>>>>> the total DC current from two >>>>>>>>>>>>> or more photodiodes cancel out, the correction voltage gets >>>>>>>>>>>>> applied to the base of Q2. Since the resistances are nearly >>>>>>>>>>>>> constant, rapid adjustment of the correction law is not >>>>>>>>>>>>> required. >>>>>>>>>>>>> >>>>>>>>>>>>> However, the unwanted degeneration applies at AC as well as >>>>>>>>>>>>> DC, and the attainable benefit >>>>>>>>>>>>> is limited by phase shift and amplitude error >>>>>>>>>>>>> in the correction voltage.&Acirc;&nbsp; Thus I do need to >>>>>>>>>>>>> form the correction in analogue with as high a bandwidth as >>>>>>>>>>>>> reasonably possible. >>>>>>>>>>>>> >>>>>>>>>>>>> There'll be a cal table in flash, which will probably rely >>>>>>>>>>>>> on the AD5273's decent DNL to interpolate relatively >>>>>>>>>>>>> coarsely between steps--aiming for, say, 8-bit accuracy. >>>>>>>>>>>>> That's potentially enough to reduce the degeneration effect >>>>>>>>>>>>> by 50 dB in the spherical cow universe. >>>>>>>>>>>>> >>>>>>>>>>>>> Then there'll be a magic pushbutton on the box so that >>>>>>>>>>>>> users in lab settings can tell it that their experiment is >>>>>>>>>>>>> all set up, so please optimize the noise cancellation for >>>>>>>>>>>>> these >>>>>>>>>>>>> exact conditions.&Acirc;&nbsp; Nobody will mind if that >>>>>>>>>>>>> takes 5 seconds or so.&Acirc;&nbsp; (The command will be >>>>>>>>>>>>> available electronically as well--USB serial or >>>>>>>>>>>>> maybe a dedicated control line.) >>>>>>>>>>>>> >>>>>>>>>>>>> The magic BFP640, with its ~1-kV Early voltage, >>>>>>>>>>>>> excellent saturation behaviour, and ultralow >>>>>>>>>>>>> C_CB, allows all sorts of cute tricks. I'm >>>>>>>>>>>>> dorking V_CE on one side of the diff pair in >>>>>>>>>>>>> real time to force the power dissipation of Q1 >>>>>>>>>>>>> and Q2 to be equal irrespective of the splitting ratio >>>>>>>>>>>>> (within limits). >>>>>>>>>>>>> >>>>>>>>>>>>> With some routed slots to control local temperature >>>>>>>>>>>>> gradients, it looks like I can get performance equivalent >>>>>>>>>>>>> to a 40-GHz monolithic dual. (We'll see how spherical the >>>>>>>>>>>>> cows are in real life--I've seen some pretty fat ones.) ;) >>>>>>>>>>>>> >>>>>>>>>>>>> Fun. >>>>>>>>>>>>> >>>>>>>>>>>>> Cheers >>>>>>>>>>>>> >>>>>>>>>>>>> Phil Hobbs >>>>>>>>>>>>> >>>>>>>>>>>>> (Who's stocking up on BFP640s as he did on BF862s) >>>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> By the way, I don't know if you've seen this, >>>>>>>>>>>> but google and skywater fab are open-sourcing the >>>>>>>>>>>> PDK for a 0.13um CMOS process, and google is >>>>>>>>>>>> paying for some free shuttle runs, subject to >>>>>>>>>>>> certain rules including that all designs be >>>>>>>>>>>> open-sourced too. >>>>>>>>>>>> >>>>>>>>>>>> If you can think of anything that you really >>>>>>>>>>>> wish you could get on a chip, and that can be >>>>>>>>>>>> made in CMOS, and that is useful to you but not >>>>>>>>>>>> secret enough to not want to publish the design, >>>>>>>>>>>> now is the time! Shuttle run in November and you >>>>>>>>>>>> get hundreds of parts back, so maybe enough for >>>>>>>>>>>> a low-volume product. Lots of people are playing with the >>>>>>>>>>>> tools so quite likely someone else would >>>>>>>>>>>> lay it out for fun if you didn't have time. >>>>>>>>>>>> >>>>>>>>>>>> There is a link to the slack workspace here, >>>>>>>>>>>> with many more details: >>>>>>>>>>>> >>>>>>>>>>>> https://groups.google.com/forum/#!topic/skywater-pdk-announce/zijPNEsqsx4 >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> Sounds like a good opportunity for sure.&Acirc;&nbsp; If somebody would >>>>>>>>>>> do that with a decent low-noise analogue bipolar process (say >>>>>>>>>>> 0.5 um) I'd be all over it. >>>>>>>>>>> >>>>>>>>>>> Cheers >>>>>>>>>>> >>>>>>>>>>> Phil Hobbs >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> I'd welcome ideas anyway. Even if there is only a small chance >>>>>>>>>> of it working in CMOS, it might be >>>>>>>>>> worth trying, maybe even just on the corner of >>>>>>>>>> someone else's chip. >>>>>>>>>> >>>>>>>>>> I'm mostly interested in trying something that takes little >>>>>>>>>> effort but that could not be replicated >>>>>>>>>> easily using off-the-shelf parts. Maybe a trigger >>>>>>>>>> comparator + adjustable delay + sampler with several >>>>>>>>>> channels, for a sampling scope frontend. Even just a >>>>>>>>>> beefy inverter in 0.13um might make a nice fast edge generator >>>>>>>>>> for testing scope risetime, especially as it'll be a flipchip >>>>>>>>>> chipscale package thing so no bondwires. If there is a usable >>>>>>>>>> bipolar then I might do a bandgap reference / LDO and see what >>>>>>>>>> noise performance I can get from burning a few mA rather than >>>>>>>>>> the few uA that they usually allow themselves. >>>>>>>>>> I quite likely won't have time though. >>>>>>>>>> >>>>>>>>> >>>>>>>>> Well, a high-bandwidth dpot/attenuator comes to mind. Something >>>>>>>>> around 1-2k and 8 bits, maybe an R-2R thing. If the switches >>>>>>>>> were as good as the TMUX1511's, it could be pretty swoopy. >>>>>>>> >>>>>>>> The best bandwidth would come from using 0.13um >>>>>>>> (behaving more like 0.18um I hear) NMOS-only switches but >>>>>>>> they are nominally 1.8V devices so might not be useful >>>>>>>> for some of your purposes (and driving the gates would >>>>>>>> get tricky if you need to use much of that range). How >>>>>>>> much swing will your DPOT see, and do you really want a >>>>>>>> true pot or just a variable resisor (rheostat)? What is >>>>>>>> the DC bias on it? >>>>>>> >>>>>>> I'd be willing to be very flexible in exchange for, say, 100 MHz >>>>>>> BW. The present application needs to put about >>>>>>> +-20 mV across an ohm or two or five, to compensate the >>>>>>> R_E degeneration in the diff pair of a laser noise >>>>>>> canceller. (Less is better since the BFP640 has only about >>>>>>> 3 ohms R_B, and it's a shame to waste that sort of noise >>>>>>> performance.) >>>>>>> >>>>>>>> >>>>>>>> If you wanted a variable resistor with one side grounded then >>>>>>>> the NMOS might work very well. If you could show me where it >>>>>>>> will be used, I might have other ideas that are more optimal >>>>>>>> than a general purpose DPOT. I'm pretty >>>>>>>> sure I won't come up with a general purpose DPOT better >>>>>>>> than the two remaining semiconductor companies can do, >>>>>>>> but I might be able to think of something that solves >>>>>>>> your circuit problem better. >>>>>>> >>>>>>> The circuit is basically Figure 3 in >>>>>>> <https://electrooptical.net/static/media/uploads/Projects/LaserNoiseCanceller/noisecan.pdf> >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> with the modifications of Figures 12 (R_E cancellation) >>>>>>> and 19 (differential/high power version that reduces the current >>>>>>> in the diff pair).&Acirc;&nbsp; (There's also some mildly complicated >>>>>>> bootstrapping and cascoding going on, because >>>>>>> I can't get fast PNPs anymore, but that's for another thread.) >>>>>>> >>>>>>> Sticking with Figure 3, overall feedback forces the >>>>>>> current through D1 to be the same as the collector current >>>>>>> of Q2. (In principle, this is true at all frequencies >>>>>>> regardless of the loop bandwidth--that's why the circuit >>>>>>> works.)&Acirc;&nbsp; In Figure 12, the correction voltage comes >>>>>>> directly from Q1's collector current and a mirrored version >>>>>>> of the tail current of the pair, scaled by a couple of >>>>>>> low-value trimpots.&Acirc;&nbsp; That's pretty simple and works pretty >>>>>>> well, as long as the user is a circuits guy with some vague >>>>>>> clue as to how it all works. >>>>>>> >>>>>>> In the current circuit, I'm forcing the dissipation of Q1 to >>>>>>> equal that of Q2 dorking its V_CE with a DAC >>>>>>> controlling another BFP640 cascode transistor.&Acirc;&nbsp; That's >>>>>>> where the effectively-infinite Early voltage comes in >>>>>>> handy.&Acirc;&nbsp; With a C-shaped cutout in the board and a nice >>>>>>> symmetric layout, that ought to keep the transistors within >>>>>>> 0.1 C of each other. If so, that will basically eliminate >>>>>>> temperature differences as a limiting factor, just as if I >>>>>>> had a 40-GHz monolithic dual NPN. >>>>>>> >>>>>>> Since I need to control VC(Q1), I can't just dump IC(Q1) into the >>>>>>> compensation network.&Acirc;&nbsp; (I also can't get an electronically >>>>>>> controllable equivalent to a 10-ohm trimpot.)&Acirc;&nbsp; Anyway, D1 needs >>>>>>> some reverse bias. >>>>>>> >>>>>>> Soooo, instead I'm using floating ADA4817 TIAs: one in the >>>>>>> &Acirc;&nbsp;collector of the cascode to measure IC(Q1)) and one in >>>>>>> the cathode of D1 to measure IC(Q2).&Acirc;&nbsp; I'm forming the correction >>>>>>> term by a 499-ohm resistor in one TIA and one >>>>>>> of these compound dpot gizmos in the other.&Acirc;&nbsp; An LM6171 and four >>>>>>> 0.025% resistors are doing the diff amp honours to do the >>>>>>> subtraction and shift the difference signal to near ground.&Acirc;&nbsp; (If >>>>>>> I could get a 100-MHz instrumentation amp >>>>>>> that handled 30-V supplies, I'd use that instead.) >>>>>>> >>>>>>> After the diff amp, there's a 499/100 ohm voltage divider, >>>>>>> followed by another of these dpot gizmos running off >>>>>>> +-2.5V to divide that voltage down to the +-20 mV level. >>>>>>> The divider protects the dpots from overvoltage, >>>>>> So far so good, I think I understand up to here... >>>>>> >>>>>>> and besides there's a bias current in D1's bootstrap circuit that >>>>>>> I need to cancel out--the current goes into the 499-ohm TIA so I >>>>>>> need a 499 ohm load to cancel it.) >>>>>> Ok now I am confused about this bit. >>>>> >>>>> The bootstraps/cascodes are Darlington-connected BFP640s, each with >>>>> a 5-ohm bead in series with the base.&Acirc;&nbsp; The beads turn >>>>> them from twitchy magic Ferraris into boring magic Hondas--they >>>>> keep their 500 beta, 1 kV Early voltage, 0.3 nV 1-Hz flatband >>>>> noise, and 0.6 ohm R_E, but become nice and stable although >>>>> probably 20x slower.&Acirc;&nbsp; However, the combo's rolloff is roughly >>>>> quadratic rather than linear below about 500 MHz, so from DC to >>>>> VHF they're nearly indistinguishable from the untouched magic >>>>> microwave transistor. >>>>> >>>>> In the present application, I'm aiming for accuracies of >>>>> around 1 part in 10**4 over a 100:1 range of photocurrent, 50 >>>>> uA to 5 mA.&Acirc;&nbsp; (The complete instrument won't be quite that >>>>> good--this is the budget per photodiode.)&Acirc;&nbsp; So the bootstraps >>>>> and cascodes are Darlingtons with additional external bias for >>>>> the driver transistor to keep the bandwidth from going into the >>>>> tank at low photocurrent.(*)&Acirc;&nbsp; For a normal photodiode >>>>> bootstrap, where we measure the end that goes to the TIA and >>>>> jiggle the end that goes to the bias supply, there's no >>>>> issue--we don't care about mixing the photocurrent and bias >>>>> current on that end of the device. >>>>> >>>>> However, since there are no fast PNPs available anymore, we have to >>>>> bootstrap D1 with NPNs cascode-style: measure the >>>>> anode and jiggle the cathode.&Acirc;&nbsp; That means that we have to get >>>>> our photocurrent measurement from the collectors of the >>>>> Darlington. Since both collectors connect to the TIA input, the >>>>> external bias current for the driver transistor corrupts the >>>>> TIA's output. >>>>> >>>>> That bias comes via a 10k resistor connected someplace near ground, >>>>> so since I chose that TIA to be the one with the fixed 499-ohm >>>>> resistor, the output is in error by about 499 ohms * Vbias/10k >>>>> ohms. Conveniently, that TIA connects to the - input of the diff >>>>> amp, so the bias current makes the diff amp's output go too low. >>>>> >>>>> Thus by hanging a 499 ohm resistor in series with the diff amp >>>>> output, I can null out the offset by simply connecting the other >>>>> end of the 10k resistor to the far&Acirc;&nbsp; end of the 499 ohms. As the >>>>> diff amp output changes, the bias current will change a little, but >>>>> Kirchhoff says it'll stay nulled.&Acirc;&nbsp; ;) This is true regardless of >>>>> the 499 / 100 ohm divider--it works at any ratio. >>>>> >>>>>>> A rheostat with one end near ground but not actually connected >>>>>>> there would do fine in both places >>>>>> In the place where the 20 Ohm pot is shown in the circuit of fig. >>>>>> 12 I guess one end really would be grounded, unless I misunderstand. >>>>>> >>>>>> In the other DPOT location, I understand this to be the feedback >>>>>> resistor of the TIA that senses the current in Q1. >>>>>> I it seems to me that this one is biased up at whatever >>>>>> voltage you need for achieving the right amount of heating in >>>>>> Q1, so it would not be possible for the second DPOT to reside >>>>>> on the same die as the first DPOT that feeds the base of Q1, >>>>>> which is sad. >>>>> >>>>> Yeah, their supplies are offset by like 18V from each other, but >>>>> I'm totally happy using two chips.&Acirc;&nbsp; If I wind up wiring >>>>> VSS of the dpot to the TIA input it'd have to be a single >>>>> anyway. >>>>> >>>>>> So, maybe there isn't a dpot on the base of Q1 but a fixed >>>>>> resistive divider, and do the scaling elsewhere... >>>>>> >>>>>> Do both floating ADA4817 TIAs opamps share the same voltage on >>>>>> their non-inverting inputs? >>>>> >>>>> Yes. They're both connected to a 'floating ground' hung 5V below >>>>> the main VCC rail.&Acirc;&nbsp; Their VEE pins are a couple of volts below >>>>> that.&Acirc;&nbsp; Both rails courtesy of that TCA0372 I was whining about on >>>>> another thread. ;) >>>>> >>>>>> Otherwise I don't understand how the LM6171 and four 0.025% >>>>>> resistor diff amp would manage the subtraction without further >>>>>> complication. If the TIAs are biased up at the same voltage, then >>>>>> I guess both TIAs could use the new wideband DPOTs/rheostats and >>>>>> could float up there together on the >>>>>> same die. >>>>> >>>>> I think that would probably work fine, as long as the bottom end of >>>>> the rheostats were separate rather than connecting directly to VSS. >>>>> >>>>> Since the input transistor of the D1 Darlington is above the >>>>> floating ground and the voltage drop doesn't vary rapidly, I could >>>>> probably get rid of the bias current effect adequately using >>>>> another dpot and software to distribute it between the two TIAs >>>>> correctly. >>>>> >>>>>> So the gains of both TIAs would be adjusted separately and the the >>>>>> results of that would get subtracted and shifted >>>>>> down by the diff amp and scaled by a fixed resistive divider >>>>>> to feed the base of Q1. I am guessing that in this case you would >>>>>> want a ~500 Ohm value rheostat for each TIA, but might have to go >>>>>> for a lower value in order to limit the voltage >>>>>> at the end of the rheostat. >>>>> I'm totally happy bootstrapping the supplies in any way necessary, >>>>> so as long as the cold ends of the rheostats aren't both grounded, >>>>> we're good. >>>>> >>>>>> >>>>>>> and I could live with 2V supplies if I had to.&Acirc;&nbsp; If I >>>>>>> really had to, I could run the dpot's ground pin into the >>>>>>> TIA and fix up the quiescent current afterwards. >>>>>> Do you mean the wiper, or the VSS? VSS of the dpot thing could be >>>>>> driven by whatever sets the non-inverting input of the TIA opamps, >>>>>> I think. >>>>>> >>>>>> One part I don't understand is the correction of bootstrap bias >>>>>> current that you mentioned. If only usenet had a whiteboard. >>>>> >>>>> I hope I've explained it adequately.&Acirc;&nbsp; I'll happily post a schematic >>>>> fragment if needed. >>>> I'm afraid I am still very confused, after trying quite hard to >>>> interpret your explanation in the context of Fig. 3 from your link. >>>> I appreciate that you have put a lot of work into the explanation, >>>> and I was going to point out each part that I >>>> didn't understand, but I think re-explaining all of that in text >>>> would perhaps not be an efficient use of your time. >>>> >>>> I think part of it is that avoiding the PNP probably makes the >>>> circuit fairly different from Fig. 3, and part of it is that I >>>> am imagining that there are three TIAs (the main one for the >>>> subtracted photocurrents that produces the final output, and one for >>>> monitoring the collector current of each transistor in the diff pair >>>> that does the current splitting), but it is not always clear to me >>>> in each case which TIA you are referring to above. >>>> >>>> If you could post a schematic, that would be very efficient, however >>>> I would understand if you prefer not to do that unless privately >>>> under formal or informal NDA, in which case I've sent you an e-mail >>>> by which we could arrange that if necessary. >>>> >>>> Curiousity aside, for implementing a fast DPOT the main thing I >>>> think I am missing is an understanding of how the bias current (of >>>> the Darlington) gets subtracted out, and how the diffamp is >>>> connected. Given that the tempco of the dpot resistors (and initial >>>> tolerance) is likely to be truly awful, there might be >>>> an advantage in implementing the two input resistors of the >>>> diffamp on-chip using the exact same awful tempco as the DPOT, to >>>> take out the gain drift. It may not matter that the voltage on >>>> one end of those unswitched resistors goes well outside the >>>> rails, as long as I am allowed to get creative with the ESD >>>> protection cells. >>>> >>>>> >>>>>> Also this whole circuit would be great in a fast complementary >>>>>> bipolar process like XFCB3. Oh well. >>>>>> >>>>>> Stuck with CMOS, it is tempting to also try some sort of >>>>>> multiplying current DAC to scale the comparison photodiode current >>>>>> until it is equal to the signal photodiode current. Getting enough >>>>>> resolution for good cancellation, and over a wide bandwidth sounds >>>>>> very hard though. Also it would only ever work for cases where the >>>>>> ratio of the photocurrents is pretty constant over a measurement run. >>>>> >>>>> It's generally pretty well that way. >>>> >>>> Most of the ideas that I have come up with involve a fast PNP >>>> somewhere. I wonder how good a 0.13um PMOS is, and if there is a way >>>> to use it that does not rely on decent "Early voltage" (or the fet >>>> equivalent), nor care about 1/f noise. >>>> >>>> >>> >>> Sorry for the obscurity.&Acirc;&nbsp; I posted the relevant part of the >>> circuit at >>> <https://electrooptical.net/static/oldsite/www/sed/cloud9detail.png>. >>> >>> > (The name is a parody of New Focus's 'Nirvana', which I never did >>> like.) >>> >>> There aren't any ref des yet--I assign them while I'm doing the BOM, >>> which helps prevent missing or duplicated designators. >>> >>> The VFG ('floating ground') and VFN('floating negative') come from >>> the TCA0372. >>> >>> The bias current that needs cancelling is tagged ITAIL and is around >>> 1 mA. >>> >>> The flags DUMPM, VC1, VC2, VB1, VB2, VDISS, and VE are for the R_E >>> and power dissipation compensation facilities. >> >> Thanks, that helped a lot. >> >> In the worst case, what current does each TIA need to deal with? > > About 5 mA.&Acirc;&nbsp; Above there the photodiodes' epi resistance starts to be > the limiting factor in cancellation--at high enough current density it > goes nonlinear, even with large reverse bias. > >> What bandwidth do you get from the LM6171 stage with the 10k >> resistors? I wonder whether you'd be able to use an AD8130 instead, >> and get rid of the 0.025% resistors. (The TIAs would need lower >> resistor values to keep the signal small enough I guess.) > > The main issue is the >10V reverse bias on the PDs--the 6171 does the > level shift as well as the subtraction.&Acirc;&nbsp; I suppose I could float an > AD8130 as well, and then just level-shift its output somehow.&Acirc;&nbsp; That > might reduce the effect of phase shifts on the individual TIA signals, > but would need something like a 6171 anyway.
No, the AD8130 can do the subtraction and level shifting without any matched resistors nor floating supplies, provided the inputs remain well within the rails, which should be feasible if you use the same supply rails that you were using with the LM6171. I got confused there and said AD8130 when I meant AD830, but the AD8130 seems better anyway. The AD8130 has lower maximum supply voltage and maximum input voltage than the AD830 but better bias current and bandwidth. Both of them run pretty hot. I was just dubious that you'd be able to take full advantage of a new dpot that is good to 100MHz using the diff amp with 10k resistors in it. (I have a lot of scrap boards with AD830s on them, and due to an urgent requirement I used one to make a differental scope probe. It is not great but still very handy, but now I think I should make another with the AD8130. The biggest nuisance is powering it so maybe I need to make a quiet 5V to +/-12V converter that plugs into the scope's USB port.)
> The resistors are actually a quad pack: > > RES QUAD 10K 0.1% 25PPM THIN 15ppm match TC&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp; 0612 > ACASA1002S1002P100&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp; Vishay&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp;&Acirc;&nbsp; $0.23705 @ qty 1000
Thanks, nice part!
> The principal error will be an offset due to VFG not cancelling > perfectly, so there's an offset control for that.&Acirc;&nbsp; The LM6171's typical > CMR is a surprisingly good 110 dB, which is pretty amazing considering > its grossly asymmetrical input structure.&Acirc;&nbsp; (It's a CFA with a buffer > stage driving the inverting input.)
Yes, I was surprised about that too.
>> If the AD8130 had low enough input current and current noise, >> perhaps you could just put the two high bandwidth custom DPOTs as >> plain resistive loads fed from the collectors of the BFP640s, instead >> of putting them into TIAs. > > Interesting idea.&Acirc;&nbsp; They'd need to be pretty low-Z for that to work though.
Yep. The dpot resistance would need to be a bit lower anyway if using 0.13um devices, to keep the swing well below 1.8V.
>> That would save two opamps but would throw away the nice possibility >> of correcting the dpot resistor tempco that I mentioned last time. > > If we could pin out a matched resistor separately, I could have the > micro measure it and dork the cancellation to match, or just use it as > part of the downstream voltage divider.
I think the analog option of using the resistor in the signal path is nicer as I suspect the temperature may vary rapidly due to dissipation.