Forums

tiebreaker

Started by John Larkin June 24, 2020
We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus
memory interface. It doesn't work. The software person suspects an
FPGA bug, and vice versa. I'm going to scope things and see.

And no matter how many test points you design into a board, they are
seldom the right ones.

https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1

-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin:
> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus > memory interface. It doesn't work. The software person suspects an > FPGA bug, and vice versa. I'm going to scope things and see. > > And no matter how many test points you design into a board, they are > seldom the right ones. > > https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >
https://www.xilinx.com/products/intellectual-property/ila.html
On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: >> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus >> memory interface. It doesn't work. The software person suspects an >> FPGA bug, and vice versa. I'm going to scope things and see. >> >> And no matter how many test points you design into a board, they are >> seldom the right ones. >> >> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >> > >https://www.xilinx.com/products/intellectual-property/ila.html
The FPGA is re-programmable, right ? Probably time to add some simple debigging code to be able to view comm signals. A logic analyzer maybe like Lasse mentions or a Seilig (spelling ?) But which one responds to who ? Does the Xylinx not talk unless asked by the ARM processor or maybe the other way around ? Might have to change code to debug that. I/O interrupts on the ARM chip ? Maybe I didn't notice a CLK line between the two. Hard to say without at least a partial schematic. Fun stuff though !
On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: >> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus >> memory interface. It doesn't work. The software person suspects an >> FPGA bug, and vice versa. I'm going to scope things and see. >> >> And no matter how many test points you design into a board, they are >> seldom the right ones. >> >> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >> > >https://www.xilinx.com/products/intellectual-property/ila.html
It's fixed. The fpga lady is too young to know that \WE is always active low. Lotta soldering to make people THINK. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wednesday, 24 June 2020 15:09:00 UTC-4, John Larkin  wrote:
> On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: > >> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus > >> memory interface. It doesn't work. The software person suspects an > >> FPGA bug, and vice versa. I'm going to scope things and see. > >> > >> And no matter how many test points you design into a board, they are > >> seldom the right ones. > >> > >> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 > >> > > > >https://www.xilinx.com/products/intellectual-property/ila.html > > It's fixed. The fpga lady is too young to know that \WE is always > active low. > > Lotta soldering to make people THINK. > > -- > > John Larkin Highland Technology, Inc > picosecond timing precision measurement > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.com
Murphy's Law (?) If anything can be inverted. it will be. Interesting way to have test points... but quick recovery.
On Wed, 24 Jun 2020 12:08:36 -0700, boB <boB@K7IQ.com> wrote:

>On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen ><langwadt@fonz.dk> wrote: > >>onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: >>> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus >>> memory interface. It doesn't work. The software person suspects an >>> FPGA bug, and vice versa. I'm going to scope things and see. >>> >>> And no matter how many test points you design into a board, they are >>> seldom the right ones. >>> >>> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >>> >> >>https://www.xilinx.com/products/intellectual-property/ila.html > > >The FPGA is re-programmable, right ? Probably time to add >some simple debigging code to be able to view comm signals. > >A logic analyzer maybe like Lasse mentions or a Seilig (spelling ?) > >But which one responds to who ? Does the Xylinx not talk unless >asked by the ARM processor or maybe the other way around ? >Might have to change code to debug that. > >I/O interrupts on the ARM chip ? Maybe I didn't notice a CLK line >between the two. Hard to say without at least a partial schematic. >Fun stuff though ! > > >
The ARM runs off its internal clock, and the FPGA uses a 40 MHz crystal oscillator. So the memory transations are async. I think this ARM always treats external memory devices as SRAM. The ARM is now doing 1 us wide memory cycles, and the FPGA runs a state machine to act like an SRAM. 1 us is conservative and fast enough in this application. There is a wait-state handshake mode in the ARM bus controller, but using that would be a nuisance. We ran the \WAIT signal between chips, but I don't want to use it. I just want to be done on a time scale of weeks, not microseconds. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wed, 24 Jun 2020 12:16:46 -0700 (PDT), Anthony Stewart
<tony.sunnysky@gmail.com> wrote:

>On Wednesday, 24 June 2020 15:09:00 UTC-4, John Larkin wrote: >> On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: >> >> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus >> >> memory interface. It doesn't work. The software person suspects an >> >> FPGA bug, and vice versa. I'm going to scope things and see. >> >> >> >> And no matter how many test points you design into a board, they are >> >> seldom the right ones. >> >> >> >> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >> >> >> > >> >https://www.xilinx.com/products/intellectual-property/ila.html >> >> It's fixed. The fpga lady is too young to know that \WE is always >> active low. >> >> Lotta soldering to make people THINK. >> >> -- >> >> John Larkin Highland Technology, Inc >> picosecond timing precision measurement >> >> jlarkin att highlandtechnology dott com >> http://www.highlandtechnology.com > >Murphy's Law (?) If anything can be inverted. it will be. > >Interesting way to have test points... but quick recovery.
I had one engineer who couldn't tell left from right. He also couldn't tell 1 from 0. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wed, 24 Jun 2020 12:38:51 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

>On Wed, 24 Jun 2020 12:16:46 -0700 (PDT), Anthony Stewart ><tony.sunnysky@gmail.com> wrote: > >>On Wednesday, 24 June 2020 15:09:00 UTC-4, John Larkin wrote: >>> On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen >>> <langwadt@fonz.dk> wrote: >>> >>> >onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: >>> >> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus >>> >> memory interface. It doesn't work. The software person suspects an >>> >> FPGA bug, and vice versa. I'm going to scope things and see. >>> >> >>> >> And no matter how many test points you design into a board, they are >>> >> seldom the right ones. >>> >> >>> >> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >>> >> >>> > >>> >https://www.xilinx.com/products/intellectual-property/ila.html >>> >>> It's fixed. The fpga lady is too young to know that \WE is always >>> active low. >>> >>> Lotta soldering to make people THINK. >>> >>> -- >>> >>> John Larkin Highland Technology, Inc >>> picosecond timing precision measurement >>> >>> jlarkin att highlandtechnology dott com >>> http://www.highlandtechnology.com >> >>Murphy's Law (?) If anything can be inverted. it will be. >> >>Interesting way to have test points... but quick recovery. > >I had one engineer who couldn't tell left from right. He also couldn't >tell 1 from 0.
We had one young woman in production years ago that could not read an analog clock. I temporarily would ask would-be job candidates to show me what counter-clockwise direction was to see if they knew what that meant. Most people do know that of course but you can't be too careful these days.
On Wed, 24 Jun 2020 15:44:20 -0700, boB <boB@K7IQ.com> wrote:

>On Wed, 24 Jun 2020 12:38:51 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote: > >>On Wed, 24 Jun 2020 12:16:46 -0700 (PDT), Anthony Stewart >><tony.sunnysky@gmail.com> wrote: >> >>>On Wednesday, 24 June 2020 15:09:00 UTC-4, John Larkin wrote: >>>> On Wed, 24 Jun 2020 11:28:23 -0700 (PDT), Lasse Langwadt Christensen >>>> <langwadt@fonz.dk> wrote: >>>> >>>> >onsdag den 24. juni 2020 kl. 20.08.29 UTC+2 skrev John Larkin: >>>> >> We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus >>>> >> memory interface. It doesn't work. The software person suspects an >>>> >> FPGA bug, and vice versa. I'm going to scope things and see. >>>> >> >>>> >> And no matter how many test points you design into a board, they are >>>> >> seldom the right ones. >>>> >> >>>> >> https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 >>>> >> >>>> > >>>> >https://www.xilinx.com/products/intellectual-property/ila.html >>>> >>>> It's fixed. The fpga lady is too young to know that \WE is always >>>> active low. >>>> >>>> Lotta soldering to make people THINK. >>>> >>>> -- >>>> >>>> John Larkin Highland Technology, Inc >>>> picosecond timing precision measurement >>>> >>>> jlarkin att highlandtechnology dott com >>>> http://www.highlandtechnology.com >>> >>>Murphy's Law (?) If anything can be inverted. it will be. >>> >>>Interesting way to have test points... but quick recovery. >> >>I had one engineer who couldn't tell left from right. He also couldn't >>tell 1 from 0. > > >We had one young woman in production years ago that could not read an >analog clock. > >I temporarily would ask would-be job candidates to show me what >counter-clockwise direction was to see if they knew what that meant. > >Most people do know that of course but you can't be too careful these >days. > >
Google can't read analog clock -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wednesday, June 24, 2020 at 3:44:25 PM UTC-7, boB wrote:
> On Wed, 24 Jun 2020 12:38:51 -0700, John Larkin
> We had one young woman in production years ago that could not read an > analog clock. > > I temporarily would ask would-be job candidates to show me what > counter-clockwise direction was to see if they knew what that meant.
Oh, that's easy; it's the direction sundials indicate, in Australia.