I have a fast 3.3 volt logic level that I'd like to split into inverted and non-inverted copies with minimum time skew. I think that TI once had a buffer with one input and complementary outputs, but I can't find a reference to that. It's probably slow and obsolete. A TTL to RS485 converter sort of works but would be slow. I could use two separate XOR gates, one as a buffer and the other as an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate packages and different logic functions, delay symmetry might be suspect. 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some asymmetry when it inverts vs when it doesn't. Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a buffer. Q and Qbar may be pretty symmetric. -- John Larkin Highland Technology, Inc The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
complementary cmos levels
Started by ●February 16, 2020
Reply by ●February 16, 20202020-02-16
Reply by ●February 16, 20202020-02-16
On Sunday, February 16, 2020 at 1:13:39 PM UTC-8, jla...@highlandsniptechnology.com wrote:> I have a fast 3.3 volt logic level that I'd like to split into > inverted and non-inverted copies with minimum time skew.CMOS parts have different rise and fall times (PMOS half needs more input capacitance to give output conductance than the NMOS half), but a flipflop with the outputs anti-coupled with a small transformer will have matching slew AND impedance, at the highest frequencies of the input waveform. I'm thinking a ferrite bead with two wires. You'd want to load the outputs symmetrically, of course.
Reply by ●February 16, 20202020-02-16
On 17/02/2020 08:13, jlarkin@highlandsniptechnology.com wrote:> > > I have a fast 3.3 volt logic level that I'd like to split into > inverted and non-inverted copies with minimum time skew. > > I think that TI once had a buffer with one input and complementary > outputs, but I can't find a reference to that. It's probably slow and > obsolete. > > A TTL to RS485 converter sort of works but would be slow. > > I could use two separate XOR gates, one as a buffer and the other as > an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate > packages and different logic functions, delay symmetry might be > suspect. > > 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some > asymmetry when it inverts vs when it doesn't. > > Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a > buffer. Q and Qbar may be pretty symmetric.If you had a LVDS or ECL input signal and cared more that the delay from the rising edge at the input to the rising edge at one output is the same as the delay from the falling edge at the input to the rising edge at the other output, then you could use two identical differential to single-ended converters with the input pair of one of them swapped in polarity. It sounds like this isn't what you want though.
Reply by ●February 16, 20202020-02-16
On Sun, 16 Feb 2020 14:09:21 -0800 (PST), plastcontrol.ru@gmail.com wrote:>http://www.ti.com/lit/ds/symlink/sn74lvc1g19.pdfThe data sheet doesn't address delay symmetry. Tpd from (some input) to (some output) is 1 to 4 ns at 3.3 volts. I could use an analog ADC driver diffamp, but that's overkill. Could be done with discretes, ditto. MC10EL89 has real diff outputs, but swings a bit under 2 volts and needs a lot of power and is expensive. I worry about ECL going obsolete too. -- John Larkin Highland Technology, Inc The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●February 17, 20202020-02-17
On 2020-02-16 16:13, jlarkin@highlandsniptechnology.com wrote:> > > I have a fast 3.3 volt logic level that I'd like to split into > inverted and non-inverted copies with minimum time skew. > > I think that TI once had a buffer with one input and complementary > outputs, but I can't find a reference to that. It's probably slow and > obsolete. > > A TTL to RS485 converter sort of works but would be slow. > > I could use two separate XOR gates, one as a buffer and the other as > an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate > packages and different logic functions, delay symmetry might be > suspect. > > 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some > asymmetry when it inverts vs when it doesn't. > > Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a > buffer. Q and Qbar may be pretty symmetric. > > >There are also reasonably quick DIY gates (a modern version of the ancient TTL and-or-invert) such as NC7SZ58P6X. I don't know how symmetrical their delays are, but you have 4 choices of configuration to make an inverter and 4 for a buffer, so you might find two that are close. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●February 17, 20202020-02-17
søndag den 16. februar 2020 kl. 22.13.39 UTC+1 skrev jla...@highlandsniptechnology.com:> I have a fast 3.3 volt logic level that I'd like to split into > inverted and non-inverted copies with minimum time skew. > > I think that TI once had a buffer with one input and complementary > outputs, but I can't find a reference to that. It's probably slow and > obsolete. > > A TTL to RS485 converter sort of works but would be slow. > > I could use two separate XOR gates, one as a buffer and the other as > an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate > packages and different logic functions, delay symmetry might be > suspect. > > 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some > asymmetry when it inverts vs when it doesn't. > > Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a > buffer. Q and Qbar may be pretty symmetric. >two of your favorite LVDS recievers, bias on one input to vcc/2 swap inputs on one of them ?
Reply by ●February 17, 20202020-02-17
On Sunday, February 16, 2020 at 4:13:39 PM UTC-5, jla...@highlandsniptechnology.com wrote:> I have a fast 3.3 volt logic level that I'd like to split into > inverted and non-inverted copies with minimum time skew. > > I think that TI once had a buffer with one input and complementary > outputs, but I can't find a reference to that. It's probably slow and > obsolete. > > A TTL to RS485 converter sort of works but would be slow. > > I could use two separate XOR gates, one as a buffer and the other as > an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate > packages and different logic functions, delay symmetry might be > suspect. > > 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some > asymmetry when it inverts vs when it doesn't.I recently used a 74VHC86 to produce complementary polarities. The data sheet said "balanced propagation delays," but tpd(max) was < my |tpdA-tpdB| target, so I didn't bother actually measuring. "Balanced propagation delays: tpLH ≈ tpHL" https://media.digikey.com/pdf/Data%20Sheets/Toshiba%20PDFs/TC74VHC86F,FN,FT,FK.pdf> > Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a > buffer. Q and Qbar may be pretty symmetric.Cheers, James Arthur
Reply by ●February 17, 20202020-02-17
On Mon, 17 Feb 2020 09:43:09 -0800 (PST), dagmargoodboat@yahoo.com wrote:>On Sunday, February 16, 2020 at 4:13:39 PM UTC-5, jla...@highlandsniptechnology.com wrote: >> I have a fast 3.3 volt logic level that I'd like to split into >> inverted and non-inverted copies with minimum time skew. >> >> I think that TI once had a buffer with one input and complementary >> outputs, but I can't find a reference to that. It's probably slow and >> obsolete. >> >> A TTL to RS485 converter sort of works but would be slow. >> >> I could use two separate XOR gates, one as a buffer and the other as >> an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate >> packages and different logic functions, delay symmetry might be >> suspect. >> >> 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some >> asymmetry when it inverts vs when it doesn't. > >I recently used a 74VHC86 to produce complementary polarities. >The data sheet said "balanced propagation delays," but tpd(max) >was < my |tpdA-tpdB| target, so I didn't bother actually measuring. > >"Balanced propagation delays: tpLH ? tpHL" >https://media.digikey.com/pdf/Data%20Sheets/Toshiba%20PDFs/TC74VHC86F,FN,FT,FK.pdf > >> >> Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a >> buffer. Q and Qbar may be pretty symmetric. > >Cheers, >James ArthurInteresting, but I hate it whan a claim is made on sheet 1 of a data sheet, and then it's not quantified anywhere. The specified prop delay over temperatre is 1.0 to 16.5 ns! -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●February 17, 20202020-02-17
On Mon, 17 Feb 2020 09:02:48 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>s�ndag den 16. februar 2020 kl. 22.13.39 UTC+1 skrev jla...@highlandsniptechnology.com: >> I have a fast 3.3 volt logic level that I'd like to split into >> inverted and non-inverted copies with minimum time skew. >> >> I think that TI once had a buffer with one input and complementary >> outputs, but I can't find a reference to that. It's probably slow and >> obsolete. >> >> A TTL to RS485 converter sort of works but would be slow. >> >> I could use two separate XOR gates, one as a buffer and the other as >> an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate >> packages and different logic functions, delay symmetry might be >> suspect. >> >> 74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some >> asymmetry when it inverts vs when it doesn't. >> >> Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a >> buffer. Q and Qbar may be pretty symmetric. >> > >two of your favorite LVDS recievers, bias on one input to vcc/2 >swap inputs on one of them ? >That would work. DS90LV012A is our default receiver. It actually has rise and fall prop delay specified separately, with a typ difference of 100 ps, max 400. I'm guessing that a pair of Tiny 1ns XORs (off the same reel) would be about that good. In one case, my diff signals come from a 1 ns Tiny D-flop with Q and \Q pins, which is probably about as good as I can do. In another case, I need to split an unclocked single-ended signal into differential to drive another gadget. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
