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200Mbps link between FPGAs

Started by Piotr Wyderski December 27, 2019
Hi,

I need to reliably connect two FPGAs with a 200Mbps link. The chips will 
be separated by the distance of max. 2m, no isolation is required, an 
ethernet FTP cable is available. The link should be bidirectional, but
the communication needs to be fast in just one direction. Having two 
unidirectional links is a viable option. PHY layer simplicity is at a 
premium. I bet that many of you have already solved a similar problem
successfully, so any suggestions will be appreciated.

The answer is "differential", but differential what exactly?

	Best regards, Piotr
On Friday, December 27, 2019 at 9:52:09 PM UTC+11, Piotr Wyderski wrote:
> Hi, > > I need to reliably connect two FPGAs with a 200Mbps link. The chips will > be separated by the distance of max. 2m, no isolation is required, an > ethernet FTP cable is available. The link should be bidirectional, but > the communication needs to be fast in just one direction. Having two > unidirectional links is a viable option. PHY layer simplicity is at a > premium. I bet that many of you have already solved a similar problem > successfully, so any suggestions will be appreciated. > > The answer is "differential", but differential what exactly?
It's been a while since I looked at FPGAs, but back when I was looking the faster ones they offer LVDS signalling. https://en.wikipedia.org/wiki/Low-voltage_differential_signaling "This (2001) standard originally recommended a maximum data rate of 655 Mbit/s over twisted-pair copper wire, but data rates from 1 to 3 Gbit/s are common today on high quality transmission mediums" -- Bill Sloman, Sydney
Bill Sloman wrote:

> It's been a while since I looked at FPGAs, but back when I was looking the faster ones they offer LVDS signalling.
I was convinced that the FPGA LVDS should not leave the PCB, but it turns out that you are right, there are good transceiver chips, like the SN65LVDS051. Some folks seem to be using only the FPGA built-in transceivers, but it is way outside of my comfort zone. Problem solved; thank you, Bill! Best regards, Piotr
On Fri, 27 Dec 2019 11:52:05 +0100, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

>Hi, > >I need to reliably connect two FPGAs with a 200Mbps link. The chips will >be separated by the distance of max. 2m, no isolation is required, an >ethernet FTP cable is available. The link should be bidirectional, but >the communication needs to be fast in just one direction. Having two >unidirectional links is a viable option. PHY layer simplicity is at a >premium. I bet that many of you have already solved a similar problem >successfully, so any suggestions will be appreciated. > >The answer is "differential", but differential what exactly? > > Best regards, Piotr
Straight LVDS should be OK over 2m of CAT5/6 cable. At 200 MBPS, you could do it brute force, clock+data in each direction. To go a little farther and faster, SFP modules + SERDES are great. -- John Larkin Highland Technology, Inc trk jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Saturday, December 28, 2019 at 2:36:03 AM UTC+11, John Larkin wrote:
> On Fri, 27 Dec 2019 11:52:05 +0100, Piotr Wyderski > <peter.pan@neverland.mil> wrote: > > >Hi, > > > >I need to reliably connect two FPGAs with a 200Mbps link. The chips will > >be separated by the distance of max. 2m, no isolation is required, an > >ethernet FTP cable is available. The link should be bidirectional, but > >the communication needs to be fast in just one direction. Having two > >unidirectional links is a viable option. PHY layer simplicity is at a > >premium. I bet that many of you have already solved a similar problem > >successfully, so any suggestions will be appreciated. > > > >The answer is "differential", but differential what exactly? > > Straight LVDS should be OK over 2m of CAT5/6 cable. At 200 MBPS, you > could do it brute force, clock+data in each direction.
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling "The ANSI/TIA/EIA-644-A (published in 2001) standard defines LVDS. This standard originally recommended a maximum data rate of 655 Mbit/s over twisted-pair copper wire, but data rates from 1 to 3 Gbit/s are common today on high quality transmission mediums." LVDS is already an overkill.
> To go a little farther and faster, SFP modules + SERDES are great.
Why waste money on an even more extravagant over-kill? Two metres isn't far, and he doesn't need isolation. -- Bill Sloman, Sydney
On Fri, 27 Dec 2019 12:58:05 +0100, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

>Bill Sloman wrote: > >> It's been a while since I looked at FPGAs, but back when I was looking the faster ones they offer LVDS signalling. > >I was convinced that the FPGA LVDS should not leave the PCB, but it >turns out that you are right, there are good transceiver chips, like the >SN65LVDS051. Some folks seem to be using only the FPGA built-in >transceivers, but it is way outside of my comfort zone. > >Problem solved; thank you, Bill! > > Best regards, Piotr
I'd go LVDS directly between FPGAs, but if you want an LVDS-LVDS buffer, FIN1101 is fast (about 1 ns) and cheap. -- John Larkin Highland Technology, Inc trk jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Fri, 27 Dec 2019 19:01:04 -0800 (PST), Bill Sloman
<bill.sloman@ieee.org> wrote:

>On Saturday, December 28, 2019 at 2:36:03 AM UTC+11, John Larkin wrote: >> On Fri, 27 Dec 2019 11:52:05 +0100, Piotr Wyderski >> <peter.pan@neverland.mil> wrote: >> >> >Hi, >> > >> >I need to reliably connect two FPGAs with a 200Mbps link. The chips will >> >be separated by the distance of max. 2m, no isolation is required, an >> >ethernet FTP cable is available. The link should be bidirectional, but >> >the communication needs to be fast in just one direction. Having two >> >unidirectional links is a viable option. PHY layer simplicity is at a >> >premium. I bet that many of you have already solved a similar problem >> >successfully, so any suggestions will be appreciated. >> > >> >The answer is "differential", but differential what exactly? >> >> Straight LVDS should be OK over 2m of CAT5/6 cable. At 200 MBPS, you >> could do it brute force, clock+data in each direction. > >https://en.wikipedia.org/wiki/Low-voltage_differential_signaling > >"The ANSI/TIA/EIA-644-A (published in 2001) standard defines LVDS. This standard originally recommended a maximum data rate of 655 Mbit/s over twisted-pair copper wire, but data rates from 1 to 3 Gbit/s are common today on high quality transmission mediums." > >LVDS is already an overkill. > >> To go a little farther and faster, SFP modules + SERDES are great. > >Why waste money on an even more extravagant over-kill? > >Two metres isn't far, and he doesn't need isolation.
Unfortunately, the LVDS common mode voltage is quite limited, so the Tx and Rx grounds should be within +/- 1 V from each other. Care is needed when wiring DC power and ground feeds between cards especially if there are some inductive loads fed from the same DC power. The spikes in the ground return could be quite large.
On Friday, December 27, 2019 at 9:18:23 PM UTC-8, upsid...@downunder.com wrote:
> On Fri, 27 Dec 2019 19:01:04 -0800 (PST), Bill Sloman > <bill.sloman@ieee.org> wrote:
> >Two metres isn't far, and he doesn't need isolation. > > Unfortunately, the LVDS common mode voltage is quite limited, so the > Tx and Rx grounds should be within +/- 1 V from each other.
With a self-clocked modulation scheme, Ethernet magnetics (for isolation) should keep up with the requirement. You can get four parallel streams at 125 MHz with long (100M) wires, so a short link can probably handle the 200 Mbps task with two pairs (send and receive). I presume availability of logic modules for modulation, demodulation, and FIFO functions?
On Saturday, December 28, 2019 at 4:18:23 PM UTC+11, upsid...@downunder.com wrote:
> On Fri, 27 Dec 2019 19:01:04 -0800 (PST), Bill Sloman > <bill.sloman@ieee.org> wrote: > > >On Saturday, December 28, 2019 at 2:36:03 AM UTC+11, John Larkin wrote: > >> On Fri, 27 Dec 2019 11:52:05 +0100, Piotr Wyderski > >> <peter.pan@neverland.mil> wrote: > >> > >> >Hi, > >> > > >> >I need to reliably connect two FPGAs with a 200Mbps link. The chips will > >> >be separated by the distance of max. 2m, no isolation is required, an > >> >ethernet FTP cable is available. The link should be bidirectional, but > >> >the communication needs to be fast in just one direction. Having two > >> >unidirectional links is a viable option. PHY layer simplicity is at a > >> >premium. I bet that many of you have already solved a similar problem > >> >successfully, so any suggestions will be appreciated. > >> > > >> >The answer is "differential", but differential what exactly? > >> > >> Straight LVDS should be OK over 2m of CAT5/6 cable. At 200 MBPS, you > >> could do it brute force, clock+data in each direction. > > > >https://en.wikipedia.org/wiki/Low-voltage_differential_signaling > > > >"The ANSI/TIA/EIA-644-A (published in 2001) standard defines LVDS. This standard originally recommended a maximum data rate of 655 Mbit/s over twisted-pair copper wire, but data rates from 1 to 3 Gbit/s are common today on high quality transmission mediums." > > > >LVDS is already an overkill. > > > >> To go a little farther and faster, SFP modules + SERDES are great. > > > >Why waste money on an even more extravagant over-kill? > > > >Two metres isn't far, and he doesn't need isolation. > > Unfortunately, the LVDS common mode voltage is quite limited, so the > Tx and Rx grounds should be within +/- 1 V from each other. > > Care is needed when wiring DC power and ground feeds between cards > especially if there are some inductive loads fed from the same DC > power. The spikes in the ground return could be quite large.
What we did with a Taxichip link - which wasn't quite that fast at 125Mbit/sec - was to use a transmission line transformer to provide isolation (mainly to block any ground link through that path). It was just a twisted pair of enamelled wire wound onto an RM6 coil former. I started off with subminature coax, but checked to see if twisted pair would work and it did. The Taxichip link used an 10/8 code which avoided data packets with a high DC content. A simple common mode choke would block spikes. -- Bill Sloman, Sydney
whit3rd <whit3rd@gmail.com> wrote in
news:1d2c44a8-0c0a-4acf-a09e-5a845cf4f46b@googlegroups.com: 

> On Friday, December 27, 2019 at 9:18:23 PM UTC-8, > upsid...@downunder.com wrote: >> On Fri, 27 Dec 2019 19:01:04 -0800 (PST), Bill Sloman >> <bill.sloman@ieee.org> wrote: > >> >Two metres isn't far, and he doesn't need isolation. >> >> Unfortunately, the LVDS common mode voltage is quite limited, so >> the Tx and Rx grounds should be within +/- 1 V from each other. > > With a self-clocked modulation scheme, Ethernet magnetics (for > isolation) should keep up with the requirement. You can get four > parallel streams at 125 MHz with long (100M) wires, so a short > link can probably handle the 200 Mbps task with two pairs (send > and receive). > > I presume availability of logic modules for modulation, > demodulation, and FIFO functions? >
You can use plain old CAT6 OR get specialized CAT7 or even newer stuff that is not in the main channel yet if the wire is ever an issue. But we used it and made our own comm link code. And you can get shielded ENET wire too. Cheap, so make two runs and put each direction on one and only use the tighter twisted pair.