MOSFET: why is it called Miller plateau?

Hi,

many papers explain the MOSFET's gate-source charging curve, especially 
the plateau part of it, by the Miller effect. Sometime this is even 
briefly called "the Miller plateau". But why?

To my understanding, the Miller effect is of entirely dynamic nature
and is simply caused by the negative feedback introduced by parasitic
capacitances between the input and the output of an inverting amplifier.
However, if the gate charging time goes to infinity, the effective 
impedance of Cgd is also infinite, so effectively there is no feedback. 
But the plateau can still be observed. I think that this is caused by
the increasing effective capacitance between the gate surface and
the building conductive channel. A sort of rotary variable capacitor,
so to say. Qgs rises, but so does Cgs, so Vgs is approximately constant, 
up to the saturation point -- the channel surface cannot be any bigger 
physically and so there is the deflection point on the right of the 
plateau, where the proportion is restored.

Where am I wrong? If this is correct, then why do people merge two 
unrelated effects into a single "Miller" thing?

	Best regards, Piotr

On Tue, 10 Dec 2019 18:10:20 +0100, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

>Hi,
>
>many papers explain the MOSFET's gate-source charging curve, especially 
>the plateau part of it, by the Miller effect. Sometime this is even 
>briefly called "the Miller plateau". But why?
>
>To my understanding, the Miller effect is of entirely dynamic nature
>and is simply caused by the negative feedback introduced by parasitic
>capacitances between the input and the output of an inverting amplifier.
>However, if the gate charging time goes to infinity, the effective 
>impedance of Cgd is also infinite, so effectively there is no feedback. 
>But the plateau can still be observed. I think that this is caused by
>the increasing effective capacitance between the gate surface and
>the building conductive channel. A sort of rotary variable capacitor,
>so to say. Qgs rises, but so does Cgs, so Vgs is approximately constant, 
>up to the saturation point -- the channel surface cannot be any bigger 
>physically and so there is the deflection point on the right of the 
>plateau, where the proportion is restored.
>
>Where am I wrong? If this is correct, then why do people merge two 
>unrelated effects into a single "Miller" thing?
>
>	Best regards, Piotr

Miller Effect is now a loose description of the effective
multiplication of plate-grid or drain-gate capacitance by the negative
voltage gain of the device. In the active gain region, it makes sense.

In a switching mosfet, the concept aligns with how much gate charge it
takes to switch. It's just delta-q = c * delta-v. Gain makes delta-v
big.

We call that Miller Effect and Miller Capacitance as a sort of
shorthand. Language purists often disapprove of the ways that
engineers talk to one another. Let them freeze in the dark.



-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

jlarkin@highlandsniptechnology.com wrote:

> Miller Effect is now a loose description of the effective
> multiplication of plate-grid or drain-gate capacitance by the negative
> voltage gain of the device. In the active gain region, it makes sense.

It indeed does make sense, but not in quasi-static conditions.
A capacitor has no useful DC impedance.

> We call that Miller Effect and Miller Capacitance as a sort of
> shorthand. Language purists often disapprove of the ways that
> engineers talk to one another. Let them freeze in the dark.

This is not about purism, but about my own consistency check of the 
understanding of the Miller effect. I am perfectly fine with you calling 
that region "Miller plateau" or "Einstein-Podolsky-Rosen plateau" -- it 
has exactly nothing in common with either of them, so both are equally 
OK. Miller wins for being shorter.

	Best regards, Piotr

Piotr Wyderski wrote...
>
> This is not about purism, but about my own consistency
> check of the understanding of the Miller effect. 

 The equation, Q = C V works at DC.  Whenever you want
 to change the voltage on a capacitance, you must keep
 track of charge.  In fact, for convenience, MOSFET
 Miller plots are usually made virtually at DC.  In
 x-Chapters, 3x.12, there's a nice bench test circuit,
 typically run with 1mA gate current, that we use to
 make some fascinating gate-charge measurements, as a
 function of the drain supply voltage.  Some MOSFETs
 have a "textbook" flat curve, others slope upwards.


-- 
 Thanks,
    - Win

On 2019-12-10 18:10, Piotr Wyderski wrote:
> Hi,
>
> many papers explain the MOSFET's gate-source charging curve, especially
> the plateau part of it, by the Miller effect. Sometime this is even
> briefly called "the Miller plateau". But why?
>
> To my understanding, the Miller effect is of entirely dynamic nature
> and is simply caused by the negative feedback introduced by parasitic
> capacitances between the input and the output of an inverting amplifier.
> However, if the gate charging time goes to infinity, the effective
> impedance of Cgd is also infinite, so effectively there is no feedback.
> But the plateau can still be observed. I think that this is caused by
> the increasing effective capacitance between the gate surface and
> the building conductive channel. A sort of rotary variable capacitor,
> so to say. Qgs rises, but so does Cgs, so Vgs is approximately constant,
> up to the saturation point -- the channel surface cannot be any bigger
> physically and so there is the deflection point on the right of the
> plateau, where the proportion is restored.
>
> Where am I wrong? If this is correct, then why do people merge two
> unrelated effects into a single "Miller" thing?
>
>      Best regards, Piotr
>

The plateau exists while Vd is changing. It's Cgd that takes all the 
charge, not Cgs. In my mind, the Miller effect describes exactly that.
Is the plateau still there if you keep Vd constant?

Jeroen Belleman

On Tue, 10 Dec 2019 18:41:32 +0100, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

>jlarkin@highlandsniptechnology.com wrote:
>
>> Miller Effect is now a loose description of the effective
>> multiplication of plate-grid or drain-gate capacitance by the negative
>> voltage gain of the device. In the active gain region, it makes sense.
>
>It indeed does make sense, but not in quasi-static conditions.
>A capacitor has no useful DC impedance.

We don't think of a cap as having a DC impedance. That's meaningless.
But it still has capacitance even when there's no voltage across it.

>
>> We call that Miller Effect and Miller Capacitance as a sort of
>> shorthand. Language purists often disapprove of the ways that
>> engineers talk to one another. Let them freeze in the dark.
>
>This is not about purism, but about my own consistency check of the 
>understanding of the Miller effect. I am perfectly fine with you calling 
>that region "Miller plateau" or "Einstein-Podolsky-Rosen plateau" -- it 
>has exactly nothing in common with either of them, so both are equally 
>OK. Miller wins for being shorter.
>
>	Best regards, Piotr
>

Right, in casual speech, it can refer to Cdg, or Cdg*gain, or the
charge equivalents. "The Miller capacitor" sometimes means any
capacitance between drain and gate. Speech can be casual, but when it
gets down to numbers, it has to be more precise. Doing the numbers
makes the words not matter much.

We say things like "zero" and "infinite" to mean small and big, and
that works too.

-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

Piotr Wyderski <peter.pan@neverland.mil> wrote in
news:qsojhq$1vrh$1@gioia.aioe.org: 

> 
> Hi,
> 
> many papers explain the MOSFET's gate-source charging curve,
> especially the plateau part of it, by the Miller effect. Sometime
> this is even briefly called "the Miller plateau". But why?
> 

  Because it established a ceiling for the miller region, a plotted 
graph which describes the turn on event of the UUT.  It has a start 
point and an event duration, and the miller region and miller plateau 
lie within that.

 Taking readings on several aspects notes one such reading which once 
switching begins, rides flat until the switch on event is complete.  
The ON resistance takes 'a moment' to propagate through the entire 
gate.  It is fast but not instantaneous.  That is why they end up 
classed by how fast they can switch for the radio boys.  For power it 
is how 'hard' they can switch and how fast, and that event takes a 
bit.  It does not slew up instantly. (or down for the resistance).

John Larkin <jlarkin@highland_atwork_technology.com> wrote in 
news:fgovuetdcp48nb8jj9t9ceb98i1ei5iigq@4ax.com:

> We say things like "zero" and "infinite" to mean small and big, and
> that works too.
> 

  As in "The Apollo Program was a BIG boost to the scientific community 
of the entire world..."

  And "John Larkin is a small booster wannabe..."  "...but ended up a 
zero boost Trumpanzee jackass..."

  You mean like that?

Jeroen Belleman wrote:

> The plateau exists while Vd is changing. It's Cgd that takes all the 
> charge, not Cgs. In my mind, the Miller effect describes exactly that.
> Is the plateau still there if you keep Vd constant?

Below is the setup I have in mind. You can see the plateau, but the Cgd 
impedance is huge at this time scale. My working hypothesis is that this
is a purely geometric effect of the conducting, quasi-metallic channel 
formation and the corresponding growth of the gate-channel capacitance.
Since the channel is effectively connected to the source, this implies
growing Cgs and hence flat Vgs curve (up to the channel saturation 
point). This also explains the Cgs(Vds) dependence. This is a kind of 
phase transition, not a Miller issue. Where am I wrong?

	Best regards, Piotr

Version 4
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SYMATTR Value 10V
TEXT 110 200 Left 2 !.tran 100m
TEXT 112 232 Left 2 !.IC V(Vgs)=0

"Piotr Wyderski" <peter.pan@neverland.mil> wrote in message 
news:qsoq3j$vnl$1@gioia.aioe.org...
> Below is the setup I have in mind. You can see the plateau, but the Cgd
> impedance is huge at this time scale. My working hypothesis is that this
> is a purely geometric effect of the conducting, quasi-metallic channel 
> formation and the corresponding growth of the gate-channel capacitance.

What impedance are you defining?  I don't see an impedance statement on the 
sheet.

There's nothing quasi-stable about this system, the drain voltage is 
changing rapidly (it's also not a simple linear ramp, if you want to think 
of that as a quasi-stable condition).

There's nothing physicsy about it: the same gross behavior can be 
demonstrated with a pure SPICE ideal amplifier with finite gain and 
saturating output.


> Since the channel is effectively connected to the source, this implies
> growing Cgs and hence flat Vgs curve (up to the channel saturation point). 
> This also explains the Cgs(Vds) dependence. This is a kind of phase 
> transition, not a Miller issue. Where am I wrong?

The Miller theorem shows that we can express Cdg as an effective Cgs, but 
it's only a reflection of the change in drain voltage, and as soon as that 
change goes away, the Cgs(eff) goes away.  Try clamping drain voltage with a 
diode from another voltage source. :)

Nothing discontinuous occurs, nor anything chaotic or difficult 
(impossible?) to model; it's not a phase transformation, at least not a low 
order one.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/