Forums

FPGA config sizes

Started by John Larkin November 8, 2019
On 2019-11-08 20:23, Rick C wrote:
> On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote: >> We're planning a new universal boot loader for a family of ST >> processors. The uP would host the loader in a bit of local flash and >> read an outboard serial flash to get the specific application code and >> one or more FPGA configurations. >> >> So, how many config bits might there be for a modern mid-range FPGA >> doing a moderately complex application? >> >> I think we could enable compression too. >> >> Please consider this a PHB type question. I don't do FPGA development >> myself, past whiteboarding. > > Anyone know what a "PHB" type question is? >
Pointy-Haired Boss, a character from the Dilbert cartoon. The theme of the cartoon is workplace relations. Jeroen Belleman
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
> > On 2019-11-08 20:23, Rick C wrote: > > > > Anyone know what a "PHB" type question is? > > > > Pointy-Haired Boss, a character from the Dilbert cartoon. > The theme of the cartoon is workplace relations.
Sloman is the model for the 'Wally' character?
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
> On 2019-11-08 20:23, Rick C wrote: > > On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote: > >> We're planning a new universal boot loader for a family of ST > >> processors. The uP would host the loader in a bit of local flash and > >> read an outboard serial flash to get the specific application code and > >> one or more FPGA configurations. > >> > >> So, how many config bits might there be for a modern mid-range FPGA > >> doing a moderately complex application? > >> > >> I think we could enable compression too. > >> > >> Please consider this a PHB type question. I don't do FPGA development > >> myself, past whiteboarding. > > > > Anyone know what a "PHB" type question is? > > > > Pointy-Haired Boss, a character from the Dilbert cartoon. > The theme of the cartoon is workplace relations.
No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon. -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
fredag den 8. november 2019 kl. 23.45.40 UTC+1 skrev Rick C:
> On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote: > > On 2019-11-08 20:23, Rick C wrote: > > > On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote: > > >> We're planning a new universal boot loader for a family of ST > > >> processors. The uP would host the loader in a bit of local flash and > > >> read an outboard serial flash to get the specific application code and > > >> one or more FPGA configurations. > > >> > > >> So, how many config bits might there be for a modern mid-range FPGA > > >> doing a moderately complex application? > > >> > > >> I think we could enable compression too. > > >> > > >> Please consider this a PHB type question. I don't do FPGA development > > >> myself, past whiteboarding. > > > > > > Anyone know what a "PHB" type question is? > > > > > > > Pointy-Haired Boss, a character from the Dilbert cartoon. > > The theme of the cartoon is workplace relations. > > No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon. >
I think we are well past the point where a reference to PHB can be considered obscure in engineering circles https://en.wikipedia.org/wiki/Pointy-haired_Boss
On Friday, November 8, 2019 at 6:07:03 PM UTC-5, Lasse Langwadt Christensen wrote:
> fredag den 8. november 2019 kl. 23.45.40 UTC+1 skrev Rick C: > > On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote: > > > On 2019-11-08 20:23, Rick C wrote: > > > > On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote: > > > >> We're planning a new universal boot loader for a family of ST > > > >> processors. The uP would host the loader in a bit of local flash and > > > >> read an outboard serial flash to get the specific application code and > > > >> one or more FPGA configurations. > > > >> > > > >> So, how many config bits might there be for a modern mid-range FPGA > > > >> doing a moderately complex application? > > > >> > > > >> I think we could enable compression too. > > > >> > > > >> Please consider this a PHB type question. I don't do FPGA development > > > >> myself, past whiteboarding. > > > > > > > > Anyone know what a "PHB" type question is? > > > > > > > > > > Pointy-Haired Boss, a character from the Dilbert cartoon. > > > The theme of the cartoon is workplace relations. > > > > No wonder a Google search didn't find anything. Just the reference is obscure enough, using an abbreviation makes it local jargon. > > > > I think we are well past the point where a reference to PHB can be considered obscure in engineering circles > > https://en.wikipedia.org/wiki/Pointy-haired_Boss
https://lmgtfy.com/?q=phb&s=g -- Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
On Fri, 08 Nov 2019 12:20:44 -0800, John Larkin wrote:

> On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com > wrote: > >>On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote: >>> We're planning a new universal boot loader for a family of ST >>> processors. The uP would host the loader in a bit of local flash and >>> read an outboard serial flash to get the specific application code and >>> one or more FPGA configurations. >>> >>> So, how many config bits might there be for a modern mid-range FPGA >>> doing a moderately complex application? >>> >>> >>Page 21: >> >>https://www.xilinx.com/support/documentation/user_guides/ug570-
ultrascale-configuration.pdf
> > I was just wondering what sort of config file sizes people were really > seeing. Maybe compressed, too. > > Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine > storing maybe four configs in the flash chip.
The built-in bitstream compression merely reuses indentical configuration frames. This gives good results on an empty FPGA, but poor results on a moderately utilised one. We use gzip -9 here. From this thread on the Xilinx forum, https://forums.xilinx.com/t5/FPGA-Configuration/Complete-reconfiguration- with-GZip-ed-bitstream/m-p/667837#M4437 I can see that this gives a compression ranging from 28:1 to 2.8:1, but usually about 3.8 : 1 for a typical FPGA. Please note that ungzipping is only possible in software. You will not be able to use that method if configuring an FPGA directly from a PROM. Regards, Allan
On 08/11/2019 19:08, John Larkin wrote:
> > > We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. >
From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039. LFE5-45 - 8.86Mb From Xilinx UG470 Xilinx Artix 35T and 50T need the same 17.536 Mb MK
On 09/11/2019 09:49, Michael Kellett wrote:
> On 08/11/2019 19:08, John Larkin wrote: >> >> >> We're planning a new universal boot loader for a family of ST >> processors. The uP would host the loader in a bit of local flash and >> read an outboard serial flash to get the specific application code and >> one or more FPGA configurations. >> >> So, how many config bits might there be for a modern mid-range FPGA >> doing a moderately complex application? >> >> I think we could enable compression too. >> >> Please consider this a PHB type question. I don't do FPGA development >> myself, past whiteboarding. >> > From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039. > > LFE5-45 - 8.86Mb > > > From Xilinx UG470 > Xilinx Artix 35T and 50T need the same 17.536 Mb > > MK
Why complicate things with memory soooo cheap ??? Just store raw data...
On Sat, 09 Nov 2019 01:27:44 -0600, Allan Herriman
<allanherriman@hotmail.com> wrote:

>On Fri, 08 Nov 2019 12:20:44 -0800, John Larkin wrote: > >> On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com >> wrote: >> >>>On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote: >>>> We're planning a new universal boot loader for a family of ST >>>> processors. The uP would host the loader in a bit of local flash and >>>> read an outboard serial flash to get the specific application code and >>>> one or more FPGA configurations. >>>> >>>> So, how many config bits might there be for a modern mid-range FPGA >>>> doing a moderately complex application? >>>> >>>> >>>Page 21: >>> >>>https://www.xilinx.com/support/documentation/user_guides/ug570- >ultrascale-configuration.pdf >> >> I was just wondering what sort of config file sizes people were really >> seeing. Maybe compressed, too. >> >> Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine >> storing maybe four configs in the flash chip. > > >The built-in bitstream compression merely reuses indentical configuration >frames. This gives good results on an empty FPGA, but poor results on a >moderately utilised one. > >We use gzip -9 here. From this thread on the Xilinx forum, >https://forums.xilinx.com/t5/FPGA-Configuration/Complete-reconfiguration- >with-GZip-ed-bitstream/m-p/667837#M4437 >I can see that this gives a compression ranging from 28:1 to 2.8:1, but >usually about 3.8 : 1 for a typical FPGA. >Please note that ungzipping is only possible in software. You will not >be able to use that method if configuring an FPGA directly from a PROM. > >Regards, >Allan
I did a little compression thing, file compressor in PowerBasic and unpacker in assembly, based on finding runs of 1s or 0s. Typical compression was 2:1 or better, and the decoder was small and very fast. It configured most FPGAs faster than the un-compressed version, because the 1-or-0 unpack bursts were the tightest possible loops. I wouldn't use that again, because an ARM with hardware SPI or QSPI interfaces, from serial flash and to the FPGA config pins, would probably be faster. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On Sat, 9 Nov 2019 11:15:56 +0000, TTman <kraken.sankey@gmail.com>
wrote:

>On 09/11/2019 09:49, Michael Kellett wrote: >> On 08/11/2019 19:08, John Larkin wrote: >>> >>> >>> We're planning a new universal boot loader for a family of ST >>> processors. The uP would host the loader in a bit of local flash and >>> read an outboard serial flash to get the specific application code and >>> one or more FPGA configurations. >>> >>> So, how many config bits might there be for a modern mid-range FPGA >>> doing a moderately complex application? >>> >>> I think we could enable compression too. >>> >>> Please consider this a PHB type question. I don't do FPGA development >>> myself, past whiteboarding. >>> >> From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039. >> >> LFE5-45 - 8.86Mb >> >> >> From Xilinx UG470 >> Xilinx Artix 35T and 50T need the same 17.536 Mb >> >> MK >Why complicate things with memory soooo cheap ??? Just store raw data...
Compression could save bootup time. The Artix7 that I'm using now is only 17 mbits, but some of the Vertix chips are approaching a gigabit. Luckily, I can't afford them. https://www.digikey.com/product-detail/en/xilinx-inc/XCVU37P-3FSVH2892E/122-XCVU37P-3FSVH2892E-ND/10445719 Probably lots of config bits. -- John Larkin Highland Technology, Inc lunatic fringe electronics