Forums

FPGA config sizes

Started by John Larkin November 8, 2019

We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application? 

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

Am 08.11.19 um 20:08 schrieb John Larkin:
> > > We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. >
The size of the programming file is in the data sheet. It is constant and does not depend on the implemented circuitry. Newer FPGAs may allow to program only some sectors of the chip. regards, Gerhard
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
> We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding.
Anyone know what a "PHB" type question is? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
On Friday, November 8, 2019 at 2:13:18 PM UTC-5, Gerhard Hoffmann wrote:
> Am 08.11.19 um 20:08 schrieb John Larkin: > > > > > > We're planning a new universal boot loader for a family of ST > > processors. The uP would host the loader in a bit of local flash and > > read an outboard serial flash to get the specific application code and > > one or more FPGA configurations. > > > > So, how many config bits might there be for a modern mid-range FPGA > > doing a moderately complex application? > > > > I think we could enable compression too. > > > > Please consider this a PHB type question. I don't do FPGA development > > myself, past whiteboarding. > > > > The size of the programming file is in the data sheet. It is constant > and does not depend on the implemented circuitry. > > Newer FPGAs may allow to program only some sectors of the chip. > > regards, Gerhard
I've never used compression on the bit stream, but I recall there is compression available, possibly even through the tools. I don't have any direct work experience with this, but I have a recollection that most of the bits in an FPGA bit stream are zeros. So some type of a RLL compression may be very useful. Where have you seen info on programming only parts of chips? I recall some years back Xilinx talked about partial configuration, but they never got that working to the point it was generally available. I think they worked on it for a few large customers and they likely decided it wasn't worth the effort. Now, instead of programming a part of an FPGA for different tasks, you can easily just use multiple FPGAs and program them individually. Lattice makes some very tiny FPGA packages. I mean cell phone tiny. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
> We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? >
Page 21: https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
fredag den 8. november 2019 kl. 20.29.31 UTC+1 skrev Rick C:
> On Friday, November 8, 2019 at 2:13:18 PM UTC-5, Gerhard Hoffmann wrote: > > Am 08.11.19 um 20:08 schrieb John Larkin: > > > > > > > > > We're planning a new universal boot loader for a family of ST > > > processors. The uP would host the loader in a bit of local flash and > > > read an outboard serial flash to get the specific application code and > > > one or more FPGA configurations. > > > > > > So, how many config bits might there be for a modern mid-range FPGA > > > doing a moderately complex application? > > > > > > I think we could enable compression too. > > > > > > Please consider this a PHB type question. I don't do FPGA development > > > myself, past whiteboarding. > > > > > > > The size of the programming file is in the data sheet. It is constant > > and does not depend on the implemented circuitry. > > > > Newer FPGAs may allow to program only some sectors of the chip. > > > > regards, Gerhard > > I've never used compression on the bit stream, but I recall there is compression available, possibly even through the tools. I don't have any direct work experience with this, but I have a recollection that most of the bits in an FPGA bit stream are zeros. So some type of a RLL compression may be very useful. >
the bitstream can make the bit file much smaller depending on how much you use of the fpga, but if you decide to encrypt the bitstream and put a key in the fpga you are back at the maximum size
On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com
wrote:

>On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote: >> We're planning a new universal boot loader for a family of ST >> processors. The uP would host the loader in a bit of local flash and >> read an outboard serial flash to get the specific application code and >> one or more FPGA configurations. >> >> So, how many config bits might there be for a modern mid-range FPGA >> doing a moderately complex application? >> > >Page 21: > >https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
I was just wondering what sort of config file sizes people were really seeing. Maybe compressed, too. Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine storing maybe four configs in the flash chip. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
fredag den 8. november 2019 kl. 21.20.55 UTC+1 skrev John Larkin:
> On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com > wrote: > > >On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote: > >> We're planning a new universal boot loader for a family of ST > >> processors. The uP would host the loader in a bit of local flash and > >> read an outboard serial flash to get the specific application code and > >> one or more FPGA configurations. > >> > >> So, how many config bits might there be for a modern mid-range FPGA > >> doing a moderately complex application? > >> > > > >Page 21: > > > >https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf > > I was just wondering what sort of config file sizes people were really > seeing. Maybe compressed, too. > > Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine > storing maybe four configs in the flash chip. >
http://stm32f4-discovery.net/2014/07/library-21-read-sd-card-fatfs-stm32f4xx-devices/
On 08/11/2019 19:08, John Larkin wrote:
> > > We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. >
The uncompressed FPGA configuration file size does not change with the device utilization. You need to look at the data sheet for the particular device. Obviously the compressed file size will be variable - with anything from 0% to near 100% compression ratio dependent on content and compression algorithm.
On Fri, 8 Nov 2019 12:32:39 -0800 (PST), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>fredag den 8. november 2019 kl. 21.20.55 UTC+1 skrev John Larkin: >> On Fri, 8 Nov 2019 11:43:08 -0800 (PST), edward.ming.lee@gmail.com >> wrote: >> >> >On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote: >> >> We're planning a new universal boot loader for a family of ST >> >> processors. The uP would host the loader in a bit of local flash and >> >> read an outboard serial flash to get the specific application code and >> >> one or more FPGA configurations. >> >> >> >> So, how many config bits might there be for a modern mid-range FPGA >> >> doing a moderately complex application? >> >> >> > >> >Page 21: >> > >> >https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf >> >> I was just wondering what sort of config file sizes people were really >> seeing. Maybe compressed, too. >> >> Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine >> storing maybe four configs in the flash chip. >> > >http://stm32f4-discovery.net/2014/07/library-21-read-sd-card-fatfs-stm32f4xx-devices/ >
Interesting, but looks like overkill for a little resident boot loader. We have used SD cards with Zynq chips, but they already know how to boot from SD. https://www.dropbox.com/s/03r1b3zbrqa9lme/P5_SD_1.jpg?raw=1 -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com