Forums

ribbon cable TDR test

Started by John Larkin October 24, 2019
I'm going to have one board in the front of a rackmount box, the
controller, with an FPGA. In the back of the box will be an output
board with an ADUM7703 isolated delta-sigma converter measuring
current. The boards will be connected by an 18" ribbon cable. The
signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data
coming back to the FPGA. Both sigs are source terminated. 

I was worried about signal integrity and didn't find much useful stuff
online, so I tested a ribbon cable .

https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?dl=0

The waveform and edge rate look fine, clean 390 ps rise at the end.
The FPGA will have to deal with the prop delay.

I was going to derive a lossy-line Spice model of the cable based on
these measurements (still might some day) but it looks like this cable
will be plenty good enough.

-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On Friday, October 25, 2019 at 9:57:24 AM UTC+11, John Larkin wrote:
> I'm going to have one board in the front of a rackmount box, the > controller, with an FPGA. In the back of the box will be an output > board with an ADUM7703 isolated delta-sigma converter measuring > current. The boards will be connected by an 18" ribbon cable. The > signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data > coming back to the FPGA. Both sigs are source terminated. > > I was worried about signal integrity and didn't find much useful stuff > online, so I tested a ribbon cable . > > https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?dl=0 > > The waveform and edge rate look fine, clean 390 ps rise at the end. > The FPGA will have to deal with the prop delay. > > I was going to derive a lossy-line Spice model of the cable based on > these measurements (still might some day) but it looks like this cable > will be plenty good enough.
Ribbon cable with every second wire grounded is pretty good. The next stage up is a balanced pair of signals on adjacent wires with grounded wires on either side of the pair. The dielectric/insulator isn't chosen to give good very high frequency characteristics, but eighteen inches (half a metre) isn't far. -- Bill Sloman, Sydney
fredag den 25. oktober 2019 kl. 00.57.24 UTC+2 skrev John Larkin:
> I'm going to have one board in the front of a rackmount box, the > controller, with an FPGA. In the back of the box will be an output > board with an ADUM7703 isolated delta-sigma converter measuring > current. The boards will be connected by an 18" ribbon cable. The > signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data > coming back to the FPGA. Both sigs are source terminated. > > I was worried about signal integrity and didn't find much useful stuff > online, so I tested a ribbon cable . > > https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?dl=0 > > The waveform and edge rate look fine, clean 390 ps rise at the end. > The FPGA will have to deal with the prop delay. > > I was going to derive a lossy-line Spice model of the cable based on > these measurements (still might some day) but it looks like this cable > will be plenty good enough. >
IDE Harddrives managed 33MHz or something like that on ribbon cables, thought at the end they used the special cable with twice the conductors every other one ground if two pairs and three grounds will do you could use SATA cables
On 25/10/2019 03:39, Lasse Langwadt Christensen wrote:
> fredag den 25. oktober 2019 kl. 00.57.24 UTC+2 skrev John Larkin: >> I'm going to have one board in the front of a rackmount box, the >> controller, with an FPGA. In the back of the box will be an output >> board with an ADUM7703 isolated delta-sigma converter measuring >> current. The boards will be connected by an 18" ribbon cable. The >> signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data >> coming back to the FPGA. Both sigs are source terminated. >> >> I was worried about signal integrity and didn't find much useful stuff >> online, so I tested a ribbon cable . >> >> https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?dl=0 >> >> The waveform and edge rate look fine, clean 390 ps rise at the end. >> The FPGA will have to deal with the prop delay. >> >> I was going to derive a lossy-line Spice model of the cable based on >> these measurements (still might some day) but it looks like this cable >> will be plenty good enough. >> > > IDE Harddrives managed 33MHz or something like that on ribbon cables, > thought at the end they used the special cable with twice the conductors > every other one ground > > if two pairs and three grounds will do you could use SATA cables > > > >
Any one care to comment on this related problem. 8 digital outputs (3.3V CMOS from FPGA (guess)) and other things on 37 way D connector, one ground pin for the digital outputs, at one end of the connector. I have to connect this, via about 30cm of cable, to my box and buffer the signals. The goal is to get the best result (for speed and decent pulses) that I can. Plan A is to try with IDC D plugs on the cable and use ribbon cable with T networks of 0603 parts to be optimised in my box at the other end. Plan B is to use tiny resistors in the cable D connector at the source end and T networks of 0603 parts to be optimised in my box at the other end. Cable to be whatever it takes. Plan C is to have an active board at the source plug. Plan D (doing it right with LVDS drivers in the source box) is too late because the source box has been bought and paid for already. A good result would be decent 20ns pulses at 25MHz rate. MK -- This email has been checked for viruses by AVG. https://www.avg.com
On Friday, October 25, 2019 at 8:35:05 PM UTC+11, Michael Kellett wrote:
> On 25/10/2019 03:39, Lasse Langwadt Christensen wrote: > > fredag den 25. oktober 2019 kl. 00.57.24 UTC+2 skrev John Larkin: > >> I'm going to have one board in the front of a rackmount box, the > >> controller, with an FPGA. In the back of the box will be an output > >> board with an ADUM7703 isolated delta-sigma converter measuring > >> current. The boards will be connected by an 18" ribbon cable. The > >> signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data > >> coming back to the FPGA. Both sigs are source terminated. > >> > >> I was worried about signal integrity and didn't find much useful stuff > >> online, so I tested a ribbon cable . > >> > >> https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?dl=0 > >> > >> The waveform and edge rate look fine, clean 390 ps rise at the end. > >> The FPGA will have to deal with the prop delay. > >> > >> I was going to derive a lossy-line Spice model of the cable based on > >> these measurements (still might some day) but it looks like this cable > >> will be plenty good enough. > >> > > > > IDE Harddrives managed 33MHz or something like that on ribbon cables, > > thought at the end they used the special cable with twice the conductors > > every other one ground > > > > if two pairs and three grounds will do you could use SATA cables > > > Any one care to comment on this related problem. > 8 digital outputs (3.3V CMOS from FPGA (guess)) and other things on 37 > way D connector, one ground pin for the digital outputs, at one end of > the connector. > I have to connect this, via about 30cm of cable, to my box and buffer > the signals. > The goal is to get the best result (for speed and decent pulses) that I can.
It's a nice short cable - about 1.5nsec of propagation delay - so it shouldn't be too difficult. You should have enough connections to let you put a ground wire between each of the eight signal wires. This gives each line a characteristic impedance of between 110R and 130R (depending on the ribbon - measure it if you have to, but the manufacturer should be able to tell you if it isn't in the data sheet). If you put a big enough damping resistor on each driver to boost the output impedance to this level, the signal will travel along the cable as half voltage step, but if your receiver has a fairly high input impedance, the reflection at the receiving end will mean that you will see a full step at the receiver, and the should be very little reflection when this reflected step gets back to the driver.
> Plan A is to try with IDC D plugs on the cable and use ribbon cable with > T networks of 0603 parts to be optimised in my box at the other end.
Eight resistors at the driving end should be all that you need. They only dissipated heat whole the cable capacitance is charging up (1.5 nsec in each 40nsec for a 25MHz signal rate) so 0603 should be fine (but check).
> Plan B is to use tiny resistors in the cable D connector at the source > end and T networks of 0603 parts to be optimised in my box at the other > end. Cable to be whatever it takes.
Okay. So what I am saying is that plan B should be fine, and the T network shouldn't be necessary.
> Plan C is to have an active board at the source plug.
If you need a high current drive to cope with getting your voltage swing into a 110R t0 130R transient load (for 1.5 nsec in 40nec whenever you are sending data at 25MHz, this might be necessary.
> Plan D (doing it right with LVDS drivers in the source box) is too late > because the source box has been bought and paid for already.
LVDS sounds like a bit of an overkill for a 25MHz data rate and a 30cm cable.
> A good result would be decent 20ns pulses at 25MHz rate.
At 25MHz you should see steps no more frequently than once every 40nsec. You want them to be reliably high or low when the receiving circuit looks at them, which means getting a 25MHz clock - high for 20nsec, low for 20nsec - down the ribbon cable, and using balance clock signal minimises the amount of noise (cross-talk) injected into adjacent wires. Not doing that certainly screwed up one system that I worked on, which had been fine when originally designed for a 5MHz data rate over a few metres of ribbon cable, but got very cranky when the data rate got pushed up to 10MHz and the cable stretched to 18 metres, when the receiving circuits started getting moved into clean areas. Throwing in opto-isolators made life even more complicated. It wasn't hard to fix, but getting it right took a bit of care. -- Bill Sloman, Sydney
On Fri, 25 Oct 2019 10:34:50 +0100, Michael Kellett <mk@mkesc.co.uk>
wrote:

>On 25/10/2019 03:39, Lasse Langwadt Christensen wrote: >> fredag den 25. oktober 2019 kl. 00.57.24 UTC+2 skrev John Larkin: >>> I'm going to have one board in the front of a rackmount box, the >>> controller, with an FPGA. In the back of the box will be an output >>> board with an ADUM7703 isolated delta-sigma converter measuring >>> current. The boards will be connected by an 18" ribbon cable. The >>> signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data >>> coming back to the FPGA. Both sigs are source terminated. >>> >>> I was worried about signal integrity and didn't find much useful stuff >>> online, so I tested a ribbon cable . >>> >>> https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?dl=0 >>> >>> The waveform and edge rate look fine, clean 390 ps rise at the end. >>> The FPGA will have to deal with the prop delay. >>> >>> I was going to derive a lossy-line Spice model of the cable based on >>> these measurements (still might some day) but it looks like this cable >>> will be plenty good enough. >>> >> >> IDE Harddrives managed 33MHz or something like that on ribbon cables, >> thought at the end they used the special cable with twice the conductors >> every other one ground >> >> if two pairs and three grounds will do you could use SATA cables >> >> >> >> >Any one care to comment on this related problem. >8 digital outputs (3.3V CMOS from FPGA (guess)) and other things on 37 >way D connector, one ground pin for the digital outputs, at one end of >the connector. >I have to connect this, via about 30cm of cable, to my box and buffer >the signals. >The goal is to get the best result (for speed and decent pulses) that I can. > >Plan A is to try with IDC D plugs on the cable and use ribbon cable with >T networks of 0603 parts to be optimised in my box at the other end. > >Plan B is to use tiny resistors in the cable D connector at the source >end and T networks of 0603 parts to be optimised in my box at the other >end. Cable to be whatever it takes. > >Plan C is to have an active board at the source plug. > >Plan D (doing it right with LVDS drivers in the source box) is too late >because the source box has been bought and paid for already. > >A good result would be decent 20ns pulses at 25MHz rate. > >MK
Schmitt triggers are always good. You could leave the transmit end alone and lowpass+Schmitt each line on your end. First guess, 100 ohms and 50 pF then a Schmitt, 5 ns time constant and a partial termination to damp any ringing. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On Thu, 24 Oct 2019 15:57:15 -0700, John Larkin wrote:

> I'm going to have one board in the front of a rackmount box, the > controller, with an FPGA. In the back of the box will be an output board > with an ADUM7703 isolated delta-sigma converter measuring current. The > boards will be connected by an 18" ribbon cable. The signals are a 20 > MHz clock to the ADUM and 20 mpbs delta-sigma data coming back to the > FPGA. Both sigs are source terminated. > > I was worried about signal integrity and didn't find much useful stuff > online, so I tested a ribbon cable . > > https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa?
dl=0 You've basically reinvented IBM tri-lead, which they devised for the IBM 370 series. They used smaller wires, and got a 91 Ohm single-ended single-signal cable. Jon
On Fri, 25 Oct 2019 15:43:58 -0500, Jon Elson <elson@pico-systems.com>
wrote:

>On Thu, 24 Oct 2019 15:57:15 -0700, John Larkin wrote: > >> I'm going to have one board in the front of a rackmount box, the >> controller, with an FPGA. In the back of the box will be an output board >> with an ADUM7703 isolated delta-sigma converter measuring current. The >> boards will be connected by an 18" ribbon cable. The signals are a 20 >> MHz clock to the ADUM and 20 mpbs delta-sigma data coming back to the >> FPGA. Both sigs are source terminated. >> >> I was worried about signal integrity and didn't find much useful stuff >> online, so I tested a ribbon cable . >> >> https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa? >dl=0 >You've basically reinvented IBM tri-lead, which they devised for the IBM >370 series. They used smaller wires, and got a 91 Ohm single-ended >single-signal cable. > >Jon
It's standard 3M ribbon cable. Wiki says "The ribbon cable was invented in 1956 by Cicoil Corporation." I just couldn't find any data on pulse behavior. I should test a much longer chunk, to see some serious drool, then hack a Spice lossy transmission line model to match. I was happy with the rise time over a 2' length. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Saturday, October 26, 2019 at 2:47:37 AM UTC+11, jla...@highlandsniptechnology.com wrote:
> On Fri, 25 Oct 2019 10:34:50 +0100, Michael Kellett <mk@mkesc.co.uk> > wrote: > > >On 25/10/2019 03:39, Lasse Langwadt Christensen wrote: > >> fredag den 25. oktober 2019 kl. 00.57.24 UTC+2 skrev John Larkin:
<snip>
> >Any one care to comment on this related problem. > >8 digital outputs (3.3V CMOS from FPGA (guess)) and other things on 37 > >way D connector, one ground pin for the digital outputs, at one end of > >the connector. > >I have to connect this, via about 30cm of cable, to my box and buffer > >the signals. > >The goal is to get the best result (for speed and decent pulses) that I can. > > > >Plan A is to try with IDC D plugs on the cable and use ribbon cable with > >T networks of 0603 parts to be optimised in my box at the other end. > > > >Plan B is to use tiny resistors in the cable D connector at the source > >end and T networks of 0603 parts to be optimised in my box at the other > >end. Cable to be whatever it takes. > > > >Plan C is to have an active board at the source plug. > > > >Plan D (doing it right with LVDS drivers in the source box) is too late > >because the source box has been bought and paid for already. > > > >A good result would be decent 20ns pulses at 25MHz rate. > > Schmitt triggers are always good. You could leave the transmit end > alone and lowpass+Schmitt each line on your end.
This is remarkably bad advice. The problem with fast signals on ribbon cables (and every other kind of transmission line) is reflections. If you drive a 1.5nec long transmission line with a device that has a lower output impedance than the transmission line (about 120R in this instance) the amplitude of the signal is doubled when it hits far end (potentially damaging the receiver, or at least putting it into a state where it can behave very strangely). Using a Schmitt trigger receiver won't help. If the driver is fast enough to produce a 390psec rise-time, you will see this problem. At the driven end, the reflection will come back as the same double height signal after 3nsec, and wont do the driver any good either.
> First guess, 100 ohms and 50 pF then a Schmitt, 5 ns time constant and > a partial termination to damp any ringing.
A 100R resistor as source terminator (at the driving end) should do all that is necessary. Futzing around at the receiver end is the sort mindless twiddling that ignorant amateurs go in for. -- Bill Sloman, Sydney
On Saturday, October 26, 2019 at 8:44:24 AM UTC+11, John Larkin wrote:
> On Fri, 25 Oct 2019 15:43:58 -0500, Jon Elson <elson@pico-systems.com> > wrote: > > >On Thu, 24 Oct 2019 15:57:15 -0700, John Larkin wrote: > > > >> I'm going to have one board in the front of a rackmount box, the > >> controller, with an FPGA. In the back of the box will be an output board > >> with an ADUM7703 isolated delta-sigma converter measuring current. The > >> boards will be connected by an 18" ribbon cable. The signals are a 20 > >> MHz clock to the ADUM and 20 mpbs delta-sigma data coming back to the > >> FPGA. Both sigs are source terminated. > >> > >> I was worried about signal integrity and didn't find much useful stuff > >> online, so I tested a ribbon cable . > >> > >> https://www.dropbox.com/sh/9l0l34qqyyyg2nh/AABtNoqvuOct1kQ74a3lRUrHa? > >dl=0 > >You've basically reinvented IBM tri-lead, which they devised for the IBM > >370 series. They used smaller wires, and got a 91 Ohm single-ended > >single-signal cable. > > > >Jon > > It's standard 3M ribbon cable. Wiki says "The ribbon cable was > invented in 1956 by Cicoil Corporation." > > I just couldn't find any data on pulse behavior.
Some data sheets list the characteristic impedance. The trick of using a grounded wire between each signal wire makes the signal wires look like tolerable transmission lines.
> I should test a much longer chunk, to see some serious drool, then > hack a Spice lossy transmission line model to match.
You should think about what's actually going on - reflections and some attenuation of the higher frequency components in the current that charges up the transmission line and gets reflected at discontinuities in the transmission line - the ends, mostly. Even Howard Johnson could do better than that.
> I was happy with the rise time over a 2' length.
When you should have been worrying about the reflections, if the rise-time were shorter than the roughly 3nsec propagation delay that you'd expect with two feet (61cm) of ribbon cable. -- Bill Sloman, Sydney