Forums

Flip-Flop in LTSpice, set/reset assertion?

Started by Joerg September 21, 2019
Today I found that a simulation wasn't working right because the set and 
reset on the flip-flop (dflop) in LTSpice has the set and reset inputs 
active high. Yet every modern flip-flop is active low. So I had to 
invert everything on those inputs just for the simulation. The "Special 
Functions" instructions in LTSPice are silent about this issue.

Does this date back to the days of Methusaleh or what could be the reason?

Connecting unused AND gate inputs to terminal 8 as per instructions also 
did not work but that was easy to figure out.

-- 
Regards, Joerg

http://www.analogconsultants.com/
lørdag den 21. september 2019 kl. 16.48.41 UTC+2 skrev Joerg:
> Today I found that a simulation wasn't working right because the set and > reset on the flip-flop (dflop) in LTSpice has the set and reset inputs > active high. Yet every modern flip-flop is active low. So I had to > invert everything on those inputs just for the simulation. The "Special > Functions" instructions in LTSPice are silent about this issue. > > Does this date back to the days of Methusaleh or what could be the reason?
it's a behavioural model that does just what it says on the box, active low inputs is more of a practical implementation detail
Am 21.09.2019 um 16:48 schrieb Joerg:
> Today I found that a simulation wasn't working right because the set and > reset on the flip-flop (dflop) in LTSpice has the set and reset inputs > active high. Yet every modern flip-flop is active low. So I had to > invert everything on those inputs just for the simulation. The "Special > Functions" instructions in LTSPice are silent about this issue. > > Does this date back to the days of Methusaleh or what could be the reason? > > Connecting unused AND gate inputs to terminal 8 as per instructions also > did not work but that was easy to figure out. >
Hello Joerg, The basic digital primitives, (AND, OR, XOR, DFLOP, ...) are independent of any device which you can buy. Even the handling of not used inputs is different. Simply connect nothing on the unused inputs. The LTspice circuit-compiler will then "remove" these pins to make the circuit as simple as possible for the simulation. Don't forget to set a rise time or a delay in DFLOP. Value: td=5n If you want a Q=1 at the start, then somply add a IC=1. Value: td=5n IC=1 Best regards, Helmut
On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com>
wrote:

>Today I found that a simulation wasn't working right because the set and >reset on the flip-flop (dflop) in LTSpice has the set and reset inputs >active high. Yet every modern flip-flop is active low.
Not the ECL parts, like 10EP51. Reset and clear are active high.
On 2019-09-21 08:15, Helmut Sennewald wrote:
> Am 21.09.2019 um 16:48 schrieb Joerg: >> Today I found that a simulation wasn't working right because the set >> and reset on the flip-flop (dflop) in LTSpice has the set and reset >> inputs active high. Yet every modern flip-flop is active low. So I had >> to invert everything on those inputs just for the simulation. The >> "Special Functions" instructions in LTSPice are silent about this issue. >> >> Does this date back to the days of Methusaleh or what could be the >> reason? >> >> Connecting unused AND gate inputs to terminal 8 as per instructions >> also did not work but that was easy to figure out. >> > > Hello Joerg, > > The basic digital primitives, (AND, OR, XOR, DFLOP, ...) are independent > of any device which you can buy. >
So they are always active high for control inputs?
> Even the handling of not used inputs is different. Simply connect > nothing on the unused inputs. The LTspice circuit-compiler will then > "remove" these pins to make the circuit as simple as possible for the > simulation. >
In the instructions under "Special Functions" it says, quote "Unused inputs and outputs are to be connected to terminal 8". I guess that's not correct then. At least it fails in my simulation.
> Don't forget to set a rise time or a delay in DFLOP. > > Value: td=5n >
Also, one must set Vhigh=3.3V or to whichever logic voltage it is to be. Unfortunately that can't be fed in from any real rail which makes unorthodox stuff such as controlled back-feeding difficult.
> If you want a Q=1 at the start, then somply add a IC=1. > > Value: td=5n IC=1 >
In this case I needed to used the CLR pin in a more controlled fashion, where reset happens a few msec after an event. -- Regards, Joerg http://www.analogconsultants.com/
jlarkin@highlandsniptechnology.com wrote...
> >On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com> >wrote: > >>Today I found that a simulation wasn't working right because the set and >>reset on the flip-flop (dflop) in LTSpice has the set and reset inputs >>active high. Yet every modern flip-flop is active low. > > Not the ECL parts, like 10EP51. Reset and clear are active high.
The same is true for the Ancient CD4000 series high-voltage CMOS. -- Thanks, - Win
On 2019-09-21 11:59, Winfield Hill wrote:
> jlarkin@highlandsniptechnology.com wrote... >> >> On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com> >> wrote: >> >>> Today I found that a simulation wasn't working right because the set and >>> reset on the flip-flop (dflop) in LTSpice has the set and reset inputs >>> active high. Yet every modern flip-flop is active low. >> >> Not the ECL parts, like 10EP51. Reset and clear are active high.
That's essentially RF stuff and can't easily be simulated with the LTSpice behavioral models. Most of it needs to be breadboarded anyhow.
> > The same is true for the Ancient CD4000 series high-voltage CMOS. >
True but those are really long in the tooth. I still use them in designs but figured that a modern simulator would use more modern conventions. -- Regards, Joerg http://www.analogconsultants.com/
On Sat, 21 Sep 2019 12:43:42 -0700, Joerg <news@analogconsultants.com>
wrote:

>On 2019-09-21 11:59, Winfield Hill wrote: >> jlarkin@highlandsniptechnology.com wrote... >>> >>> On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com> >>> wrote: >>> >>>> Today I found that a simulation wasn't working right because the set and >>>> reset on the flip-flop (dflop) in LTSpice has the set and reset inputs >>>> active high. Yet every modern flip-flop is active low. >>> >>> Not the ECL parts, like 10EP51. Reset and clear are active high. > > >That's essentially RF stuff and can't easily be simulated with the >LTSpice behavioral models. Most of it needs to be breadboarded anyhow. > >> >> The same is true for the Ancient CD4000 series high-voltage CMOS. >> > >True but those are really long in the tooth. I still use them in designs >but figured that a modern simulator would use more modern conventions.
LT Spice is not very digital. I suspect that the library flops and gates are not behavioral models. More than suspect. I've had shift registers fail because I didn't set a non-zero prop delay. The EL and EP logic behaves very well, just about what the data sheets say. If you need to divide down a 600 MHz oscillator, they are the choice. Just trekked to Safeway. It's brutally hot here, must be pushing 80F. How is it out there?
On Saturday, September 21, 2019 at 4:06:54 PM UTC-4, jla...@highlandsniptechnology.com wrote:
> On Sat, 21 Sep 2019 12:43:42 -0700, Joerg <news@analogconsultants.com> > wrote: > > >On 2019-09-21 11:59, Winfield Hill wrote: > >> jlarkin@highlandsniptechnology.com wrote... > >>> > >>> On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com> > >>> wrote: > >>> > >>>> Today I found that a simulation wasn't working right because the set and > >>>> reset on the flip-flop (dflop) in LTSpice has the set and reset inputs > >>>> active high. Yet every modern flip-flop is active low. > >>> > >>> Not the ECL parts, like 10EP51. Reset and clear are active high. > > > > > >That's essentially RF stuff and can't easily be simulated with the > >LTSpice behavioral models. Most of it needs to be breadboarded anyhow. > > > >> > >> The same is true for the Ancient CD4000 series high-voltage CMOS. > >> > > > >True but those are really long in the tooth. I still use them in designs > >but figured that a modern simulator would use more modern conventions. > > LT Spice is not very digital. I suspect that the library flops and > gates are not behavioral models. More than suspect. > > I've had shift registers fail because I didn't set a non-zero prop > delay.
Same is true in any simulation. The individual devices are evaluated in an arbitrary order. Clock input causes an output change in one FF and the next FF is evaluated after the first, the change will ripple through when it would not in a real part with a finite delay. Kind of a Duh! That's why VHDL has delta delays which still won't protect you if you have any buffers, or other things in the clock path to some FFs (which add a delta delay).
> The EL and EP logic behaves very well, just about what the data sheets > say. If you need to divide down a 600 MHz oscillator, they are the > choice. > > Just trekked to Safeway. It's brutally hot here, must be pushing 80F. > How is it out there?
Here it is a very nice 90&deg;F. Great day to be outside. Why is Joerge ranting about LTSpice? Why isn't he at least thanking Helmut for the advice? Helmut is one of the truly knowledgeable people around on LTSpice. He has been a tremendous aid to the community. He also never insults anyone that I've ever seen. -- Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Am 21.09.19 um 21:43 schrieb Joerg:
> On 2019-09-21 11:59, Winfield Hill wrote: >> jlarkin@highlandsniptechnology.com wrote... >>> >>> On Sat, 21 Sep 2019 07:48:49 -0700, Joerg <news@analogconsultants.com> >>> wrote: >>> >>>> Today I found that a simulation wasn't working right because the set >>>> and >>>> reset on the flip-flop (dflop) in LTSpice has the set and reset inputs >>>> active high. Yet every modern flip-flop is active low. >>> >>> Not the ECL parts, like 10EP51. Reset and clear are active high. > > > That's essentially RF stuff and can't easily be simulated with the > LTSpice behavioral models. Most of it needs to be breadboarded anyhow.
That has nothing to do with RF can be perfectly simulated. It's just that the delay numbers are small. In a previous life, when 10kH an 100K were the newest thing, I have built a nice 100K library for the Simucad Silos simulator. That included setup/hold violations etc. I had only a 200 MHz scope, so I had to make sure that at least the logic was OK to start with.
>> &nbsp; The same is true for the Ancient CD4000 series high-voltage CMOS. > > True but those are really long in the tooth. I still use them in designs > but figured that a modern simulator would use more modern conventions.
You've got that the wrong way. Low active inputs are a very retro 74xx thing. TTL designers speculated that it took more signal energy to produce a LOW input than a HIGH (correct for TTL) and that would give better noise immunity since most of the time these inputs do nothing. That has survived for some time only for some things like 74HCT that allowed burning less power without requiring heavy re-thinking. And no, modern digital design has nothing to do with deploying 74xxx. You formulate your system in VHDL, Verilog or Matlab and that's it. Nobody cares about flipflops, let alone their reset pin polarity. As it happens, I needed more space in may parts store last week and I decided to move most things with pins, 74xx, 10K, 100K etc into plastic containers in the basement. I did not use them in years. Even the rests of glue logic in my designs go into a Coolrunner2. cheers, Gerhard