Forums

1ns max jitter oscillator, cheap - for fast 4 diode sampler

Started by Unknown May 7, 2019
On Wed, 8 May 2019 11:27:00 -0400, bitrex <user@example.net> wrote:

>On 5/8/19 11:15 AM, John Larkin wrote: >> On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote: >> >>> On 5/7/19 5:16 PM, whit3rd wrote: >>>> On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote: >>>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote: >>>> >>>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible) >>>> [and want a low-jitter oscillator] >>>> >>>>> I know I'll appear a dinosaur by saying this, but you really can't beat a >>>>> good old fashioned Wien Bridge oscillator when it comes to spectral >>>>> purity and low phase noise. They certainly beat the crap out of any >>>>> digital synthesis technique IMV. >>>> >>>> The best timing performance requires significant stored energy, >>>> if only for Heisenberg uncertainty principles. That means LC beats RC >>>> circuitry (the resistors don't store energy, they just waste it). A rock >>>> has the full momentum of the standing wave acoustics, so a crystal is better >>>> than LC. Short of maser/resonant cavity references, the possibilities are good >>>> for plain old wires as delay lines (distributed L, C) also. >>>> >>>> World-class timing uses superconducting cavities, if that matters. >>>> >>> >>> There's nothing intrinsic about the poor, besmirched Wien bridge >>> oscillator topology that makes it intrinsically low Q, intrinsically >>> high phase noise, or any of these scurrilous accusations against it! And >>> the topology is already used in ICs to generate accurate sampling >>> clocks, as a matter-of-fact. >> >> Which ICs? >> > >A good number of papers in the literature about design of on-chip low >phase noise Wien bridge clock oscillators: > ><https://core.ac.uk/download/pdf/34451869.pdf> > ><https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en> > >A patent by Infinenon: > ><https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf> > >For clocks in the 100s of kHz to several MHz range the topology seems to >have a lot of nice properties, since unless you want to use off-chip Ls >or crystals your options are rather limited. >
Do any actual chips do this? We're using the LMX2571 frequency synthesizer chip, which has phenomenal jitter performance. Like other new-generation synth chips, it has multiple VCO cores inside, LC oscillators probably. The math is mind-boggling. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On Wednesday, May 8, 2019 at 8:10:45 AM UTC-4, Chris Jones wrote:
> On 08/05/2019 10:40, bitrex wrote: > > On 5/7/19 5:16 PM, whit3rd wrote: > >> On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote: > >>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote: > >> > >>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible) > >> [and want a low-jitter oscillator] > >> > >>> I know I'll appear a dinosaur by saying this, but you really can't > >>> beat a > >>> good old fashioned Wien Bridge oscillator when it comes to spectral > >>> purity and low phase noise. They certainly beat the crap out of any > >>> digital synthesis technique IMV. > >> > >> The best timing performance requires significant stored energy, > >> if only for Heisenberg uncertainty principles.&nbsp;&nbsp; That means LC beats RC > >> circuitry (the resistors don't store energy, they just waste it).&nbsp;&nbsp; A > >> rock > >> has the full momentum of the standing wave acoustics, so a crystal is > >> better > >> than LC.&nbsp;&nbsp; Short of maser/resonant cavity&nbsp; references, the > >> possibilities are good > >> for plain old wires as delay lines (distributed L, C) also. > >> > >> World-class timing uses superconducting cavities, if that matters. > >> > > > > There's nothing intrinsic about the poor, besmirched Wien bridge > > oscillator topology that makes it intrinsically low Q, > Um do you know what Q is? > > intrinsically > > high phase noise, or any of these scurrilous accusations against it! And > > the topology is already used in ICs to generate accurate sampling > > clocks, as a matter-of-fact. > Which ones? I haven't seen it used on a chip. > > > Do they usually put inductors in ICsThey don't usually put inductors in chips if it is not necessary, > because they are big, which means the chips use more area on the wafer > and cost more money to make. They do use inductors on chips, > begrudgingly, when they want a low phase-noise oscillator, because LC > oscillators have better phase noise than RC oscillators, and because > people will pay enough more money for this good phase noise performance > that it justifies the increased cost of the silicon that is occupied by > the big inductor. I have designed the local oscillator of a cellphone > radio chip, and yes it used an LC oscillator, like all of our > competitors also did. > > It is difficult to convince people about things like phase noise, > because most people lack the equipment to measure it easily, and because > LTSpice won't simulate it. You need something a bit more spendy, like > SpectreRF.
Can you see phase noise with a DSO by triggering on the oscillator and then looking at the signal a long time later. And seeing how stable it is wrt time.? George H.
> > I also find it impossible to convince people that their mixer won't work > better with a low-distortion sine wave LO signal than it would with a > nice sharp square wave LO. Again, hard to simulate the noise performance > properly with anything cheap, and the people who know how to measure it > are not the ones who need convincing.
On 5/8/19 11:54 AM, John Larkin wrote:
> On Wed, 8 May 2019 11:27:00 -0400, bitrex <user@example.net> wrote: > >> On 5/8/19 11:15 AM, John Larkin wrote: >>> On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote: >>> >>>> On 5/7/19 5:16 PM, whit3rd wrote: >>>>> On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote: >>>>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote: >>>>> >>>>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible) >>>>> [and want a low-jitter oscillator] >>>>> >>>>>> I know I'll appear a dinosaur by saying this, but you really can't beat a >>>>>> good old fashioned Wien Bridge oscillator when it comes to spectral >>>>>> purity and low phase noise. They certainly beat the crap out of any >>>>>> digital synthesis technique IMV. >>>>> >>>>> The best timing performance requires significant stored energy, >>>>> if only for Heisenberg uncertainty principles. That means LC beats RC >>>>> circuitry (the resistors don't store energy, they just waste it). A rock >>>>> has the full momentum of the standing wave acoustics, so a crystal is better >>>>> than LC. Short of maser/resonant cavity references, the possibilities are good >>>>> for plain old wires as delay lines (distributed L, C) also. >>>>> >>>>> World-class timing uses superconducting cavities, if that matters. >>>>> >>>> >>>> There's nothing intrinsic about the poor, besmirched Wien bridge >>>> oscillator topology that makes it intrinsically low Q, intrinsically >>>> high phase noise, or any of these scurrilous accusations against it! And >>>> the topology is already used in ICs to generate accurate sampling >>>> clocks, as a matter-of-fact. >>> >>> Which ICs? >>> >> >> A good number of papers in the literature about design of on-chip low >> phase noise Wien bridge clock oscillators: >> >> <https://core.ac.uk/download/pdf/34451869.pdf> >> >> <https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en> >> >> A patent by Infinenon: >> >> <https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf> >> >> For clocks in the 100s of kHz to several MHz range the topology seems to >> have a lot of nice properties, since unless you want to use off-chip Ls >> or crystals your options are rather limited. >> > > Do any actual chips do this? > > We're using the LMX2571 frequency synthesizer chip, which has > phenomenal jitter performance. Like other new-generation synth chips, > it has multiple VCO cores inside, LC oscillators probably. The math is > mind-boggling.
Definitively? I cannot say for sure it's not like olden times where you got a schematic with the data-sheet; IC mfgrs don't tell u SHIT without an NDA not even the CPU core voltages of the new shit like in my post a few moments ago. I can only assume that if they patented it there's a decent chance it will be or is being used for something. Not a guarantee sometimes they just sit on them but it seems like a lot of work to pay a team for as just a jerk-off exercise.
John Larkin <jjlarkin@highlandtechnology.com> wrote:

>>That's not what I meant. When you start the LC oscillator, there is a >>random phase between the trigger and the XO. How do you measure that? > > It's a weird digital PLL. A fast ADC is clocked based on the XO and > digitizes the triggered oscillator waveform. A mess of math in an FPGA > figures out the phase difference, does some PID control stuff, and > drives a DAC and a varicap to trim the LC oscillator. Lots of fun > signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.
Excellent. Thanks
On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:

>John Larkin <jjlarkin@highlandtechnology.com> wrote: > >>>That's not what I meant. When you start the LC oscillator, there is a >>>random phase between the trigger and the XO. How do you measure that? >> >> It's a weird digital PLL. A fast ADC is clocked based on the XO and >> digitizes the triggered oscillator waveform. A mess of math in an FPGA >> figures out the phase difference, does some PID control stuff, and >> drives a DAC and a varicap to trim the LC oscillator. Lots of fun >> signals-and-systems-Nyquist-sampling-theorem-control-theory stuff. > >Excellent. Thanks
The Pepper thing, where an analog ramp is suspended for some number of XO clocks, is magnificent. EG&G used to sell a DDG based on that. Theirs was a very bad implementation of a great idea, and the interrupted ramp thing has drift problems for long delays. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin <jjlarkin@highland_snip_technology.com> wrote:

> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote: >>Excellent. Thanks
> The Pepper thing, where an analog ramp is suspended for some number of > XO clocks, is magnificent. EG&G used to sell a DDG based on that. > Theirs was a very bad implementation of a great idea, and the > interrupted ramp thing has drift problems for long delays.
Any more information? All I get is Dr. Pepper and pepper spray.
John Larkin <jjlarkin@highland_snip_technology.com> wrote:

> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote:
>>Excellent. Thanks
> The Pepper thing, where an analog ramp is suspended for some number of > XO clocks, is magnificent. EG&G used to sell a DDG based on that. > Theirs was a very bad implementation of a great idea, and the > interrupted ramp thing has drift problems for long delays.
Any more info? All I get is Dr. pepper and pepper spray
On Wed, 08 May 2019 19:30:32 GMT, Steve Wilson <no@spam.com> wrote:

>John Larkin <jjlarkin@highland_snip_technology.com> wrote: > >> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote: >>>Excellent. Thanks > >> The Pepper thing, where an analog ramp is suspended for some number of >> XO clocks, is magnificent. EG&G used to sell a DDG based on that. >> Theirs was a very bad implementation of a great idea, and the >> interrupted ramp thing has drift problems for long delays. > >Any more information? All I get is Dr. Pepper and pepper spray.
It's referenced in the Wiki article, patent US4968907A. The patent is hard to read, but basically he built a constant-current, linear analog ramp delay generator to cover some modest time span, and suspended the current for some integer number of XO clocks to add time. The async suspensions add time but don't add clock jitter. Brilliant. I had an understanding to license the patent, but decided to do the triggered oscillator thing instead. It's better for long delays. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wednesday, 8 May 2019 17:27:05 UTC+2, bitrex  wrote:
> On 5/8/19 11:15 AM, John Larkin wrote: > > On Tue, 7 May 2019 20:40:35 -0400, bitrex <user@example.net> wrote: > > > >> On 5/7/19 5:16 PM, whit3rd wrote: > >>> On Tuesday, May 7, 2019 at 10:20:49 AM UTC-7, Cursitor Doom wrote: > >>>> On Tue, 07 May 2019 07:14:33 -0700, klaus.kragelund wrote: > >>> > >>>>> I'm working on my ~3ns 4 diode sampler (preferable 1ns if possible) > >>> [and want a low-jitter oscillator] > >>> > >>>> I know I'll appear a dinosaur by saying this, but you really can't beat a > >>>> good old fashioned Wien Bridge oscillator when it comes to spectral > >>>> purity and low phase noise. They certainly beat the crap out of any > >>>> digital synthesis technique IMV. > >>> > >>> The best timing performance requires significant stored energy, > >>> if only for Heisenberg uncertainty principles. That means LC beats RC > >>> circuitry (the resistors don't store energy, they just waste it). A rock > >>> has the full momentum of the standing wave acoustics, so a crystal is better > >>> than LC. Short of maser/resonant cavity references, the possibilities are good > >>> for plain old wires as delay lines (distributed L, C) also. > >>> > >>> World-class timing uses superconducting cavities, if that matters. > >>> > >> > >> There's nothing intrinsic about the poor, besmirched Wien bridge > >> oscillator topology that makes it intrinsically low Q, intrinsically > >> high phase noise, or any of these scurrilous accusations against it! And > >> the topology is already used in ICs to generate accurate sampling > >> clocks, as a matter-of-fact. > > > > Which ICs? > > > > A good number of papers in the literature about design of on-chip low > phase noise Wien bridge clock oscillators: > > <https://core.ac.uk/download/pdf/34451869.pdf> > > <https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_11.20140681/_article/-char/en> > > A patent by Infinenon: > > <https://patentimages.storage.googleapis.com/75/c1/d6/eab596d54fba38/US9231520.pdf> > > For clocks in the 100s of kHz to several MHz range the topology seems to > have a lot of nice properties, since unless you want to use off-chip Ls > or crystals your options are rather limited.
Well, couldn't you add a PLL to boost the frequency to what is needed (in my case 144MHz). If the PLL phase noise if good enough that is Cheers Klaus
On Wednesday, 8 May 2019 21:41:59 UTC+2, John Larkin  wrote:
> On Wed, 08 May 2019 19:30:32 GMT, Steve Wilson <no@spam.com> wrote: > > >John Larkin <jjlarkin@highland_snip_technology.com> wrote: > > > >> On Wed, 08 May 2019 17:35:38 GMT, Steve Wilson <no@spam.com> wrote: > >>>Excellent. Thanks > > > >> The Pepper thing, where an analog ramp is suspended for some number of > >> XO clocks, is magnificent. EG&G used to sell a DDG based on that. > >> Theirs was a very bad implementation of a great idea, and the > >> interrupted ramp thing has drift problems for long delays. > > > >Any more information? All I get is Dr. Pepper and pepper spray. > > It's referenced in the Wiki article, patent US4968907A.
I wasn't able to find the Wiki. Searched it for your name, but nothing popped up. Cheers Klaus