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1ns max jitter oscillator, cheap - for fast 4 diode sampler

Started by Unknown May 7, 2019
John Larkin <jjlarkin@highlandtechnology.com> wrote:

> Here's a cheap semi-linear ramp delay: > > https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0 >
Why not use a current source|
On 8/5/19 12:38 pm, John Larkin wrote:
> Here's a cheap semi-linear ramp delay: > https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0 > Making two ranges would't be hard. Switch the cap or the charging > current.
Or just lower the charge voltage and linearise the exponential charge curve in software. Longer delay -> less dV/dt -> less accurate.
On Wed, 08 May 2019 02:30:11 GMT, Steve Wilson <no@spam.com> wrote:

>John Larkin <jjlarkin@highland_snip_technology.com> wrote: > >> On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote: > >>>John Larkin <jjlarkin@highland_snip_technology.com> wrote: > >>>> It is possible to build an instant-start LC oscillator, and phase-lock >>>> it to a low phase noise XO, and preserve the original trigger timing >>>> with picosecond precision, but I can't tell how. > >>>"preserve the original trigger timing" <- compared to what? > >> Like this: > >> https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0 > >> That oscillator starts instantly when an external trigger comes in, >> but it's phase locked to a crystal oscillator. The XO is at some >> random phase at trigger time. Injection locking would walk the >> triggered oscillator into phase with the XO, which we don't want. > >So you count cycles until you reach the desired time, then start a fast ramp >to set the vernier delay. How you measure the vernier delay time?
In our products, we compute a polynomial at factory cal time to linearize the dac codes going into the ramp comparator. The poly terms go into a cal table. That's why we can use an RC instead of a current source. We use a Keysight time interval counter to cal the ramps. It takes a bit of care to avoid "stitching errors", little hickies every time we add one digital count and jump the ramp back down. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On Wed, 08 May 2019 03:28:25 GMT, Steve Wilson <no@spam.com> wrote:

>John Larkin <jjlarkin@highlandtechnology.com> wrote: > >> Here's a cheap semi-linear ramp delay: >> >> https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0 >> > >Why not use a current source|
Resistors are cheap and very wideband. Fast precision current sources are a real pain. The curvature is small, and a 2nd or 3rd order polynomial onto the DAC data calibrates things nicely. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On 5/7/19 11:00 PM, Clifford Heath wrote:
> On 8/5/19 11:22 am, bitrex wrote: >> On 5/7/19 8:56 PM, Clifford Heath wrote: >>> On 8/5/19 10:21 am, bitrex wrote: >>>> there's nothing intrinsically high phase noise about the Wien bridge >>>> topology or injection locking. it all depends on the implementation.... >>> >>> Injection of phase adjustments doesn't cause phase noise? >>> Tell us another joke, please... >> >> Are you hoping for -infinity dBc? No indeed you can't have that sorry > > Duh. But start with high Q (low phase noise, low resistance->Johnson > noise, LC not RC) and you need smaller kicks to injection lock. Varicap > tuning to reduce the frequency deviation would also allow smaller > injections - you could still use a phase detector to PLL the tuning.
I don't get where this idea come from that the Wien bridge topology is intrinsically low Q. Is it because the open-loop RC network is? The amplifier in the circuit is not just a power buffer to overcome loss like e.g. a Colpitts oscillator or phase-shift oscillator. Look at which terminal the frequency-selective network is connected to, y'all.
On Wednesday, May 8, 2019 at 1:43:22 PM UTC+10, John Larkin wrote:
> On Wed, 08 May 2019 03:28:25 GMT, Steve Wilson <no@spam.com> wrote: > > >John Larkin <jjlarkin@highlandtechnology.com> wrote: > > > >> Here's a cheap semi-linear ramp delay: > >> > >> https://www.dropbox.com/s/hu6ltipwyi8f2go/Timebase_Ramp.JPG?dl=0 > >> > > > >Why not use a current source| > > Resistors are cheap and very wideband. Fast precision current sources > are a real pain.
Precision might be, but running through a calibration procedure (which might take a millisecond, most of it devoted to engaging a microprocessor and turning it off again afterwards) every minute would let you get away with something cheap and practical.
> The curvature is small, and a 2nd or 3rd order > polynomial onto the DAC data calibrates things nicely.
That's one approach. If you want to exploit the full precision of the DAC, a linear ramp makes best use of it. -- Bill Sloman, Sydney
On Tuesday, May 7, 2019 at 4:07:03 PM UTC-7, John Larkin wrote:
> On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote: > > >John Larkin <jjlarkin@highland_snip_technology.com> wrote: > > > >> It is possible to build an instant-start LC oscillator, and phase-lock > >> it to a low phase noise XO, and preserve the original trigger timing > >> with picosecond precision, but I can't tell how.
> Like this: > > https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0 > > That oscillator starts instantly when an external trigger comes in, > but it's phase locked to a crystal oscillator. The XO is at some > random phase at trigger time. Injection locking would walk the > triggered oscillator into phase with the XO, which we don't want.
The asynchronous slick way to do that (we've discussed it in the past) is with a sine/cosine quadrature master oscillator (which can be quartz-locked) and track/hold amps that go into HOLD at the trigger time, with multiplier/summer circuitry. sin(w*t -phi) = sin(w*t) cos(phi) - cos(w*t) sin(phi) after you engage the HOLD, and sin(w*t - w*t) = 0 = sin(w * t) cos(w * t) - cos(w * t) sin (w * t) before (with the track/hold amplifiers tracking the sine and cosine of the master clock). Just like the picture, output goes from flat zero to full sinewave in an instant. Gilbert cells and transformer adders can do the job at a wide range of frequencies.
John Larkin <jjlarkin@highlandtechnology.com> wrote:

> On Wed, 08 May 2019 02:30:11 GMT, Steve Wilson <no@spam.com> wrote: > >>John Larkin <jjlarkin@highland_snip_technology.com> wrote: >> >>> On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote: >> >>>>John Larkin <jjlarkin@highland_snip_technology.com> wrote: >> >>>>> It is possible to build an instant-start LC oscillator, and >>>>> phase-lock it to a low phase noise XO, and preserve the original >>>>> trigger timing with picosecond precision, but I can't tell how. >> >>>>"preserve the original trigger timing" <- compared to what? >> >>> Like this: >> >>> https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0 >> >>> That oscillator starts instantly when an external trigger comes in, >>> but it's phase locked to a crystal oscillator. The XO is at some >>> random phase at trigger time. Injection locking would walk the >>> triggered oscillator into phase with the XO, which we don't want. >> >>So you count cycles until you reach the desired time, then start a fast >>ramp to set the vernier delay. How you measure the vernier delay time? > > In our products, we compute a polynomial at factory cal time to > linearize the dac codes going into the ramp comparator. The poly terms > go into a cal table. That's why we can use an RC instead of a current > source. > > We use a Keysight time interval counter to cal the ramps. > > It takes a bit of care to avoid "stitching errors", little hickies > every time we add one digital count and jump the ramp back down.
That's not what I meant. When you start the LC oscillator, there is a random phase between the trigger and the XO. How do you measure that?
On 8/5/19 2:12 pm, bitrex wrote:
> On 5/7/19 11:00 PM, Clifford Heath wrote: >> On 8/5/19 11:22 am, bitrex wrote: >>> On 5/7/19 8:56 PM, Clifford Heath wrote: >>>> On 8/5/19 10:21 am, bitrex wrote: >>>>> there's nothing intrinsically high phase noise about the Wien >>>>> bridge topology or injection locking. it all depends on the >>>>> implementation.... >>>> >>>> Injection of phase adjustments doesn't cause phase noise? >>>> Tell us another joke, please... >>> >>> Are you hoping for -infinity dBc? No indeed you can't have that sorry >> >> Duh. But start with high Q (low phase noise, low resistance->Johnson >> noise, LC not RC) and you need smaller kicks to injection lock. >> Varicap tuning to reduce the frequency deviation would also allow >> smaller injections - you could still use a phase detector to PLL the >> tuning. > > I don't get where this idea come from that the Wien bridge topology is > intrinsically low Q. Is it because the open-loop RC network is? > > The amplifier in the circuit is not just a power buffer to overcome loss > like e.g. a Colpitts oscillator or phase-shift oscillator. Look at which > terminal the frequency-selective network is connected to, y'all.
Wien relies on the cancellation of two RC phase-shift networks. Both the R's are noisy, so how can the result *not* be noisy? In a good LC, the resistance is far less than 1% of the reactances.
On Wednesday, May 8, 2019 at 2:45:47 PM UTC+10, Steve Wilson wrote:
> John Larkin <jjlarkin@highlandtechnology.com> wrote: > > > On Wed, 08 May 2019 02:30:11 GMT, Steve Wilson <no@spam.com> wrote: > > > >>John Larkin <jjlarkin@highland_snip_technology.com> wrote: > >> > >>> On Tue, 07 May 2019 21:37:16 GMT, Steve Wilson <no@spam.com> wrote: > >> > >>>>John Larkin <jjlarkin@highland_snip_technology.com> wrote: > >> > >>>>> It is possible to build an instant-start LC oscillator, and > >>>>> phase-lock it to a low phase noise XO, and preserve the original > >>>>> trigger timing with picosecond precision, but I can't tell how. > >> > >>>>"preserve the original trigger timing" <- compared to what? > >> > >>> Like this: > >> > >>> https://www.dropbox.com/s/0pldde09649579k/Burst_2.jpg?dl=0 > >> > >>> That oscillator starts instantly when an external trigger comes in, > >>> but it's phase locked to a crystal oscillator. The XO is at some > >>> random phase at trigger time. Injection locking would walk the > >>> triggered oscillator into phase with the XO, which we don't want. > >> > >>So you count cycles until you reach the desired time, then start a fast > >>ramp to set the vernier delay. How you measure the vernier delay time? > > > > In our products, we compute a polynomial at factory cal time to > > linearize the dac codes going into the ramp comparator. The poly terms > > go into a cal table. That's why we can use an RC instead of a current > > source. > > > > We use a Keysight time interval counter to cal the ramps. > > > > It takes a bit of care to avoid "stitching errors", little hickies > > every time we add one digital count and jump the ramp back down. > > That's not what I meant. When you start the LC oscillator, there is a > random phase between the trigger and the XO. How do you measure that?
Start a ramp at the trigger instant. Let it ramp up until the next clock edge but one, stop it, and digitise the static voltage that the ramp settled at. Waiting for at least one clock interval gets past the mess as the ramp gets under way. Back in 1990 we did it with an 800MHz clock and divided up the 1.25nsec clock into 10psec intervals. It took about 40nsec for the digitised interval to come available, and we had to recalibrate the ramp generator every few minutes - one DAC set the ramp starting voltage, and another the ramp slope - but that took less than a millisecond. The system had a pair of timing boards which could also generate edges timed to 10psec between clock edges which made self-calibration tolerably straight-forward. -- Bill Sloman, Sydney