Forums

dac architecture

Started by John Larkin January 5, 2019
John Larkin wrote
>On Sat, 5 Jan 2019 14:05:08 -0800 (PST), "John Miles, KE5FX" ><jmiles@gmail.com> wrote: > >>On Saturday, January 5, 2019 at 1:23:09 PM UTC-8, John Larkin wrote: >>> That circuit is conceptual, certainly not done. Only one comparator >>> switches at a time, and each step would change the frequency PPBs. >>> Sure, lowpass the varicap drive. Even better, make the comparator >>> gains low so the transitions are soft. >>> >> >>Is there a difference between building this circuit and adding an LPF, >>and using a traditional DAC and adding an LPF? Either way, you aren't >>going to add significant phase noise beyond the LPF cutoff. > >Looks pretty different to me. There's no clock to make power supply >and varicap noise. Incremental linearity is almost perfect. Might be >suitable for integration. > >I just thought it was an interesting nonlinear function generator that >I hadn't see before. Low integrator gains would be interesting too.
The old way I did things like that was also clock-less: ADC-8-bits -> address-EPROM-data -> DAC. Conversion table in EPROM [1]. There is then still some noise, as bits do not always appear on the EPROM output at the same time, there are time differences in address lookup, but 't works. For a wider bus use 2 EPROMS for 16 bits etc. [1] EPROMS were those chips with a little window where you could see the silly-con and give it a sun-tan to make it lose its memory. I still have some 2732 around somewhere and an UV tube.
"John Larkin"  wrote in message 
news:nj123e1uhgc6cc1df5n5p2sbkdsi5a2pk2@4ax.com...

On Sat, 05 Jan 2019 19:12:25 GMT, <698839253X6D445TD@nospam.org>
wrote:

> John Larkin wrote >>We were talking about TCXOs. One measures temperature and drives a >>varicap through some nonlinear transfer function to get minumum net >>TC. >> >>We don't want a digital design (ADC, lookup table or polynomial, DAC) >>because that might add phase noise. I guess you could use a static >>polynomial with the equivalent of nonvolatile DPOTS as the >>coefficients. >> >> >>This occurred to me, not as anything practical maybe but as an >>interesting architecture. >> >>https://www.dropbox.com/s/8ls632mndcxqby8/DAC_TCXO.JPG?raw=1 >> >>It's sort of a thermometer-code ADC, but each comparator incrementally >>adds + or - one increment to the output. >> >>As the temperature increases, we jog the output up or down one >>increment at a time. >> >>The sequence of switch settings become a delta-sigma code to make the >>output. >> >>The comparators could be sort of linear, not step outputs, to kind of >>interpolate a bit. Some flash ADCs did something like that, soft >>comparators. > >>Yes, >>but you can get more linear varicap effect by using for example 2. >>This paper shows some topologies and their effect: >> https://www.everythingrf.com/uploads/whitepapers/IEEE_BCTM_092010_2.pdf > >>Then use a linear opamp feedback loop? > >>I am using something like fig 1b on page 3 for my 25 MHz PLL reference for >>Eshail2.
>A TCXO wouldn't need a very linear varactor, but a tight PLL does.
Well... actually...the ones I am designing do.... :-) The problem is compensation skew with control voltage. The compensation might be doing a 500:1 nullification. If the V-F is nonlinear, changing the control voltage, changes the compensation. 0.1% linear is a target. There are two basic ways to linearize the transfer function. Linearizing the varacter or pre-distorting the drive voltage. There are quite a few patents, going back to the 60s on connecting varacters with individual dc offsets to do this. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
>"John Larkin" wrote in message >news:1rp13e1fdvat7c4jhvo6g017gflq2go35a@4ax.com...
>We were talking about TCXOs. One measures temperature and drives a >varicap through some nonlinear transfer function to get minumum net >TC.
>We don't want a digital design (ADC, lookup table or polynomial, DAC) >because that might add phase noise. I guess you could use a static >polynomial with the equivalent of nonvolatile DPOTS as the >coefficients.
Maybe you could use a standard xtal TCXO asic and use it just for its inbuilt nonvolatile DPOTS driving its polynomial compensation? Its a standard problem, already solved for 20+ years. We (Rakon) don't source our own asics to external customers, but AKM does https://www.akm.com/akm/en/product/detail/0041/ -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
>"John Miles, KE5FX" wrote in message >news:b35deca0-e828-43c2-829c-152f4a2628c0@googlegroups.com...
>On Saturday, January 5, 2019 at 1:23:09 PM UTC-8, John Larkin wrote: >> That circuit is conceptual, certainly not done. Only one comparator >> switches at a time, and each step would change the frequency PPBs. >> Sure, lowpass the varicap drive. Even better, make the comparator >> gains low so the transitions are soft. >
>Is there a difference between building this circuit and adding an LPF, >and using a traditional DAC and adding an LPF? Either way, you aren't >going to add significant phase noise beyond the LPF cutoff.
>A DAC-driven control loop can work well without a whole lot of head- >scatching. (Almost) everyone with a GPSDO has one of those. Remember, >TCXOs and OCXOs don't have a lot of kVCO gain, so they aren't that >vulnerable to noise injection. At least not compared to microwave VCOs >that >run at 100 MHz/volt, and that are also often pretuned by DACs.
Its also relative the speciation's that are actually required :-) For xtal TCXOs, despite having say only 20ppm/V, which aint a lot, the limitation for close in phase noise (1Hz) may well be the compensation noise injected onto the varactor, not the oscillator noise. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
On Sun, 6 Jan 2019 18:53:39 -0000, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>>"John Larkin" wrote in message >>news:1rp13e1fdvat7c4jhvo6g017gflq2go35a@4ax.com... > >>We were talking about TCXOs. One measures temperature and drives a >>varicap through some nonlinear transfer function to get minumum net >>TC. > >>We don't want a digital design (ADC, lookup table or polynomial, DAC) >>because that might add phase noise. I guess you could use a static >>polynomial with the equivalent of nonvolatile DPOTS as the >>coefficients. > >Maybe you could use a standard xtal TCXO asic and use it just for its >inbuilt nonvolatile DPOTS driving its polynomial compensation? > >Its a standard problem, already solved for 20+ years.
Sure, you can always buy a chip and an eval board and not design anything and be done. But then, all your competition can too, so it becomes a race to the bottom on volume and cost. I just thought this architecture, delta-sigma in bit-set space, was interesting.
> >We (Rakon) don't source our own asics to external customers, but AKM does > >https://www.akm.com/akm/en/product/detail/0041/
No public data sheet, apparently. How does that one work? -- John Larkin Highland Technology, Inc lunatic fringe electronics
I wrote:

>The old way I did things like that was also clock-less: > ADC-8-bits -> address-EPROM-data -> DAC. >Conversion table in EPROM [1]. >There is then still some noise, as bits do not always appear on the EPROM output at the same time, >there are time differences in address lookup, but 't works. >For a wider bus use 2 EPROMS for 16 bits etc. > >[1] EPROMS were those chips with a little window where you could see the silly-con and give it a sun-tan > to make it lose its memory. I still have some 2732 around somewhere and an UV tube.
PS I would not even bother with a DAC. For tuning, fine tuning that is, an EPROM output with an R2R network as DAC for 256 steps should do, followed by a lowpass. If the EPROM logic output levels are not really CMOS Vss and Vdd, then use a CMOS buffer. Some resistors from the same batch. Clock, what clock? Done it for video with R2R on FPGA output, works great.
<698839253X6D445TD@nospam.org> wrote...
> > PS > I would not even bother with a DAC. > For tuning, fine tuning that is, an EPROM output with > an R2R network as DAC for 256 steps should do ...
But a small cheap DAC is so tempting. I started with a PWM signal filtered with Stephen Woodward's trick, for my MPX-16H DAQ ** and finally realized an honest DAC made more sense, and updated the PCB to an MCP4921, a 12-bit DAC in an SOIC-8 package, only $1.50 qty100. ** MPX-16H bare boards, free, winfieldhill@yahoo.com https://www.dropbox.com/sh/41r9wwgqo7rk3lw/AACKDkCKKJRq8DUvSSfQWkv0a?dl=0 -- Thanks, - Win
On a sunny day (7 Jan 2019 09:23:44 -0800) it happened Winfield Hill
<hill@rowland.harvard.edu> wrote in <q101v00i0r@drn.newsguy.com>:

><698839253X6D445TD@nospam.org> wrote... >> >> PS >> I would not even bother with a DAC. >> For tuning, fine tuning that is, an EPROM output with >> an R2R network as DAC for 256 steps should do ... > > But a small cheap DAC is so tempting. I started with > a PWM signal filtered with Stephen Woodward's trick, > for my MPX-16H DAQ ** and finally realized an honest > DAC made more sense, and updated the PCB to an MCP4921, > a 12-bit DAC in an SOIC-8 package, only $1.50 qty100. > > ** MPX-16H bare boards, free, winfieldhill@yahoo.com > https://www.dropbox.com/sh/41r9wwgqo7rk3lw/AACKDkCKKJRq8DUvSSfQWkv0a?dl=0
Yes, sure, but that is a serial SPI input DAC that needs a clock, and a micro. he wants no clock? The R2R, or if you are brave 8 resistors ratio 1,2,4,8,..128, on the output of an EPROM data bus, well lemme draw something: http://panteltje.com/pub/EPROM_and_R2R_and_varicap_IMG_6710.JPG Resistors are cheap, leaves him more money for skying. Flash ADCs are fast, not so many bits,,, like your 24 ! That is amazing. I have never used a 'duino in my life ;-)
On Mon, 07 Jan 2019 19:12:14 GMT, <698839253X6D445TD@nospam.org>
wrote:

>On a sunny day (7 Jan 2019 09:23:44 -0800) it happened Winfield Hill ><hill@rowland.harvard.edu> wrote in <q101v00i0r@drn.newsguy.com>: > >><698839253X6D445TD@nospam.org> wrote... >>> >>> PS >>> I would not even bother with a DAC. >>> For tuning, fine tuning that is, an EPROM output with >>> an R2R network as DAC for 256 steps should do ... >> >> But a small cheap DAC is so tempting. I started with >> a PWM signal filtered with Stephen Woodward's trick, >> for my MPX-16H DAQ ** and finally realized an honest >> DAC made more sense, and updated the PCB to an MCP4921, >> a 12-bit DAC in an SOIC-8 package, only $1.50 qty100. >> >> ** MPX-16H bare boards, free, winfieldhill@yahoo.com >> https://www.dropbox.com/sh/41r9wwgqo7rk3lw/AACKDkCKKJRq8DUvSSfQWkv0a?dl=0 > >Yes, sure, but that is a serial SPI input DAC that needs a clock, and a micro. >he wants no clock? > >The R2R, or if you are brave 8 resistors ratio 1,2,4,8,..128, > >on the output of an EPROM data bus, well lemme draw something: > >http://panteltje.com/pub/EPROM_and_R2R_and_varicap_IMG_6710.JPG > >Resistors are cheap, leaves him more money for skying.
With season passes to Sugar Bowl and Tahoe Donner, incremental skiing is free. Well, I do have to pay for the mid-day rum+coke. I was thinking of the weird dac as an IC in a TCXO, but generally just thinking of a physically linear delta-sigma thing. It would be tough to make a real 8-bit DAC out of resistors and CMOS levels. You might also sum a large number of bad (2 or 3 bit) DACs to get sort of the same effect I was considering. There are some DACs that implement their three MSBs as 8 equally-weighted resistors. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin wrote:

> We don't want a digital design (ADC, lookup table or polynomial, DAC) > because that might add phase noise.
Not sure if I understand correcty, but whenever there is a discrete level change, there will inevitably be some injection of phase noise. So what are you trying to avoid? Best regards, Piotr