Double balanced diode mixer question

>"Gerhard Hoffmann"  wrote in message 
>news:g6pvi1F7gc5U1@mid.individual.net...

>Am 05.12.18 um 12:06 schrieb dakupoto@gmail.com:
>> Could some electronics guru here pleae help ?
>
>> I want to simulate a double balanced diode mixer
> with a LO frequency of 50 MHz and RF frequency of

>www.rubiola.org,  in particular (linked from there):

<  https://arxiv.org/pdf/physics/0608211.pdf     >

Ahhmmm.... well I can't say I agree with the bit about (p.15)

if= Is .exp(vf/nVt)

with the comment that Is and n "is of limited usefulness ....as those 
parameters are hardly available...."

To the contrary, these are the most basic parameters of the spice diode 
model, readily available, and extremely useful.

The basic problem with the paper for me, is that it is like 30+ years out of 
date. Whilst it looks impressive to belt out huge equations involving 
modified Bessel functions and so forth, it is essentially, of no to little 
value. The reality is, fully practical and optimised design is only possible 
using software tools. Piddling about with ginormous equations is a complete 
waste of time. No one in the modern engineering world, does it, or if they 
do, shouldn't. They are way to large to manage. These university professors 
just haven't caught up to this real world. Possible because it puts them out 
of a job.

The reality is that today (last 20 years) all significant number analog/rf 
design is done in asics, using simulation tools. Period. By significant, I 
mean the billions of mobile phones built using asics.

All asic design is done, essentially, 99.999% using simulation. In practice, 
the vast number of engineers producing real designs, actually have quite 
limited knowledge of the theory described in that paper, yet achieves, 
successful real designs. This is because one only need to know the overall 
principles, and drive the tools that doactually know the details. For 
example, millions that use LTSpice, have no idea how spice works.

The tools just spit out all the correct non-linear analysis results. The 
task of the engineer is to intelligently run parameter sweeps, Monte Carlo 
and Worst Case runs. I suggest having a look at the Cadence web site to see 
the facilities in their tools, e.g. compression points, mixer gain, load 
pull, phase noise etc...all automated.

In fact I am aware of a specific result in phase noise, that to my 
knowledge, only became apparent and understood because of the tools. Manual 
calculation of phase noise, is literally, impossible, for real designs. Yet 
that does not stop one designing novel circuits in simulation with phase 
noise performance exceeding anything attempted by hand or by on the bench.

The world today is a computerised  one. These proffs need to move on.

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html 

On Friday, December 7, 2018 at 12:38:26 PM UTC-5, Kevin Aylward wrote:
> >"Gerhard Hoffmann"  wrote in message 
> >news:g6pvi1F7gc5U1@mid.individual.net...
> 
> >Am 05.12.18 um 12:06 schrieb dakupoto@gmail.com:
> >> Could some electronics guru here pleae help ?
> >
> >> I want to simulate a double balanced diode mixer
> > with a LO frequency of 50 MHz and RF frequency of
> 
> >www.rubiola.org,  in particular (linked from there):
> 
> <  https://arxiv.org/pdf/physics/0608211.pdf     >
> 
> Ahhmmm.... well I can't say I agree with the bit about (p.15)
> 
> if= Is .exp(vf/nVt)
> 
> with the comment that Is and n "is of limited usefulness ....as those 
> parameters are hardly available...."
> 
> To the contrary, these are the most basic parameters of the spice diode 
> model, readily available, and extremely useful.
> 
> The basic problem with the paper for me, is that it is like 30+ years out of 
> date. Whilst it looks impressive to belt out huge equations involving 
> modified Bessel functions and so forth, it is essentially, of no to little 
> value. The reality is, fully practical and optimised design is only possible 
> using software tools. Piddling about with ginormous equations is a complete 
> waste of time. No one in the modern engineering world, does it, or if they 
> do, shouldn't. They are way to large to manage. These university professors 
> just haven't caught up to this real world. Possible because it puts them out 
> of a job.
> 
> The reality is that today (last 20 years) all significant number analog/rf 
> design is done in asics, using simulation tools. Period. By significant, I 
> mean the billions of mobile phones built using asics.
> 
> All asic design is done, essentially, 99.999% using simulation. In practice, 
> the vast number of engineers producing real designs, actually have quite 
> limited knowledge of the theory described in that paper, yet achieves, 
> successful real designs. This is because one only need to know the overall 
> principles, and drive the tools that doactually know the details. For 
> example, millions that use LTSpice, have no idea how spice works.
> 
> The tools just spit out all the correct non-linear analysis results. The 
> task of the engineer is to intelligently run parameter sweeps, Monte Carlo 
> and Worst Case runs. I suggest having a look at the Cadence web site to see 
> the facilities in their tools, e.g. compression points, mixer gain, load 
> pull, phase noise etc...all automated.
> 
> In fact I am aware of a specific result in phase noise, that to my 
> knowledge, only became apparent and understood because of the tools. Manual 
> calculation of phase noise, is literally, impossible, for real designs. Yet 
> that does not stop one designing novel circuits in simulation with phase 
> noise performance exceeding anything attempted by hand or by on the bench.
> 
> The world today is a computerised  one. These proffs need to move on.
> 
> -- Kevin Aylward
> http://www.anasoft.co.uk - SuperSpice
> http://www.kevinaylward.co.uk/ee/index.html

Software tools are worthless unless one knows what 
to expect with a given input set. This was rightfully pointed out to me by my boss in Silicon Labs about 
five years ago.

In this case of an experimental double balanced mixer,
I can believe the results because the power spectrum 
of the IF output has two promienent peaks at the two
frequencies (f_RF - f_LO) and (f_RF + f_LO), as expected.

On the other I am sure one knows about Intel's classic
blunder -- the Itanium microprocessor. It would be 
unwise to assume that Intel, with such vast resources
at its disposal did not spend thousands of engineering 
hours in formal, timing etc., verification of the design.
BUT Mother Nature had the last laugh. The Intel engineers,
in their zeal to design and build the ultimate microprocessor by marrying CISC and RISC on the same 
chip did not consider heating effects -- they ignored physics. 

The results are known to all. As soon as the first 
prototypes were tested, they went into thermal shutdown 
mode, within seconds. The Itanium was designed to power servers -- it would be exciting to have server that is
working one second, and down the next. As one of my past
profs(Dr. Jacob Abraham) at UT-Austin once remarked to 
one of his research students -- "that chip is not going 
to work, even if Intel pours in another billion dollars into it".
  

wrote in message 
news:2d1b2cb7-3bdd-4fdd-b04d-49f24894869d@googlegroups.com...

On Friday, December 7, 2018 at 12:38:26 PM UTC-5, Kevin Aylward wrote:
> >"Gerhard Hoffmann"  wrote in message
> >news:g6pvi1F7gc5U1@mid.individual.net...
>
> >Am 05.12.18 um 12:06 schrieb dakupoto@gmail.com:
> >> Could some electronics guru here pleae help ?
> >
> >> I want to simulate a double balanced diode mixer
> > with a LO frequency of 50 MHz and RF frequency of
>
> >www.rubiola.org,  in particular (linked from there):
>
> <  https://arxiv.org/pdf/physics/0608211.pdf     >
>
> Ahhmmm.... well I can't say I agree with the bit about (p.15)
>
> if= Is .exp(vf/nVt)
>
> with the comment that Is and n "is of limited usefulness ....as those
> parameters are hardly available...."
>
> To the contrary, these are the most basic parameters of the spice diode
> model, readily available, and extremely useful.
>
> The basic problem with the paper for me, is that it is like 30+ years out 
> of
> date. Whilst it looks impressive to belt out huge equations involving
> modified Bessel functions and so forth, it is essentially, of no to little
> value. The reality is, fully practical and optimised design is only 
> possible
> using software tools. Piddling about with ginormous equations is a 
> complete
> waste of time. No one in the modern engineering world, does it, or if they
> do, shouldn't. They are way to large to manage. These university 
> professors
> just haven't caught up to this real world. Possible because it puts them 
> out
> of a job.
>
> The reality is that today (last 20 years) all significant number analog/rf
> design is done in asics, using simulation tools. Period. By significant, I
> mean the billions of mobile phones built using asics.
>
>> All asic design is done, essentially, 99.999% using simulation. In 
>> practice,
>> the vast number of engineers producing real designs, actually have quite
>> limited knowledge of the theory described in that paper, yet achieves,
>> successful real designs. This is because one only need to know the 
>> overall
>> principles, and drive the tools that doactually know the details. For
>> example, millions that use LTSpice, have no idea how spice works.
>
>> The tools just spit out all the correct non-linear analysis results. The
>> task of the engineer is to intelligently run parameter sweeps, Monte 
>> Carlo
>> and Worst Case runs. I suggest having a look at the Cadence web site to 
>> see
>> the facilities in their tools, e.g. compression points, mixer gain, load
>> pull, phase noise etc...all automated.
>
> >In fact I am aware of a specific result in phase noise, that to my
>> knowledge, only became apparent and understood because of the tools. 
>> Manual
>> calculation of phase noise, is literally, impossible, for real designs. 
>> Yet
>> that does not stop one designing novel circuits in simulation with phase
>> noise performance exceeding anything attempted by hand or by on the 
>> bench.
>
>> The world today is a computerised  one. These proffs need to move on.


>Software tools are worthless unless one knows what
>to expect with a given input set. This was rightfully pointed out to me by 
>my boss in Silicon Labs about
>five years ago.

Sure, one needs to understand what they are doing. However, that has no 
baring on the fact that modern, practical, commercial design absolutely 
relies on simulation tools. Its the core way products are designed. Its 
simply *impossible* to design analog products with 100,000s of transistors 
on the bench, or using just pen and paper, or for that matter, digital 
products with billions of transistors.

>In this case of an experimental double balanced mixer,
>I can believe the results because the power spectrum
>of the IF output has two promienent peaks at the two
>frequencies (f_RF - f_LO) and (f_RF + f_LO), as expected.

I agree, and this might rattle a few... in my experience and opinion of 
interviewing ascic engineers, only 1%-2% were "competent", that is, have 
even the most basic understanding of matters such as how a band gap 
reference works, despite claiming 6 such designs on their CV, and 20 years 
of alleged experience. I have a one transistor BG test circuit I use, that 
only 1 in 50 pass. Its pretty stunning actually.

This is a different issue though, form the necessity of using simulation 
tools as fundamental to modern design.

>On the other I am sure one knows about Intel's classic
>blunder -- the Itanium microprocessor. It would be
>unwise to assume that Intel, with such vast resources
>at its disposal did not spend thousands of engineering
>hours in formal, timing etc., verification of the design.
>BUT Mother Nature had the last laugh. The Intel engineers,
>in their zeal to design and build the ultimate microprocessor by marrying 
>CISC and RISC on the same
>chip did not consider heating effects -- they ignored physics.

Sure, one can miss things. Its extremely difficult to ensure that all 
relevant simulations have actually been done. However, 100,000s to millions 
of potential issues *do* get caught in simulations. Simulation can typically 
get a first time pass of extremely complicated analog asics that are 
typically ok for customer sampling, even if they do need a 2nd pass to tidy 
up a few details.

Typically, the errors are not that the simulation can't show them, but that 
even though 100,000s of simulations runs are done, some types of runs are 
simply missed. Sure, it requires knowledge and experience to use simulation 
tools effectively.

>The results are known to all. As soon as the first
>prototypes were tested, they went into thermal shutdown
>mode, within seconds. The Itanium was designed to power servers -- it would 
>be exciting to have server that is
>working one second, and down the next. As one of my past
>profs(Dr. Jacob Abraham) at UT-Austin once remarked to
>one of his research students -- "that chip is not going
>to work, even if Intel pours in another billion dollars into it".

Sure, we all have stories where we made a less than "optimum" design 
decision. Humans make mistakes. That's reality. However, they make way fewer 
when computers are preventing the millions of other mistakes.

One of the key points I was making was concerning the academic based 
approach, i.e. highly complicated equations. These equations are simply 
useless for real design, and its just a fact than, essentially, no one uses 
them. One needs to appreciate that analytic solutions for 99.9999999999999% 
of all equations, are impossible. For example, look what's involved to solve 
just a transistor-resister circuit.

http://www.kevinaylward.co.uk/ee/widlarlambert/widlarlambert.xht

Design today, must be done from the framework of simulation. Understand the 
overall principles, well, qualitivity, and use the tools to do the details.

I am explaining what is actually done, as a matter of fact. Its what I do. 
Billions and billions of stars... err...I mean ASICs units are all designed 
entirely in the virtual world. A typical analog ASICs  might have say, 100 
main blocks, arranged in a hierarchy 10 deep with maybe 100,000 connections. 
Its the only practical way to design such systems

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html