Forums

add one resistor, quiet ugly smps ADC noise

Started by Winfield Hill June 28, 2018
John Larkin wrote:
> > Delta-sigma just uses a duty-cycle-based DAC to balance the input > signal into an integrator. When it's balanced, the duty cycle tells > you the input voltage. Some tricks are played to reduce the duty cycle > ripple and speed things up.
So you adjust the duty until the integrator equals the input. But it seems that a "duty-cycle-based DAC" _is_ an integrator. In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an internal counter and DAC driving one input of a comparator, the output of which was a duty-cycle based digital value. No integrator. It looked cheap to me then. But it seems that the output is equivalent to delta sigma.
> [1] and some questionable claims of more. > > http://www.analog.com/en/products/analog-to-digital-converters/standard-adc/precision-adc-20msps/single-channel-ad-converters/ltc2380-24.html
What is their "integrated digital filter?" That doesn't mean switched capacitor does it? I heard they are evil.
On 06/30/18 14:31, Tom Del Rosso wrote:
> John Larkin wrote: >> >> Delta-sigma just uses a duty-cycle-based DAC to balance the input >> signal into an integrator. When it's balanced, the duty cycle tells >> you the input voltage. Some tricks are played to reduce the duty cycle >> ripple and speed things up. > > So you adjust the duty until the integrator equals the input. But it > seems that a "duty-cycle-based DAC" _is_ an integrator. > > In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an > internal counter and DAC driving one input of a comparator, the output > of which was a duty-cycle based digital value. No integrator. It > looked cheap to me then. But it seems that the output is equivalent to > delta sigma. > > >> [1] and some questionable claims of more. >> >> http://www.analog.com/en/products/analog-to-digital-converters/standard-adc/precision-adc-20msps/single-channel-ad-converters/ltc2380-24.html > > What is their "integrated digital filter?" That doesn't mean switched > capacitor does it? I heard they are evil. > > >
The trick with delta sigma is that the scheme pushes the quantization noise out to higher frequency, where it's easy to filter out. (It's called 'noise shaping'.) It slows down exponentially with the number of bits, like a V-F converter, but the tradeoff can be improved in lots of ways. A lot of clever people have worked on delta sigma converters--it's a bit of a cottage industry in EE departments. Modern delta sigmas usually have multibit front ends like a pipeline converter, which helps the speed and also allows the use of dithering to get rid of idle tones. With a 1-bit converter, out-of-band dithering apparently makes a bit of a mess since there's no way to avoid overdriving the (1-bit) input quantizer. Cheers Phil Hobbs (And no, I don't know how they work exactly either.) -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On Sat, 30 Jun 2018 14:31:00 -0400, "Tom Del Rosso"
<fizzbintuesday@that-google-mail-domain.com> wrote:

>John Larkin wrote: >> >> Delta-sigma just uses a duty-cycle-based DAC to balance the input >> signal into an integrator. When it's balanced, the duty cycle tells >> you the input voltage. Some tricks are played to reduce the duty cycle >> ripple and speed things up. > >So you adjust the duty until the integrator equals the input. But it >seems that a "duty-cycle-based DAC" _is_ an integrator.
Well, one sort of DAC is a precise digital duty cycle followed by a lowpass filter. We do that ourselves to make slow analog voltages, like for offset trims. We use a uP PWM channel, or make a PWM inside an FPGA. Once you're inside an FPGA, you can do delta-sigma instead of simple PWM. (I don't entirely understand how high-precision delta-sigma ADCs or DACs work, specifically how they manage edge accuracy.)
> >In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an >internal counter and DAC driving one input of a comparator, the output >of which was a duty-cycle based digital value. No integrator. It >looked cheap to me then. But it seems that the output is equivalent to >delta sigma. > > >> [1] and some questionable claims of more. >> >> http://www.analog.com/en/products/analog-to-digital-converters/standard-adc/precision-adc-20msps/single-channel-ad-converters/ltc2380-24.html > >What is their "integrated digital filter?" That doesn't mean switched >capacitor does it? I heard they are evil. > >
No, they just do numerical filtering, probably just averaging, on the ADC's raw "24 bit" digital data. The 24 bit data claim is of course nonsense, because unfiltered it has 56 LSBs RMS noise. You could get the same results by adding analog (dither) noise to the front-end of a 16 or 18 bit ADC, then averaging. Maybe that's what they do. May as well buy a delta-sigma ADC and get the same precision for about a tenth the price. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Saturday, June 30, 2018 at 2:32:49 PM UTC-4, Tom Del Rosso wrote:
> John Larkin wrote: > > > > Delta-sigma just uses a duty-cycle-based DAC to balance the input > > signal into an integrator. When it's balanced, the duty cycle tells > > you the input voltage. Some tricks are played to reduce the duty cycle > > ripple and speed things up. > > So you adjust the duty until the integrator equals the input. But it > seems that a "duty-cycle-based DAC" _is_ an integrator. > > In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an > internal counter and DAC driving one input of a comparator, the output > of which was a duty-cycle based digital value. No integrator. It > looked cheap to me then. But it seems that the output is equivalent to > delta sigma.
I don't think so. The DAC is a conventional DAC that converts the counter output to an analog voltage, right? Then that analog signal is compared to the analog input, right? That is a ultra slow linear counting version of a SAR. At the point the comparator trips the counter value is the digital output. Not at all equivalent to a delta sigma. Rick C.
SAR is catching up fast, also in the higher number of bits. I was surprised by the results I got for >=24 bit ADCs. Sigma-Delta still rules though, but I don't think it's due to anything fundamental.

https://www.researchgate.net/publication/325285614_Analog-to-digital_conversion_beyond_20_bits_Applications_architecutres_state_of_the_art_limitations_and_future_prospects

More will be published later, including actual measurements of low-frequency noise.

One obvious thing I "discovered" along the way was that you really have to be super careful with these babies.

Cheers,
Nikolai
gnuarm.deletethisbit@gmail.com wrote:
> On Saturday, June 30, 2018 at 2:32:49 PM UTC-4, Tom Del Rosso wrote: >> John Larkin wrote: >>> >>> Delta-sigma just uses a duty-cycle-based DAC to balance the input >>> signal into an integrator. When it's balanced, the duty cycle tells >>> you the input voltage. Some tricks are played to reduce the duty >>> cycle ripple and speed things up. >> >> So you adjust the duty until the integrator equals the input. But it >> seems that a "duty-cycle-based DAC" _is_ an integrator. >> >> In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an >> internal counter and DAC driving one input of a comparator, the >> output of which was a duty-cycle based digital value. No >> integrator. It looked cheap to me then. But it seems that the >> output is equivalent to delta sigma. > > I don't think so. The DAC is a conventional DAC that converts the > counter output to an analog voltage, right? Then that analog signal > is compared to the analog input, right? That is a ultra slow linear > counting version of a SAR. At the point the comparator trips the > counter value is the digital output. Not at all equivalent to a > delta sigma.
It was an 8-pin DIP. The counter value wasn't output. All that was readable was the comparator output, so the output was the duty cycle.
On 28 Jun 2018 04:35:38 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

> Switching converters and sensitive SAR ADCs don't > go well together. Consider a 3.7 Li-ion to 14V boost > converter, switching 400mA current ramps at 500kHz. > Add a 16-bit ADC, which takes 2us to sampling a signal, > and completes its conversion in 15us. A large fraction > of the ADC samples are degraded by SMPS switching noise.
So there is a proper Sample & Hold in front of the SAR ? Without a S&H any SAR could produce quite erratic results, if the input varies during the SA sequence due to bad anti-aliasing filters or power supply noise. Is the sample pulse synchronized with the converter cycle pulse ? This would at last give consistent measurements, although not quite "correct" values. Integrate & Dump in front would be even better.
On Tuesday, July 3, 2018 at 2:05:02 AM UTC-4, Tom Del Rosso wrote:
> gnuarm.deletethisbit@gmail.com wrote: > > On Saturday, June 30, 2018 at 2:32:49 PM UTC-4, Tom Del Rosso wrote: > >> John Larkin wrote: > >>> > >>> Delta-sigma just uses a duty-cycle-based DAC to balance the input > >>> signal into an integrator. When it's balanced, the duty cycle tells > >>> you the input voltage. Some tricks are played to reduce the duty > >>> cycle ripple and speed things up. > >> > >> So you adjust the duty until the integrator equals the input. But it > >> seems that a "duty-cycle-based DAC" _is_ an integrator. > >> > >> In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an > >> internal counter and DAC driving one input of a comparator, the > >> output of which was a duty-cycle based digital value. No > >> integrator. It looked cheap to me then. But it seems that the > >> output is equivalent to delta sigma. > > > > I don't think so. The DAC is a conventional DAC that converts the > > counter output to an analog voltage, right? Then that analog signal > > is compared to the analog input, right? That is a ultra slow linear > > counting version of a SAR. At the point the comparator trips the > > counter value is the digital output. Not at all equivalent to a > > delta sigma. > > It was an 8-pin DIP. The counter value wasn't output. All that was > readable was the comparator output, so the output was the duty cycle.
Think about this a bit. The output of the comparator will be 50/50 duty cycle when the counter has reached a value where the DAC is approximately equal to the input voltage. How could the bit stream output by the comparator be duty cycle related to the input amplitude? How was this output to be used? Rick C.
upsidedown@downunder.com wrote:
> On 28 Jun 2018 04:35:38 -0700, Winfield Hill > <hill@rowland.harvard.edu> wrote: > >> Switching converters and sensitive SAR ADCs don't >> go well together. Consider a 3.7 Li-ion to 14V boost >> converter, switching 400mA current ramps at 500kHz. >> Add a 16-bit ADC, which takes 2us to sampling a signal, >> and completes its conversion in 15us. A large fraction >> of the ADC samples are degraded by SMPS switching noise. > > So there is a proper Sample & Hold in front of the SAR ? > Without a S&H any SAR could produce quite erratic results, if the > input varies during the SA sequence due to bad anti-aliasing filters > or power supply noise. > > Is the sample pulse synchronized with the converter cycle pulse ? > This would at last give consistent measurements, although not quite > "correct" values. Integrate & Dump in front would be even better. >
A SAR's analog input voltage is indeed held in a Sample & Hold. Although Maxim calls it a "track-and-hold." 73, -- Don Kuenz, KB7RPU
Am 02.07.2018 um 21:24 schrieb Castorp:
> SAR is catching up fast, also in the higher number of bits. I was surprised by the results I got for >=24 bit ADCs. Sigma-Delta still rules though, but I don't think it's due to anything fundamental. > > https://www.researchgate.net/publication/325285614_Analog-to-digital_conversion_beyond_20_bits_Applications_architecutres_state_of_the_art_limitations_and_future_prospects > > More will be published later, including actual measurements of low-frequency noise. > > One obvious thing I "discovered" along the way was that you really have to be super careful with these babies.
Yes. I'm just playing with this one: < https://www.digikey.de/product-detail/de/linear-technology-analog-devices/LTC2500CDKD-32-PBF/LTC2500CDKD-32-PBF-ND/6670442 > because I'm sick of the low frequency noise of my FFT analyzer. It is recommended to leave it alone for 2/3 of the conversion cycle, i.e no toggling of the conversion clock, no activity to read it out etc. It requires a 100 MHz SPI clock or quite clumsy multi-cycle reading at 1 MHz sample rate. regards, Gerhard