Forums

add one resistor, quiet ugly smps ADC noise

Started by Winfield Hill June 28, 2018
On Thu, 28 Jun 2018 12:21:06 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>torsdag den 28. juni 2018 kl. 21.09.47 UTC+2 skrev Winfield Hill: >> Klaus Kragelund wrote... >> > >> > I don't really see the point of your efforts about this >> > With 16bit, one LSB is 200uV >> > >> > You most likely have about 1uF output cap and a switching >> > ripple of 100mV. So you will never measure this correctly >> > if you don't filter the heck out of it, ... >> >> No, sorry, there's a high-res ADC on the circuit board >> near the converter, measuring a TIA-amplifier signal. >> The converter creates 14V for a 50mA LED current source. >> The TIA amp, ADC and smps are sharing grounds, etc., and >> the introduced converter noise looks huge on the amplified >> signal, when viewed on a scope or with the ADC data. But >> the noise disappears from the scope and ADC data while >> the converter is momentarily stopped. BTW, we may only be >> using 10 to 12 bits of the data, but the max noise seen >> must have been at the 4 to 6-bit level! Anyway, I added >> the extra 3rd resistor to the next rev of the PCB and now >> we're happy. I re-purposed a controller bit that wasn't >> busy doing anything else during the ADC conversions. >> >> I thought others might like to know about this little trick. >> > >I've done similar and also paused things like display updates >during burst of sampling > >I believe there also are some MCUs that can automatically go into >"sleepmode" during sampling > > >
Like, computing trashes the on-chip ADC? Makes sense. The ARMs that we use can, I think, have the ADC programmed to sample periodically and then interrupt. So the CPU could sleep-on-interrupt. An external ADC isn't bad; just keep the SPI bus quiet while the ADC is busy. Some SAR ADCs are actually sequenced by the SPI burst, but that's probably OK. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
torsdag den 28. juni 2018 kl. 21.40.29 UTC+2 skrev John Larkin:
> On Thu, 28 Jun 2018 12:21:06 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >torsdag den 28. juni 2018 kl. 21.09.47 UTC+2 skrev Winfield Hill: > >> Klaus Kragelund wrote... > >> > > >> > I don't really see the point of your efforts about this > >> > With 16bit, one LSB is 200uV > >> > > >> > You most likely have about 1uF output cap and a switching > >> > ripple of 100mV. So you will never measure this correctly > >> > if you don't filter the heck out of it, ... > >> > >> No, sorry, there's a high-res ADC on the circuit board > >> near the converter, measuring a TIA-amplifier signal. > >> The converter creates 14V for a 50mA LED current source. > >> The TIA amp, ADC and smps are sharing grounds, etc., and > >> the introduced converter noise looks huge on the amplified > >> signal, when viewed on a scope or with the ADC data. But > >> the noise disappears from the scope and ADC data while > >> the converter is momentarily stopped. BTW, we may only be > >> using 10 to 12 bits of the data, but the max noise seen > >> must have been at the 4 to 6-bit level! Anyway, I added > >> the extra 3rd resistor to the next rev of the PCB and now > >> we're happy. I re-purposed a controller bit that wasn't > >> busy doing anything else during the ADC conversions. > >> > >> I thought others might like to know about this little trick. > >> > > > >I've done similar and also paused things like display updates > >during burst of sampling > > > >I believe there also are some MCUs that can automatically go into > >"sleepmode" during sampling > > > > > > > > Like, computing trashes the on-chip ADC? Makes sense. >
back in the day when I was doing Bluetooth we did a stacked chip with a transceiver and an SoC, everything worked great until the code was mowed to ROM instead of RAM then the sensitivity dropped turned out to be running ROM interfered with the PLL, running code in RAM didn't
On 06/28/18 15:40, John Larkin wrote:
> On Thu, 28 Jun 2018 12:21:06 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> torsdag den 28. juni 2018 kl. 21.09.47 UTC+2 skrev Winfield Hill: >>> Klaus Kragelund wrote... >>>> >>>> I don't really see the point of your efforts about this >>>> With 16bit, one LSB is 200uV >>>> >>>> You most likely have about 1uF output cap and a switching >>>> ripple of 100mV. So you will never measure this correctly >>>> if you don't filter the heck out of it, ... >>> >>> No, sorry, there's a high-res ADC on the circuit board >>> near the converter, measuring a TIA-amplifier signal. >>> The converter creates 14V for a 50mA LED current source. >>> The TIA amp, ADC and smps are sharing grounds, etc., and >>> the introduced converter noise looks huge on the amplified >>> signal, when viewed on a scope or with the ADC data. But >>> the noise disappears from the scope and ADC data while >>> the converter is momentarily stopped. BTW, we may only be >>> using 10 to 12 bits of the data, but the max noise seen >>> must have been at the 4 to 6-bit level! Anyway, I added >>> the extra 3rd resistor to the next rev of the PCB and now >>> we're happy. I re-purposed a controller bit that wasn't >>> busy doing anything else during the ADC conversions. >>> >>> I thought others might like to know about this little trick. >>> >> >> I've done similar and also paused things like display updates >> during burst of sampling >> >> I believe there also are some MCUs that can automatically go into >> "sleepmode" during sampling >> >> >> > > Like, computing trashes the on-chip ADC? Makes sense. > > The ARMs that we use can, I think, have the ADC programmed to sample > periodically and then interrupt. So the CPU could sleep-on-interrupt. > > An external ADC isn't bad; just keep the SPI bus quiet while the ADC > is busy. Some SAR ADCs are actually sequenced by the SPI burst, but > that's probably OK.
We like the 14-bit TI ADC141S626, which works like that. It has this weird continuous mode where you leave CS' low, and it takes 18 clocks for a 14-bit conversion. That's a nuisance since the MCUs we mostly use (NXP Cortex Ms) can't do SPI transfers that long in hardware. However, if you work CS' on each acquisition, it only needs 16 clocks. It has super nice DNL and other good properties, and it's about $3 in thousands. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On Thu, 28 Jun 2018 19:59:53 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 06/28/18 15:40, John Larkin wrote: >> On Thu, 28 Jun 2018 12:21:06 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >>> torsdag den 28. juni 2018 kl. 21.09.47 UTC+2 skrev Winfield Hill: >>>> Klaus Kragelund wrote... >>>>> >>>>> I don't really see the point of your efforts about this >>>>> With 16bit, one LSB is 200uV >>>>> >>>>> You most likely have about 1uF output cap and a switching >>>>> ripple of 100mV. So you will never measure this correctly >>>>> if you don't filter the heck out of it, ... >>>> >>>> No, sorry, there's a high-res ADC on the circuit board >>>> near the converter, measuring a TIA-amplifier signal. >>>> The converter creates 14V for a 50mA LED current source. >>>> The TIA amp, ADC and smps are sharing grounds, etc., and >>>> the introduced converter noise looks huge on the amplified >>>> signal, when viewed on a scope or with the ADC data. But >>>> the noise disappears from the scope and ADC data while >>>> the converter is momentarily stopped. BTW, we may only be >>>> using 10 to 12 bits of the data, but the max noise seen >>>> must have been at the 4 to 6-bit level! Anyway, I added >>>> the extra 3rd resistor to the next rev of the PCB and now >>>> we're happy. I re-purposed a controller bit that wasn't >>>> busy doing anything else during the ADC conversions. >>>> >>>> I thought others might like to know about this little trick. >>>> >>> >>> I've done similar and also paused things like display updates >>> during burst of sampling >>> >>> I believe there also are some MCUs that can automatically go into >>> "sleepmode" during sampling >>> >>> >>> >> >> Like, computing trashes the on-chip ADC? Makes sense. >> >> The ARMs that we use can, I think, have the ADC programmed to sample >> periodically and then interrupt. So the CPU could sleep-on-interrupt. >> >> An external ADC isn't bad; just keep the SPI bus quiet while the ADC >> is busy. Some SAR ADCs are actually sequenced by the SPI burst, but >> that's probably OK. > >We like the 14-bit TI ADC141S626, which works like that. It has this >weird continuous mode where you leave CS' low, and it takes 18 clocks >for a 14-bit conversion. That's a nuisance since the MCUs we mostly use >(NXP Cortex Ms) can't do SPI transfers that long in hardware. > >However, if you work CS' on each acquisition, it only needs 16 clocks. >It has super nice DNL and other good properties, and it's about $3 in >thousands. > >Cheers > >Phil Hobbs
We use ADS7866 for a cheap outboard ADC. SOT-23-6. 12 bits, $1.50 by the reel. I once built a 10-bit ADC out of parts... transistors, no ICs. 3U rackmount. It sold for more than my Austin Healey Sprite. I interfaced it to an IBM 1401. It was used to digitize waveforms from monkey brains. Try to top that! -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
> Converters use two resistors to set the output voltage. > I added a third resistor to the 1.255V feedback node, > connected to a 3.3V controller logic output. When at > 0V the converter works normally maintaining 14 volts. > But a logic high lowers the 14V setpoint by 3.3V, to > nearly 10V, instantly stopping any converter operation. > Doing the disable a few us before triggering the ADC, > and releasing it a few us after, completely eliminates > the degraded ADC sampling, yet still lets the boost > converter keep up with the 14V load requirements.
I'm assuming you were already using a quiet ground for the ADC with a single-point tie to system ground? And possibly a resistor in series with its Vdd pin? And this wasn't enough?
Winfield Hill <hill@rowland.harvard.edu> writes:

> Converters use two resistors to set the output voltage. > I added a third resistor to the 1.255V feedback node, > connected to a 3.3V controller logic output. When at > 0V the converter works normally maintaining 14 volts. > But a logic high lowers the 14V setpoint by 3.3V, to > nearly 10V, instantly stopping any converter operation. > Doing the disable a few us before triggering the ADC, > and releasing it a few us after, completely eliminates > the degraded ADC sampling, yet still lets the boost > converter keep up with the 14V load requirements.
Nice trick, have to try out that one! I've got a sensor design with analog side supplied by TPS61030 and enough caps. -- mikko
"John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message 
news:h0dajdh6jgchvfjm2bpo1uc8745sm8kb7q@4ax.com...
> 16 bits would be awful. Those LTM switcher bricks are pretty quiet. >
Having pushed one through EMC, and seen the ~ns edges from one, I laugh derisively. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/
John Larkin wrote...
> > We use ADS7866 for a cheap outboard ADC. SOT-23-6. > 12 bits, $1.50 by the reel.
After considerable searching, I settled on MCP3201 for my go-to 12-bit ADC. This part has a pin for the voltage reference, so you aren't forced to use the digital supply. It also has separate + and - analog inputs, nice. Or place a 16-bit ADS8325 on the PCB (same MSOP8 pinout), that sealed the deal. -- Thanks, - Win
sea moss wrote...
> > I'm assuming you were already using a quiet ground > for the ADC with a single-point tie to system ground? > And possibly a resistor in series with its Vdd pin? > And this wasn't enough?
Nope, sorry, there was no room for best practices on this long thin PCB. Yes, a separate "quiet" analog supply, but was forced to be satisfied with a single slightly-fattened ground trace running the length of the board. And the TIA amp was next to the 14-volt boost converter. Yes, very risky, but perfectly OK, with the single-added-resistor smps shutoff trick. -- Thanks, - Win
Mikko OH2HVJ wrote...
> >Winfield Hill <hill@rowland.harvard.edu> writes: > >> Converters use two resistors to set the output voltage. >> I added a third resistor to the 1.255V feedback node, >> connected to a 3.3V controller logic output. When at >> 0V the converter works normally maintaining 14 volts. >> But a logic high lowers the 14V setpoint by 3.3V, to >> nearly 10V, instantly stopping any converter operation. >> Doing the disable a few us before triggering the ADC, >> and releasing it a few us after, completely eliminates >> the degraded ADC sampling, yet still lets the boost >> converter keep up with the 14V load requirements. > > Nice trick, have to try out that one! I've got a > sensor design with analog side supplied by TPS61030 > and enough caps.
The TPS61030 has a different soft-start scheme, that looks at the output voltage, so you might be able to momentarily stop conversions with the enable input. But its control scheme might also allow for quick cutoff, with the added resistor trick. Let us know. -- Thanks, - Win