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add one resistor, quiet ugly smps ADC noise

Started by Winfield Hill June 28, 2018
 Switching converters and sensitive SAR ADCs don't
 go well together.  Consider a 3.7 Li-ion to 14V boost
 converter, switching 400mA current ramps at 500kHz.
 Add a 16-bit ADC, which takes 2us to sampling a signal,
 and completes its conversion in 15us.  A large fraction
 of the ADC samples are degraded by SMPS switching noise.
 The boost converter, a TPS61040, has an enable input,
 but if used this triggers a 1 ms soft-start operation,
 so it can't serve as a way to quiet the converter.

 Converters use two resistors to set the output voltage.
 I added a third resistor to the 1.255V feedback node,
 connected to a 3.3V controller logic output.  When at
 0V the converter works normally maintaining 14 volts.
 But a logic high lowers the 14V setpoint by 3.3V, to
 nearly 10V, instantly stopping any converter operation.
 Doing the disable a few us before triggering the ADC,
 and releasing it a few us after, completely eliminates
 the degraded ADC sampling, yet still lets the boost
 converter keep up with the 14V load requirements.

 Note, not all converter ICs can be stopped so easily.
 The TPS61040 uses a pulse-frequency modulation (PFM)
 scheme, with constant peak current, and makes its
 switching decisions on a pulse-by-pulse basis.


-- 
 Thanks,
    - Win
Winfield Hill <hill@rowland.harvard.edu> wrote:
> Switching converters and sensitive SAR ADCs don't > go well together. Consider a 3.7 Li-ion to 14V boost > converter, switching 400mA current ramps at 500kHz. > Add a 16-bit ADC, which takes 2us to sampling a signal, > and completes its conversion in 15us. A large fraction > of the ADC samples are degraded by SMPS switching noise. > The boost converter, a TPS61040, has an enable input, > but if used this triggers a 1 ms soft-start operation, > so it can't serve as a way to quiet the converter. > > Converters use two resistors to set the output voltage. > I added a third resistor to the 1.255V feedback node, > connected to a 3.3V controller logic output. When at > 0V the converter works normally maintaining 14 volts. > But a logic high lowers the 14V setpoint by 3.3V, to > nearly 10V, instantly stopping any converter operation. > Doing the disable a few us before triggering the ADC, > and releasing it a few us after, completely eliminates > the degraded ADC sampling, yet still lets the boost > converter keep up with the 14V load requirements. > > Note, not all converter ICs can be stopped so easily. > The TPS61040 uses a pulse-frequency modulation (PFM) > scheme, with constant peak current, and makes its > switching decisions on a pulse-by-pulse basis. >
If a schematic's worth a thousand words, a schematic with component values is worth even more. :0) FWIW, you leave me with the impression that you're doing something similar to this: -----------------------+--------------------------------o +14V | +------------+ R1 2.2M | TPS61040 | | | | | | FB +-------+---R3-----< +3.3V Enable | | | 68k | GND +---+ | | + | R2 180k +------------+ | | -------------------+---+--------------------------------o GND 73, -- Don Kuenz, KB7RPU
On 28 Jun 2018 04:35:38 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

> Switching converters and sensitive SAR ADCs don't > go well together. Consider a 3.7 Li-ion to 14V boost > converter, switching 400mA current ramps at 500kHz. > Add a 16-bit ADC, which takes 2us to sampling a signal, > and completes its conversion in 15us. A large fraction > of the ADC samples are degraded by SMPS switching noise. > The boost converter, a TPS61040, has an enable input, > but if used this triggers a 1 ms soft-start operation, > so it can't serve as a way to quiet the converter. > > Converters use two resistors to set the output voltage. > I added a third resistor to the 1.255V feedback node, > connected to a 3.3V controller logic output. When at > 0V the converter works normally maintaining 14 volts. > But a logic high lowers the 14V setpoint by 3.3V, to > nearly 10V, instantly stopping any converter operation. > Doing the disable a few us before triggering the ADC, > and releasing it a few us after, completely eliminates > the degraded ADC sampling, yet still lets the boost > converter keep up with the 14V load requirements. > > Note, not all converter ICs can be stopped so easily. > The TPS61040 uses a pulse-frequency modulation (PFM) > scheme, with constant peak current, and makes its > switching decisions on a pulse-by-pulse basis.
How well does that work? Stopping the switcher will kill the big switching ringing, the main noise source, but will "freeze" the ripple at random voltages. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Don Kuenz, KB7RPU wrote...
> >Winfield Hill <hill@rowland.harvard.edu> wrote: >> Switching converters and sensitive SAR ADCs don't >> go well together. Consider a 3.7 Li-ion to 14V boost >> converter, switching 400mA current ramps at 500kHz. >> Add a 16-bit ADC, which takes 2us to sampling a signal, >> and completes its conversion in 15us. A large fraction >> of the ADC samples are degraded by SMPS switching noise. >> The boost converter, a TPS61040, has an enable input, >> but if used this triggers a 1 ms soft-start operation, >> so it can't serve as a way to quiet the converter. >> >> Converters use two resistors to set the output voltage. >> I added a third resistor to the 1.255V feedback node, >> connected to a 3.3V controller logic output. When at >> 0V the converter works normally maintaining 14 volts. >> But a logic high lowers the 14V setpoint by 3.3V, to >> nearly 10V, instantly stopping any converter operation. >> Doing the disable a few us before triggering the ADC, >> and releasing it a few us after, completely eliminates >> the degraded ADC sampling, yet still lets the boost >> converter keep up with the 14V load requirements. >> >> Note, not all converter ICs can be stopped so easily. >> The TPS61040 uses a pulse-frequency modulation (PFM) >> scheme, with constant peak current, and makes its >> switching decisions on a pulse-by-pulse basis. >> > >If a schematic's worth a thousand words, a schematic with component >values is worth even more. :0) FWIW, you leave me with the impression >that you're doing something similar to this: > >-----------------------+--------------------------------o +14V > | > +------------+ R1 2.2M > | TPS61040 | | > | | | > | FB +-------+---R3-----< +3.3V Enable > | | | 68k > | GND +---+ | > | + | R2 180k > +------------+ | | >-------------------+---+--------------------------------o GND > > >73,
Thanks, close, but if a 3.3V logic signal swing is to lower the output setpoint by 3.3V, then R3 = R1. In fact I used R1=R3= 2.49M and R2= 167k. -- Thanks, - Win
John Larkin wrote...
> > Winfield Hill wrote: > >> Switching converters and sensitive SAR ADCs don't >> go well together. Consider a 3.7 Li-ion to 14V boost >> converter, switching 400mA current ramps at 500kHz. >> Add a 16-bit ADC, which takes 2us to sampling a signal, >> and completes its conversion in 15us. A large fraction >> of the ADC samples are degraded by SMPS switching noise. >> The boost converter, a TPS61040, has an enable input, >> but if used this triggers a 1 ms soft-start operation, >> so it can't serve as a way to quiet the converter. >> >> Converters use two resistors to set the output voltage. >> I added a third resistor to the 1.255V feedback node, >> connected to a 3.3V controller logic output. When at >> 0V the converter works normally maintaining 14 volts. >> But a logic high lowers the 14V setpoint by 3.3V, to >> nearly 10V, instantly stopping any converter operation. >> Doing the disable a few us before triggering the ADC, >> and releasing it a few us after, completely eliminates >> the degraded ADC sampling, yet still lets the boost >> converter keep up with the 14V load requirements. >> >> Note, not all converter ICs can be stopped so easily. >> The TPS61040 uses a pulse-frequency modulation (PFM) >> scheme, with constant peak current, and makes its >> switching decisions on a pulse-by-pulse basis. > > How well does that work? Stopping the switcher will > kill the big switching ringing, the main noise source, > but will "freeze" the ripple at random voltages.
It works extremely well. The "noise" isn't from inductor-switch node ringing, etc., but rather from fast di/dt ground bounce, etc. This kind of noise is very fast, transient, and instantly disappears. -- Thanks, - Win
Hi

I don&rsquo;t really see the point of your efforts about this

With 16bit, one LSB is 200uV

You most likely have about 1uF output cap and a switching ripple of 100mV. So you will never measure this correctly if you don&rsquo;t filter the heck out of it, and the 1us idle makes no sense, since if you have filtered it will be noise free

By the way, I have done digital switch modes a couple of times and digested many papers, and have never seen a system with more than 12LSB

Cheers

Klaus
Klaus Kragelund wrote...
> > I don't really see the point of your efforts about this > With 16bit, one LSB is 200uV > > You most likely have about 1uF output cap and a switching > ripple of 100mV. So you will never measure this correctly > if you don't filter the heck out of it, ...
No, sorry, there's a high-res ADC on the circuit board near the converter, measuring a TIA-amplifier signal. The converter creates 14V for a 50mA LED current source. The TIA amp, ADC and smps are sharing grounds, etc., and the introduced converter noise looks huge on the amplified signal, when viewed on a scope or with the ADC data. But the noise disappears from the scope and ADC data while the converter is momentarily stopped. BTW, we may only be using 10 to 12 bits of the data, but the max noise seen must have been at the 4 to 6-bit level! Anyway, I added the extra 3rd resistor to the next rev of the PCB and now we're happy. I re-purposed a controller bit that wasn't busy doing anything else during the ADC conversions. I thought others might like to know about this little trick. -- Thanks, - Win
torsdag den 28. juni 2018 kl. 20.49.38 UTC+2 skrev Klaus Kragelund:
> Hi > > I don&rsquo;t really see the point of your efforts about this > > With 16bit, one LSB is 200uV > > You most likely have about 1uF output cap and a switching ripple of 100mV. So you will never measure this correctly if you don&rsquo;t filter the heck out of it, and the 1us idle makes no sense, since if you have filtered it will be noise free > > By the way, I have done digital switch modes a couple of times and digested many papers, and have never seen a system with more than 12LSB > > Cheers > > Klaus
afaiu the switcher and ADC are not related they just have to live together
torsdag den 28. juni 2018 kl. 21.09.47 UTC+2 skrev Winfield Hill:
> Klaus Kragelund wrote... > > > > I don't really see the point of your efforts about this > > With 16bit, one LSB is 200uV > > > > You most likely have about 1uF output cap and a switching > > ripple of 100mV. So you will never measure this correctly > > if you don't filter the heck out of it, ... > > No, sorry, there's a high-res ADC on the circuit board > near the converter, measuring a TIA-amplifier signal. > The converter creates 14V for a 50mA LED current source. > The TIA amp, ADC and smps are sharing grounds, etc., and > the introduced converter noise looks huge on the amplified > signal, when viewed on a scope or with the ADC data. But > the noise disappears from the scope and ADC data while > the converter is momentarily stopped. BTW, we may only be > using 10 to 12 bits of the data, but the max noise seen > must have been at the 4 to 6-bit level! Anyway, I added > the extra 3rd resistor to the next rev of the PCB and now > we're happy. I re-purposed a controller bit that wasn't > busy doing anything else during the ADC conversions. > > I thought others might like to know about this little trick. >
I've done similar and also paused things like display updates during burst of sampling I believe there also are some MCUs that can automatically go into "sleepmode" during sampling
On 28 Jun 2018 12:09:24 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>Klaus Kragelund wrote... >> >> I don't really see the point of your efforts about this >> With 16bit, one LSB is 200uV >> >> You most likely have about 1uF output cap and a switching >> ripple of 100mV. So you will never measure this correctly >> if you don't filter the heck out of it, ... > > No, sorry, there's a high-res ADC on the circuit board > near the converter, measuring a TIA-amplifier signal. > The converter creates 14V for a 50mA LED current source. > The TIA amp, ADC and smps are sharing grounds, etc., and > the introduced converter noise looks huge on the amplified > signal, when viewed on a scope or with the ADC data. But > the noise disappears from the scope and ADC data while > the converter is momentarily stopped. BTW, we may only be > using 10 to 12 bits of the data, but the max noise seen > must have been at the 4 to 6-bit level! Anyway, I added > the extra 3rd resistor to the next rev of the PCB and now > we're happy. I re-purposed a controller bit that wasn't > busy doing anything else during the ADC conversions. > > I thought others might like to know about this little trick.
That is slick. We's considering an EOM driver with a 9 Gs/s, 14-bit DAC on the same board with switchers. The active shot is under 50 ns, so we could kill all the power supplies when we fire the DAC. Here's a board with a 12-bit, 250 Ms/s ADC a few inches from some switchers. https://www.dropbox.com/s/opa02hou39tduiq/ESM_rev_B.jpg?raw=1 ADC noise is about 1 LSB RMS, dumb luck mostly. Well, everything is differential. 16 bits would be awful. Those LTM switcher bricks are pretty quiet. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com