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Spice speed

Started by John Larkin February 9, 2018


I added a *comment* to my LT Spice simulation and it slowed it down
about 20:1.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

On 2/9/2018 10:56 AM, John Larkin wrote:
> > > > I added a *comment* to my LT Spice simulation and it slowed it down > about 20:1.
I have put comments all over my simulations and never run into that problem. Are you sure it was tagged as a comment and not a directive? Are you willing to share your file?
On Fri, 9 Feb 2018 11:03:47 -0600, John S <Sophi.2@invalid.org> wrote:

>On 2/9/2018 10:56 AM, John Larkin wrote: >> >> >> >> I added a *comment* to my LT Spice simulation and it slowed it down >> about 20:1. > >I have put comments all over my simulations and never run into that >problem. Are you sure it was tagged as a comment and not a directive? > >Are you willing to share your file? >
Sorry, can't do that. I bailed out of the sim and ran a saved file, and it's better. Still slow, but better. The circuit has a wide range of time constants, down to picoseconds, and has to run for tens of us, so it's slow and exquisitly sensitive to any changes. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On 02/09/2018 11:56 AM, John Larkin wrote:
> > > > I added a *comment* to my LT Spice simulation and it slowed it down > about 20:1. > >
Assuming you're using the "alternate solver" - have you tried playing with the settings underneath for "matrix compiler" where you can select "pseduo code" or "object code"?
Am 09.02.2018 um 17:56 schrieb John Larkin:
> > > > I added a *comment* to my LT Spice simulation and it slowed it down > about 20:1. >
A friend of mine once removed a NOP from a loop in a disk driver for the then new Fairchild Clipper CPU. That also slowed it down by a factor of 20 or so. It turned out that Fairchild removed defective cache lines by laser zapping and the missing NOP moved the loop to an address that then led to cache thrashing. regards, Gerhard
"John Larkin"  wrote in message 
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On Fri, 9 Feb 2018 11:03:47 -0600, John S <Sophi.2@invalid.org> wrote:

>On 2/9/2018 10:56 AM, John Larkin wrote: >> >> >> >> I added a *comment* to my LT Spice simulation and it slowed it down >> about 20:1. > >>I have put comments all over my simulations and never run into that >>problem. Are you sure it was tagged as a comment and not a directive? > >>Are you willing to share your file? >
>Sorry, can't do that.
>I bailed out of the sim and ran a saved file, and it's better. Still >slow, but better. The circuit has a wide range of time constants, down >to picoseconds, and has to run for tens of us, so it's slow and >exquisitly sensitive to any changes.
Note: to optimise the speed, you should twiddle with TRTOL and RELTOL. LTSpice has a default of TRTOL=1, which is a departure from the Spice3 default of TRTOL=7 This is used as a safe bet for things like SMPS and Delta-Sima converters. However, it can slow the simulation by a factor of 3. Ken Kundert (Cadence/Spectre) is a proponent of not messing with TRTOL from it's Spice3 value and using RELTOL instead. I usually piss about with both. -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
On Fri, 9 Feb 2018 18:54:43 -0000, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>"John Larkin" wrote in message >news:ijnr7dlp1veo5n8p76drndnqcr85enrjn8@4ax.com... > >On Fri, 9 Feb 2018 11:03:47 -0600, John S <Sophi.2@invalid.org> wrote: > >>On 2/9/2018 10:56 AM, John Larkin wrote: >>> >>> >>> >>> I added a *comment* to my LT Spice simulation and it slowed it down >>> about 20:1. >> >>>I have put comments all over my simulations and never run into that >>>problem. Are you sure it was tagged as a comment and not a directive? >> >>>Are you willing to share your file? >> > >>Sorry, can't do that. > >>I bailed out of the sim and ran a saved file, and it's better. Still >>slow, but better. The circuit has a wide range of time constants, down >>to picoseconds, and has to run for tens of us, so it's slow and >>exquisitly sensitive to any changes. > >Note: to optimise the speed, you should twiddle with TRTOL and RELTOL. > >LTSpice has a default of TRTOL=1, which is a departure from the Spice3 >default of TRTOL=7 > >This is used as a safe bet for things like SMPS and Delta-Sima converters. >However, it can slow the simulation by a factor of 3. > >Ken Kundert (Cadence/Spectre) is a proponent of not messing with TRTOL from >it's Spice3 value and using RELTOL instead. I usually piss about with both.
Setting reltol=0.002 and trtol=5 speeds things up a lot. I have no idea what that does to my sim accuracy, but I do like the waveforms that I see. Setting abstol to 1 nA helps some too. I'm mostly dealing with amps. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
"John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message 
news:iees7dl11eb6comefdk8fqtet634rt9qa4@4ax.com...
> Setting reltol=0.002 and trtol=5 speeds things up a lot. I have no > idea what that does to my sim accuracy, but I do like the waveforms > that I see. > > Setting abstol to 1 nA helps some too. I'm mostly dealing with amps.
I tend to prefer lower RELTOL and TRTOL to get smoother, more accurate waveforms. Especially important for difference calculations like efficiency. ABSTOL, CHGTOL and VOLTOL can all be increased until the waveforms visibly suffer, then backed off a few decades. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/
On Sat, 10 Feb 2018 07:13:18 -0600, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>"John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message >news:iees7dl11eb6comefdk8fqtet634rt9qa4@4ax.com... >> Setting reltol=0.002 and trtol=5 speeds things up a lot. I have no >> idea what that does to my sim accuracy, but I do like the waveforms >> that I see. >> >> Setting abstol to 1 nA helps some too. I'm mostly dealing with amps. > >I tend to prefer lower RELTOL and TRTOL to get smoother, more accurate >waveforms. Especially important for difference calculations like >efficiency. > >ABSTOL, CHGTOL and VOLTOL can all be increased until the waveforms visibly >suffer, then backed off a few decades. > >Tim
I have a few key voltages and timings. What I'm doing is loosening up the constraints until things start to change, then back off a step. What I have now is .opt reltol=0.002 .opt abstol=5n .opt trtol=5 which runs about 10x or so faster than the defaults, and keeps going, namely doesn't stall at random places. This is a fast kilovolt pulse generator so I don't care about picoamps. And I don't fully trust the device models anyhow. This is being regularly verified by breadboards, but the Spice looks pretty good. 10% sim accuracy would be good enough here. The initial DC solution is slow. Any suggestions on speeding that up? -- John Larkin Highland Technology, Inc lunatic fringe electronics
On 02/10/2018 11:14 AM, John Larkin wrote:
> On Sat, 10 Feb 2018 07:13:18 -0600, "Tim Williams" > <tiwill@seventransistorlabs.com> wrote: > >> "John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message >> news:iees7dl11eb6comefdk8fqtet634rt9qa4@4ax.com... >>> Setting reltol=0.002 and trtol=5 speeds things up a lot. I have no >>> idea what that does to my sim accuracy, but I do like the waveforms >>> that I see. >>> >>> Setting abstol to 1 nA helps some too. I'm mostly dealing with amps. >> >> I tend to prefer lower RELTOL and TRTOL to get smoother, more accurate >> waveforms. Especially important for difference calculations like >> efficiency. >> >> ABSTOL, CHGTOL and VOLTOL can all be increased until the waveforms visibly >> suffer, then backed off a few decades. >> >> Tim > > I have a few key voltages and timings. What I'm doing is loosening up > the constraints until things start to change, then back off a step. > What I have now is > > ..opt reltol=0.002 > > ..opt abstol=5n > > ..opt trtol=5 > > which runs about 10x or so faster than the defaults, and keeps going, > namely doesn't stall at random places. > > This is a fast kilovolt pulse generator so I don't care about > picoamps. And I don't fully trust the device models anyhow. This is > being regularly verified by breadboards, but the Spice looks pretty > good. 10% sim accuracy would be good enough here. > > The initial DC solution is slow. Any suggestions on speeding that up?
.savebias newbias.op internal ;.loadbias bias.op then after it finds itself once, copy newbias.op to bias.op and remove the semicolon. Repeat whenever you change the circuit enough that it doesn't find itself. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net https://hobbs-eo.com