How does a PLL work?

Started by September 25, 2017
```But I mean, really. The usually presented theory is crystal-clear:
There is a phase detector which produces voltage proportional to
phase difference of the input signals, which is then filtered and
feed back to a VCO and the loop is closed.

I am trying to implement a software PLL and my simulations show
the above is not true. For zero phase difference the phase error
voltage is also zero, so it would require a VCO/filter with
frequency. It can be done in digital, but in the case of any
analog VCO the control voltage *sets* the frequency, not *adjusts*
it by a given amount. Therefore such a PLL requires a non-zero
phase error to stay in lock, it is just "error-shaping" that
keeps both frequencies in sync. This is done by sub-cycle
inflation/deflation of the VCO waveform, i.e. by distorting
the VCO signal. The high-freq part then integrates out to 0
and the low-freq part is what keeps the loop in lock.

This is how a free-running 50Hz PLL with a multiplying detector
locks to 55Hz input (one second simulation):

https://s26.postimg.org/7jcgkmyg9/pll1.png

and several output cycles magnified:

https://s26.postimg.org/m6df2ax2h/pll2.png

Blue/orange is the quardrature VCO, green is the input,
red is the correcting voltage. The loop is in a perfect
lock, the red waveform is sufficiently below 0 in order
to make it happen, but the red oscillations is exactly
what makes it work and *should not* be excessively
filtered. This conclusion is again backed up by simulation:
for a given cutoff frequency increasing the filter order
makes the loop harder to stabilize and for a 3rd order
RC filter with 1.5Hz cutoff I am unable to adjust the
gain to make it lock. If the order increases, it must
be compensated by the increase of the cutoff frequency.

If I am right then why all the books I know simply lie? :-)

Best regards, Piotr
```
```On Monday, September 25, 2017 at 6:07:07 PM UTC+10, Piotr Wyderski wrote:
> But I mean, really. The usually presented theory is crystal-clear:
> There is a phase detector which produces voltage proportional to
> phase difference of the input signals, which is then filtered and
> feed back to a VCO and the loop is closed.
>
> I am trying to implement a software PLL and my simulations show
> the above is not true. For zero phase difference the phase error
> voltage is also zero, so it would require a VCO/filter with
> frequency.

<snip>

Floyd M. Gardener "Phaselock techniques" ISBN 0-471-04294-3

The low pass filter between the phase detector and the VCO has enough memory to do
the job. With a first order filter it's trivial to amke it work, but even a second
order filter adds enough extra phase lag around the feedback loop, when combined
with the fact that the VCO integrates the phase error, to create a stability
problem, as is discussed at some length by Floyd Gardner, along with the solutions.

--
Bill Sloman, Sydney
```
```Piotr Wyderski <peter.pan@neverland.mil> wrote:
> But I mean, really. The usually presented theory is crystal-clear:
> There is a phase detector which produces voltage proportional to
> phase difference of the input signals, which is then filtered and
> feed back to a VCO and the loop is closed.
>
> I am trying to implement a software PLL and my simulations show
> the above is not true. For zero phase difference the phase error
> voltage is also zero, so it would require a VCO/filter with
> frequency. It can be done in digital, but in the case of any
> analog VCO the control voltage *sets* the frequency, not *adjusts*
> it by a given amount. Therefore such a PLL requires a non-zero
> phase error to stay in lock, it is just "error-shaping" that
> keeps both frequencies in sync. This is done by sub-cycle
> inflation/deflation of the VCO waveform, i.e. by distorting
> the VCO signal. The high-freq part then integrates out to 0
> and the low-freq part is what keeps the loop in lock.
>
> This is how a free-running 50Hz PLL with a multiplying detector
> locks to 55Hz input (one second simulation):
>
> https://s26.postimg.org/7jcgkmyg9/pll1.png
>
> and several output cycles magnified:
>
> https://s26.postimg.org/m6df2ax2h/pll2.png
>
> Blue/orange is the quardrature VCO, green is the input,
> red is the correcting voltage. The loop is in a perfect
> lock, the red waveform is sufficiently below 0 in order
> to make it happen, but the red oscillations is exactly
> what makes it work and *should not* be excessively
> filtered. This conclusion is again backed up by simulation:
> for a given cutoff frequency increasing the filter order
> makes the loop harder to stabilize and for a 3rd order
> RC filter with 1.5Hz cutoff I am unable to adjust the
> gain to make it lock. If the order increases, it must
> be compensated by the increase of the cutoff frequency.
>
> If I am right then why all the books I know simply lie? :-)
>
> 	Best regards, Piotr

No it is correct, books that only write what you cite in the first
paragraph are merely explaining the general principle and do not
go down to the detail that you encounter when really implementing it.
That does not make them lying, they just aren't complete.

Check the theory of a PID loop as well.
```
```Piotr Wyderski <peter.pan@neverland.mil> wrote:

> But I mean, really. The usually presented theory is crystal-clear:
> There is a phase detector which produces voltage proportional to
> phase difference of the input signals, which is then filtered and
> feed back to a VCO and the loop is closed.

> I am trying to implement a software PLL and my simulations show
> the above is not true. For zero phase difference the phase error
> voltage is also zero, so it would require a VCO/filter with
> frequency. It can be done in digital, but in the case of any
> analog VCO the control voltage *sets* the frequency, not *adjusts*
> it by a given amount. Therefore such a PLL requires a non-zero
> phase error to stay in lock, it is just "error-shaping" that
> keeps both frequencies in sync. This is done by sub-cycle
> inflation/deflation of the VCO waveform, i.e. by distorting
> the VCO signal. The high-freq part then integrates out to 0
> and the low-freq part is what keeps the loop in lock.

> This is how a free-running 50Hz PLL with a multiplying detector
> locks to 55Hz input (one second simulation):

> https://s26.postimg.org/7jcgkmyg9/pll1.png

> and several output cycles magnified:

> https://s26.postimg.org/m6df2ax2h/pll2.png

> Blue/orange is the quardrature VCO, green is the input,
> red is the correcting voltage. The loop is in a perfect
> lock, the red waveform is sufficiently below 0 in order
> to make it happen, but the red oscillations is exactly
> what makes it work and *should not* be excessively
> filtered. This conclusion is again backed up by simulation:
> for a given cutoff frequency increasing the filter order
> makes the loop harder to stabilize and for a 3rd order
> RC filter with 1.5Hz cutoff I am unable to adjust the
> gain to make it lock. If the order increases, it must
> be compensated by the increase of the cutoff frequency.

> If I am right then why all the books I know simply lie? :-)

>      Best regards, Piotr

Quadrature phase detectors can lock at non-integer ratios. You need a
frequency-phase detector to lock on the fundamental.

```
```Rob wrote:

> No it is correct, books that only write what you cite in the first
> paragraph are merely explaining the general principle and do not
> go down to the detail that you encounter when really implementing it.

I don't want to sound pompous, but I dare to think that many/most of
the authors are just copy-pasting their predecessors and have no clue
what *really* happens under the hood. In the case of the multiplying
detector the second harmonic is not a nuisance, an artifact of basic
trigonometry, but actually the thing which makes it work.

> That does not make them lying, they just aren't complete.

Definitely a more diplomatic way to say that, but whatever you
call them, they are misleading to the point which renders the
implementation of a correctly locking loop impossible, if you
follow the book too closely. I've lost a day trying to figure
out why my "properly" designed loop goes mad, but manual tweaking
makes it super-stable.

> Check the theory of a PID loop as well.

I think I would need to go there some day, because in the digital
domain it seems to be much more natural to control the increments
instead of the magnitude of some variable.

Best regards, Piotr

```
```Steve Wilson wrote:

> Quadrature phase detectors can lock at non-integer ratios.

Isn't it just a matter of the pulling range, i.e. be a problem
only in the case of wideband loops? If the VCO bandwidth is narrow,
then it simply cannot reach the stable non-integer ratio.
In my case f_c+/-10% is perfectly fine, but the exact phase
tracking is the key figure.

> You need a frequency-phase detector to lock on the fundamental.

The ones I am aware of are edge-sensitive, so for a low-frequency
loop:

1. How would you get the input signal edge in the first place?
A comparator with a preset level? No, very amplitude-dependent.
Zero crossing detector? A tiny amount of noise will derail it.

2. There are too few edges per second at 50Hz, so the convergence
will be sloooow.

The multiplier is a real-time (approximate) phase detector, you
don't need to complete a full cycle to get meaningful results.
Do you know a practical PFD with comparably low latency?

Best regards, Piotr

```
```Piotr Wyderski <peter.pan@neverland.mil> wrote:
>> That does not make them lying, they just aren't complete.
>
> Definitely a more diplomatic way to say that, but whatever you
> call them, they are misleading to the point which renders the
> implementation of a correctly locking loop impossible, if you
> follow the book too closely. I've lost a day trying to figure
> out why my "properly" designed loop goes mad, but manual tweaking
> makes it super-stable.

Like you, I have experienced this myself when I built a frequency
synthesizer (VCO/divider/reference oscillator/phase detector) way
back in the seventies, and I thought I could reduce the spurs by
"improving" the loopfilter (relative to the example I found in a magazine).

Indeed, that did not work.
```
```Rob wrote:

> Indeed, that did not work.

Thanks a lot for your confirmation that I am on the correct track, Rob!

Best regards, Piotr

```
```Piotr Wyderski <peter.pan@neverland.mil> wrote:

> Steve Wilson wrote:

>> Quadrature phase detectors can lock at non-integer ratios.

> Isn't it just a matter of the pulling range, i.e. be a problem
> only in the case of wideband loops? If the VCO bandwidth is narrow,
> then it simply cannot reach the stable non-integer ratio.
> In my case f_c+/-10% is perfectly fine, but the exact phase
> tracking is the key figure.

PFD gives exact phase tracking with no non-integer lock ratios, locks only
to the fundamental.

>> You need a frequency-phase detector to lock on the fundamental.

> The ones I am aware of are edge-sensitive, so for a low-frequency
> loop:

> 1. How would you get the input signal edge in the first place?
> A comparator with a preset level? No, very amplitude-dependent.
> Zero crossing detector? A tiny amount of noise will derail it.

Zero cross. The loop filter will take care of the noise.

> 2. There are too few edges per second at 50Hz, so the convergence
> will be sloooow.

Depends on the loop bandwidth.

> The multiplier is a real-time (approximate) phase detector, you
> don't need to complete a full cycle to get meaningful results.
> Do you know a practical PFD with comparably low latency?

>      Best regards, Piotr

The results are not meaningful when the loop is out of lock. You are not
going to get meanginful results on a partial cycle.

You can start the vco in phase with the incoming signal. In either case,
XOR or PFD, the lock time depends on the loop bandwidth. You then set a
limit to the allowable phase error and wait until it gets there. If it's
not fast enough, increase the limit or the loop bandwidth. The latter will
increase the loop jitter.

```
```On 09/25/2017 04:07 AM, Piotr Wyderski wrote:
> But I mean, really. The usually presented theory is crystal-clear:
> There is a phase detector which produces voltage proportional to
> phase difference of the input signals, which is then filtered and
> feed back to a VCO and the loop is closed.

You're describing a _first_order_ PLL.  Those lock up in 1 cycle, on the
plus side, but on the minus side they have a lot of comparison frequency
ripple and exhibit a phase error proportional to the difference between
the reference frequency and the oscillator's free-running frequency.

But practically nobody uses those.

Normally you do one of two things: for low performance, use a
frequency/phase detector with a tri-state output, such as PD 2 of a
74HC4046, or use an op amp integrator with a lead-lag characteristic.

Your average op amp has a DC gain of 90-140 dB, so that the static phase
error goes away, at least down to the level set by the offset voltages
of the op amp and phase detector.

A PLL measures phase and sets frequency, so it's intrinsically
integrating.  That means that (without a loop filter) its open-loop
transfer function has one pole at zero, and -90 degree phase everywhere.

If you add another integrator, the phase is near -180 degrees, and the
loop will oscillate.  One simple way to frequency-compensate a PLL is,
first, to calculate the frequency where the two-integrator transfer
function crosses 0 dB:

w_0 = 2 pi f_0 = sqrt(K_vco K_phi/(RC)),

where K_vco is the VCO control gain in rad/s/V, K_phi is the phase
detector gain in V/rad, and RC is the time constant of the integrator
(i.e. R_in * C_f).

Then you put a resistor R_z in series with the feedback capacitor,
forming a time constant C_f * R_z = 1/w_0.

That'll give you about a 52 degree phase margin, which is a good
starting number.

>
> I am trying to implement a software PLL and my simulations show
> the above is not true. For zero phase difference the phase error
> voltage is also zero, so it would require a VCO/filter with
> frequency. It can be done in digital, but in the case of any
> analog VCO the control voltage *sets* the frequency, not *adjusts*
> it by a given amount. Therefore such a PLL requires a non-zero
> phase error to stay in lock, it is just "error-shaping" that
> keeps both frequencies in sync. This is done by sub-cycle
> inflation/deflation of the VCO waveform, i.e. by distorting
> the VCO signal. The high-freq part then integrates out to 0
> and the low-freq part is what keeps the loop in lock.
>
> This is how a free-running 50Hz PLL with a multiplying detector
> locks to 55Hz input (one second simulation):
>
> https://s26.postimg.org/7jcgkmyg9/pll1.png
>
> and several output cycles magnified:
>
> https://s26.postimg.org/m6df2ax2h/pll2.png
>
> Blue/orange is the quardrature VCO, green is the input,
> red is the correcting voltage. The loop is in a perfect
> lock, the red waveform is sufficiently below 0 in order
> to make it happen, but the red oscillations is exactly
> what makes it work and *should not* be excessively
> filtered. This conclusion is again backed up by simulation:
> for a given cutoff frequency increasing the filter order
> makes the loop harder to stabilize and for a 3rd order
> RC filter with 1.5Hz cutoff I am unable to adjust the
> gain to make it lock. If the order increases, it must
> be compensated by the increase of the cutoff frequency.
>
> If I am right then why all the books I know simply lie? :-)
>
> &nbsp;&nbsp;&nbsp;&nbsp;Best regards, Piotr

The math isn't difficult.  You'd probably like Floyd Gardner's classic
"Phaselock Techniques", which has all of that stuff, written by one of
the pioneers.  (I usually find that the best books are written by the
people who invented the technique, because in order to do that they had
to have a simple idea of it.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics