Improve PWM outputs with S/H?

Started by whit3rd September 13, 2017
A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for
1024 - N clock cycles.   That output pin, with some RC filtering, generates
about the same range and precision of voltages as a 10-bit DAC.   But, cheaper.

It also has ripple, because the filtered output ramps UP while the pin is high, and
DOWN
while low, dithering around the intended value, in addition to slowly
(exponentially)
decaying to a new average output value when a change is  made.

The RC time constant ought not to be made too long, or a change won't
propogate quickly, but cannot be made too short, or the ripple will grow
to be more than an LSB of the output.

If one were, however, to use an analog switch in a sample/hold amplifier,
taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value
would both ramp as quickly as the RC time (give or take half the PWM cycle
period), AND would be devoid of the triangle-wave-like ripple.

So, the idea is to change from one PWM output, to a PWM output and a
two-pulse strobe auxiliary output.   Then an external S/H amp can buffer
the PWM aerage value, while rejecting the PWM ripple (because the strobe
selects the centerpoints of rise and fall phases).

Does a cheap (?quad) S/H chip exist to support this?  Have any of the
usual controller chips ever had an output option like this?
On Wednesday, September 13, 2017 at 8:21:43 PM UTC+10, whit3rd wrote:
> A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for > 1024 - N clock cycles. That output pin, with some RC filtering, generates > about the same range and precision of voltages as a 10-bit DAC. But, cheaper.
It can make sense to switch the output more frequently. Sigma-delta modulation exploits this. A primitive version of this compares the desired output (a fixed 10-bit binary number) with a counter hooked up backwards, so the least significant bit of the counter (which is toggling more or less non-stop) is compared with the most significant bit of the fixed number. I thought this up around 1976, and got to use it around 1993. It's published here Sloman A.W., Buggs P., Molloy J., and Stewart D. “A microcontroller-based driver to stabilise the temperature of an optical stage to 1mK in the range 4C to 38C, using a Peltier heat pump and a thermistor sensor” Measurement Science and Technology, 7 1653-64 (1996) in section 2.6.
> It also has ripple, because the filtered output ramps UP while the pin is high,
and DOWN while low, dithering around the intended value, in addition to slowly (exponentially) decaying to a new average output value when a change is made.
> > The RC time constant ought not to be made too long, or a change won't > propagate quickly, but cannot be made too short, or the ripple will grow > to be more than an LSB of the output.
So use a multipole filter, set up for maximally rapid settling.
> If one were, however, to use an analog switch in a sample/hold amplifier, > taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value > would both ramp as quickly as the RC time (give or take half the PWM cycle > period), AND would be devoid of the triangle-wave-like ripple.
Perhaps.
> So, the idea is to change from one PWM output, to a PWM output and a > two-pulse strobe auxiliary output. Then an external S/H amp can buffer > the PWM aerage value, while rejecting the PWM ripple (because the strobe > selects the centerpoints of rise and fall phases). > > Does a cheap (?quad) S/H chip exist to support this? Have any of the > usual controller chips ever had an output option like this?
Never heard of one. Sigma-delta D/A converters are commercially available and have been for many years. No doubt somebody here will tell you what's currently favoured. Ten bits isn't exactly difficult. -- Bill Sloman, Sydney
On Wednesday, September 13, 2017 at 6:21:43 AM UTC-4, whit3rd wrote:
> A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for > 1024 - N clock cycles. That output pin, with some RC filtering, generates > about the same range and precision of voltages as a 10-bit DAC. But, cheaper. > > It also has ripple, because the filtered output ramps UP while the pin is high,
and DOWN
> while low, dithering around the intended value, in addition to slowly
(exponentially)
> decaying to a new average output value when a change is made. > > The RC time constant ought not to be made too long, or a change won't > propogate quickly, but cannot be made too short, or the ripple will grow > to be more than an LSB of the output. > > If one were, however, to use an analog switch in a sample/hold amplifier, > taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value > would both ramp as quickly as the RC time (give or take half the PWM cycle > period), AND would be devoid of the triangle-wave-like ripple. > > So, the idea is to change from one PWM output, to a PWM output and a > two-pulse strobe auxiliary output. Then an external S/H amp can buffer > the PWM aerage value, while rejecting the PWM ripple (because the strobe > selects the centerpoints of rise and fall phases). > > Does a cheap (?quad) S/H chip exist to support this? Have any of the > usual controller chips ever had an output option like this?
I don't know. How about some algorithm that doesn't just add or subtract bits from the end, but takes them out of the middle... in some judisious manner such that the short term average is about equal to the long term average. George H.
On Wednesday, September 13, 2017 at 12:21:43 PM UTC+2, whit3rd wrote:
> A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for > 1024 - N clock cycles. That output pin, with some RC filtering, generates > about the same range and precision of voltages as a 10-bit DAC. But, cheaper. > > It also has ripple, because the filtered output ramps UP while the pin is high,
and DOWN
> while low, dithering around the intended value, in addition to slowly
(exponentially)
> decaying to a new average output value when a change is made. > > The RC time constant ought not to be made too long, or a change won't > propogate quickly, but cannot be made too short, or the ripple will grow > to be more than an LSB of the output. > > If one were, however, to use an analog switch in a sample/hold amplifier, > taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value > would both ramp as quickly as the RC time (give or take half the PWM cycle > period), AND would be devoid of the triangle-wave-like ripple. > > So, the idea is to change from one PWM output, to a PWM output and a > two-pulse strobe auxiliary output. Then an external S/H amp can buffer > the PWM aerage value, while rejecting the PWM ripple (because the strobe > selects the centerpoints of rise and fall phases). > > Does a cheap (?quad) S/H chip exist to support this? Have any of the > usual controller chips ever had an output option like this?
The price for a S/H chip and amplifier would be a lot higher than a microcontroller with the needed DAC Cheers Klaus
On Wednesday, September 13, 2017 at 3:05:36 PM UTC+2, Klaus Kragelund wrote:
> On Wednesday, September 13, 2017 at 12:21:43 PM UTC+2, whit3rd wrote: > > A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for > > 1024 - N clock cycles. That output pin, with some RC filtering, generates > > about the same range and precision of voltages as a 10-bit DAC. But, cheaper. > > > > It also has ripple, because the filtered output ramps UP while the pin is high,
and DOWN
> > while low, dithering around the intended value, in addition to slowly
(exponentially)
> > decaying to a new average output value when a change is made. > > > > The RC time constant ought not to be made too long, or a change won't > > propogate quickly, but cannot be made too short, or the ripple will grow > > to be more than an LSB of the output. > > > > If one were, however, to use an analog switch in a sample/hold amplifier, > > taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value > > would both ramp as quickly as the RC time (give or take half the PWM cycle > > period), AND would be devoid of the triangle-wave-like ripple. > > > > So, the idea is to change from one PWM output, to a PWM output and a > > two-pulse strobe auxiliary output. Then an external S/H amp can buffer > > the PWM aerage value, while rejecting the PWM ripple (because the strobe > > selects the centerpoints of rise and fall phases). > > > > Does a cheap (?quad) S/H chip exist to support this? Have any of the > > usual controller chips ever had an output option like this? > > The price for a S/H chip and amplifier would be a lot higher than a
microcontroller with the needed DAC
> > Cheers > > Klaus
Also, for a PWM output the VDD ripple ruins the accuracy, so a 10bit DAC on a 3V supply would need to have a supply with quite accurate voltage void of supply load regulation effects Cheers Klaus
On 13/09/17 22:33, George Herold wrote:
> On Wednesday, September 13, 2017 at 6:21:43 AM UTC-4, whit3rd wrote: >> A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for >> 1024 - N clock cycles. That output pin, with some RC filtering, generates >> about the same range and precision of voltages as a 10-bit DAC. But, cheaper. >> >> It also has ripple, because the filtered output ramps UP while the pin is high,
and DOWN
>> while low, dithering around the intended value, in addition to slowly
(exponentially)
>> decaying to a new average output value when a change is made. >> >> The RC time constant ought not to be made too long, or a change won't >> propogate quickly, but cannot be made too short, or the ripple will grow >> to be more than an LSB of the output. >> >> If one were, however, to use an analog switch in a sample/hold amplifier, >> taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value >> would both ramp as quickly as the RC time (give or take half the PWM cycle >> period), AND would be devoid of the triangle-wave-like ripple. >> >> So, the idea is to change from one PWM output, to a PWM output and a >> two-pulse strobe auxiliary output. Then an external S/H amp can buffer >> the PWM aerage value, while rejecting the PWM ripple (because the strobe >> selects the centerpoints of rise and fall phases). >> >> Does a cheap (?quad) S/H chip exist to support this? Have any of the >> usual controller chips ever had an output option like this? > > I don't know. How about some algorithm that doesn't just add or > subtract bits from the end, but takes them out of the middle... > in some judisious manner such that the short term average is > about equal to the long term average.
Sigma-delta, in other words.
cycle
> >> period), AND would be devoid of the triangle-wave-like ripple.
i think you will find that adding poles (i.e. more RC sections) to your filter will be easier and more fruitful. m
On Wednesday, September 13, 2017 at 9:08:04 AM UTC-4, Clifford Heath wrote:
> On 13/09/17 22:33, George Herold wrote: > > On Wednesday, September 13, 2017 at 6:21:43 AM UTC-4, whit3rd wrote: > >> A simple timer can set a pin HIGH for N clock cycles out of 1024, then LOW for > >> 1024 - N clock cycles. That output pin, with some RC filtering, generates > >> about the same range and precision of voltages as a 10-bit DAC. But,
cheaper.
> >> > >> It also has ripple, because the filtered output ramps UP while the pin is high,
and DOWN
> >> while low, dithering around the intended value, in addition to slowly
(exponentially)
> >> decaying to a new average output value when a change is made. > >> > >> The RC time constant ought not to be made too long, or a change won't > >> propogate quickly, but cannot be made too short, or the ripple will grow > >> to be more than an LSB of the output. > >> > >> If one were, however, to use an analog switch in a sample/hold amplifier, > >> taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value > >> would both ramp as quickly as the RC time (give or take half the PWM cycle > >> period), AND would be devoid of the triangle-wave-like ripple. > >> > >> So, the idea is to change from one PWM output, to a PWM output and a > >> two-pulse strobe auxiliary output. Then an external S/H amp can buffer > >> the PWM aerage value, while rejecting the PWM ripple (because the strobe > >> selects the centerpoints of rise and fall phases). > >> > >> Does a cheap (?quad) S/H chip exist to support this? Have any of the > >> usual controller chips ever had an output option like this? > > > > I don't know. How about some algorithm that doesn't just add or > > subtract bits from the end, but takes them out of the middle... > > in some judisious manner such that the short term average is > > about equal to the long term average. > > Sigma-delta, in other words.
Maybe, I don't really know about sigma-delta (S-D) DAC's. (Reading in AoE... ) Well I was picturing something different, but maybe the output pulse stream is the same. If the output was (say) 3/4 full scale what would the S-D output stream look like. I'm seeing 3 high, 1 low, 3 high, 1 low...etc. George H.
On 13/09/2017 23:07, Clifford Heath wrote:
> On 13/09/17 22:33, George Herold wrote: >> On Wednesday, September 13, 2017 at 6:21:43 AM UTC-4, whit3rd wrote: >>> A simple timer can set a pin HIGH for N clock cycles out of 1024, >>> then LOW for >>> 1024 - N clock cycles.   That output pin, with some RC filtering, >>> generates >>> about the same range and precision of voltages as a 10-bit DAC. >>> But, cheaper. >>> >>> It also has ripple, because the filtered output ramps UP while the >>> pin is high, and DOWN >>> while low, dithering around the intended value, in addition to slowly >>> (exponentially) >>> decaying to a new average output value when a change is  made. >>> >>> The RC time constant ought not to be made too long, or a change won't >>> propogate quickly, but cannot be made too short, or the ripple will grow >>> to be more than an LSB of the output. >>> >>> If one were, however, to use an analog switch in a sample/hold >>> amplifier, >>> taking a sample at N/2 cycles and/or at N + (1024-N)/2, the hold value >>> would both ramp as quickly as the RC time (give or take half the PWM >>> cycle >>> period), AND would be devoid of the triangle-wave-like ripple. >>> >>> So, the idea is to change from one PWM output, to a PWM output and a >>> two-pulse strobe auxiliary output.   Then an external S/H amp can
buffer
>>> the PWM aerage value, while rejecting the PWM ripple (because the strobe >>> selects the centerpoints of rise and fall phases). >>> >>> Does a cheap (?quad) S/H chip exist to support this?  Have any of the >>> usual controller chips ever had an output option like this? >> >> I don't know.  How about some algorithm that doesn't just add or >> subtract bits from the end, but takes them out of the middle... >> in some judisious manner such that the short term average is >> about equal to the long term average. > > Sigma-delta, in other words. >
Or if a full sigma-delta is not worth the bother, just reverse the bits in the counter value (assuming it counts from 0 to (2^N)-1 ) before comparing with the duty cycle value, as Bill suggested. Bit-reversing in software is messy, so if I'm not short of memory then I pre-compute them and use a lookup table. When I am doing software PWM like that, usually it is to dither between two adjacent duty cycle values in a hardware PWM unit, because I ran out of resolution.
Il giorno mercoledì 13 settembre 2017 16:40:46 UTC+2, Chris Jones ha
scritto:

> comparing with the duty cycle value, as Bill suggested. Bit-reversing in > software is messy, so if I'm not short of memory then I pre-compute them > and use a lookup table.
http://graphics.stanford.edu/~seander/bithacks.html#BitReverseObvious Bye Jack