On Thu, 1 Jun 2017 15:55:24 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>Den fredag den 2. juni 2017 kl. 00.40.54 UTC+2 skrev k...@notreal.com: >> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: >> >> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: >> >> >> >> >Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: >> >> >> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: >> >> >>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund >> >> >>> <klauskvik@hotmail.com> wrote: >> >> >>> >> >> >>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... >> >> >>> >> >> >>> Huh? ARMs are flash rich and SRAM poor. If you want double the >> >> >>> performance, go to an M7. SRAM is expensive. >> >> >> >> >> >> yeh, afair from when I was involved with something similar, SRAM is something >> >> >> like 4x the die area and higher standby current than flash >> >> >> >> >> >> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash >> >> > >> >> >Is there any reason to argue the concept when the details can be viewed? >> >> >> >> You found details? >> >> >> >> >Er, ah, I can't seem to find any data sheets on their MCUs. The web site is >> >> >rather goofy. It has a selection guide, but once you locate a part number >> >> >there are no links to more info. I found a page with data sheets, but none >> >> >for the MCUs. Very strange. >> >> >> >> I didn't think so. The whole idea is goofy. >> > >> >why? >> >> 1. It's a kludge > >it's a solutionWithout a problem.> >> 2. SRAM is expensive/Flash is cheap > >assuming the process supports flashIt's an ARM, ferkrissakes! If you're stupid enough to design an ARM M-series on a process that doesn't support flash, revisit your business plan. ...or use an external flash, if you're stuck on stupid.>> 3. Faster uCs are available, if necessary > >there's always faster uCs availableCheap. M7s are twice the speed of M3s. (Not sure why M3s still exist).>> 4. Off-chip flash is trivial and incredibly cheap. > >stacking save a package, removes the need to support multiple types >and saves space on the boardNo, it certainly doesn't save anything. Kludges aren't free.> >> Bottom line: it's a solution looking for a problem. > >I've seen other IC go from extern to internal serial flash, if it >wasn't something that solves a problem why would they do it?Because they're stoopid? Are they really doing it or is it someone's wet dream?
Reliability of microcontroller silicon die glue on top of another die
Started by ●May 31, 2017
Reply by ●June 1, 20172017-06-01
Reply by ●June 1, 20172017-06-01
Datasheet: http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf Price = 0.3 USD in volume, at least 25% cheaper than the STM32 The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies Operation from SRAM draws less current Cheers Klaus
Reply by ●June 1, 20172017-06-01
Designers use Cortex M3 and M0 to reduce cost I really think people are stupid just to select a fast microcontroller when the application does not require so Cheers Klaus
Reply by ●June 1, 20172017-06-01
Klaus Kragelund wrote on 6/1/2017 7:47 PM:> Datasheet: > > http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdfWTF? You had to find the data sheet on a third party web site??? Ok, I dug a bit at gsense.com and it seems they are the parent company. How did you find the data sheet?> Price = 0.3 USD in volume, at least 25% cheaper than the STM32Where did you get a price?> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologiesHuh? Having two die is not so cheap. If two separate die are "always" better, why do they combine the Flash with CPU in most cases for chips in this range?> Operation from SRAM draws less currentI don't see that in the numbers in the data sheet. ~300 uA/MHz. -- Rick C
Reply by ●June 1, 20172017-06-01
>Designers use Cortex M3 and M0 to reduce cost>I really think people are stupid just to select a fast >microcontroller when the application does not require soAssuming that engineering cost and time to market aren't issue, that is. Cheers Phil Hobbs
Reply by ●June 1, 20172017-06-01
On Thu, 1 Jun 2017 17:09:20 -0700 (PDT), pcdhobbs@gmail.com wrote:>>Designers use Cortex M3 and M0 to reduce cost > >>I really think people are stupid just to select a fast >>microcontroller when the application does not require so > >Assuming that engineering cost and time to market aren't issue, that is. > >Cheers > >Phil HobbsAlways dumfounds me how some don't value their own time when making such a decision. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Thinking outside the box... producing elegant solutions. "It is not in doing what you like, but in liking what you do that is the secret of happiness." -James Barrie
Reply by ●June 1, 20172017-06-01
On Thu, 1 Jun 2017 16:51:25 -0700 (PDT), Klaus Kragelund <klauskvik@hotmail.com> wrote:>Designers use Cortex M3 and M0 to reduce cost > >I really think people are stupid just to select a fast microcontroller when the application does not require soSo if you've got nothing to do, just use an M0.
Reply by ●June 1, 20172017-06-01
On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund <klauskvik@hotmail.com> wrote:>Datasheet: > >http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >Price = 0.3 USD in volume, at least 25% cheaper than the STM32Where?> >The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologiesThat's certainly not true. If it were, there wouldn't be mixed technology chips.>Operation from SRAM draws less currentNot buying it, at least reads (operation). Note that both are zero wait-states so no advantage there.
Reply by ●June 1, 20172017-06-01
On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote:>On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund ><klauskvik@hotmail.com> wrote: > >>Datasheet: >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >Where? >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >That's certainly not true. If it were, there wouldn't be mixed >technology chips. > >>Operation from SRAM draws less current > >Not buying it, at least reads (operation). Note that both are zero >wait-states so no advantage there.BTW, the datasheet claims 3MB "on-chip" flash? That's not what we were discussing (and *really* hard to believe). I shoulda checked the date on the datasheet (4/1? ;).
Reply by ●June 2, 20172017-06-02
On Thursday, June 1, 2017 at 3:40:54 PM UTC-7, k...@notreal.com wrote:> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com:[about flash piggybacked on CPU die]> >> ... The whole idea is goofy. > > > >why? > > 1. It's a kludgeA 'kludge' like adding another level of cache? When the manufacturer does it for you, you TAKE it and enjoy. Intel's Pentiums got more useful when they went to the Pentium Pro and various other multichip modules.> 2. SRAM is expensive/Flash is cheapOnly in mass production. The flash requires more masks, and odd thin oxides with steps (for the floating gates) that can be omitted from a CPU. SRAM is identical to other CPU logic and registers, no extra masks or process steps. If you already have a FLASH production line, it makes sense to multipurpose its chip output for other products.> 3. Faster uCs are available, if necessary?so?> 4. Off-chip flash is trivial and incredibly cheap.But, if there's enough ON-chip flash, some customers will pay to avoid the 'extra part'. Low power dissipation in the flash chip makes it a reasonable packaging decision.> Bottom line: it's a solution looking for a problem.It's an affordable upgrade from a bare-bones CPU, and when a design gets to the find-more-resources stage, this can be an easy sale. It makes business sense. It makes extra-special sense when the unexpected problem arises. That's happened to me, once or twice.
