Hi I have been looking into the GigaDevice GD32 Cortex M3 microcontroller It has a REALLY nice price performance ratio So I dug a little deeper, and found that they do not integrate the flash and microcontroller on the same die as a normal microcontroller, but instead they use a single die variant of logic and core, and glues a serial flash on top of that Link to picture: https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices It's qoute ingenious, since then they can without changing the core die just change flash sizes by popping in a diffent flash die But, I am questioning the reliability of such a construction What happens at a lot of thermal cycles, does the glue give up and the bond wires likewise? GigaDevice has a thermal shock report that shows 0 defects after 500 cycles, which is the industry norm. I would however like to hear if any one here has experience with that kind of construction? My feeling is that it is ok because the thermal expansion coefficient of the 2 dies are the same, so the stress on the glue is low, but I am not an expert at all in die and glue technology Any insights group? Regards Klaus
Reliability of microcontroller silicon die glue on top of another die
Started by ●May 31, 2017
Reply by ●May 31, 20172017-05-31
On Wed, 31 May 2017 16:08:16 -0700 (PDT), klaus.kragelund@gmail.com wrote:>Hi > >I have been looking into the GigaDevice GD32 Cortex M3 microcontroller > >It has a REALLY nice price performance ratio > >So I dug a little deeper, and found that they do not integrate the flash and microcontroller on the same die as a normal microcontroller, but instead they use a single die variant of logic and core, and glues a serial flash on top of that > >Link to picture: > >https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices > > >It's qoute ingenious, since then they can without changing the core die just change flash sizes by popping in a diffent flash dieSeems rather dumb to me. What's the point? Serial flash is cheap. Just stick it on the board. The cost has to be horrendous.>But, I am questioning the reliability of such a construction > >What happens at a lot of thermal cycles, does the glue give up and the bond wires likewise? > >GigaDevice has a thermal shock report that shows 0 defects after 500 cycles, which is the industry norm. > >I would however like to hear if any one here has experience with that kind of construction? My feeling is that it is ok because the thermal expansion coefficient of the 2 dies are the same, so the stress on the glue is low, but I am not an expert at all in die and glue technologyStacked chips and MCMs are one thing but this looks like a real kludge with no great advantage.>Any insights group?BTW, why an M3? Is it really cheaper than an M4?
Reply by ●June 1, 20172017-06-01
Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3....
Reply by ●June 1, 20172017-06-01
On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund <klauskvik@hotmail.com> wrote:>Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3....Huh? ARMs are flash rich and SRAM poor. If you want double the performance, go to an M7. SRAM is expensive.
Reply by ●June 1, 20172017-06-01
Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com:> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund > <klauskvik@hotmail.com> wrote: > > >Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... > > Huh? ARMs are flash rich and SRAM poor. If you want double the > performance, go to an M7. SRAM is expensive.yeh, afair from when I was involved with something similar, SRAM is something like 4x the die area and higher standby current than flash the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash
Reply by ●June 1, 20172017-06-01
Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM:> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: >> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund >> <klauskvik@hotmail.com> wrote: >> >>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... >> >> Huh? ARMs are flash rich and SRAM poor. If you want double the >> performance, go to an M7. SRAM is expensive. > > yeh, afair from when I was involved with something similar, SRAM is something > like 4x the die area and higher standby current than flash > > the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flashIs there any reason to argue the concept when the details can be viewed? Er, ah, I can't seem to find any data sheets on their MCUs. The web site is rather goofy. It has a selection guide, but once you locate a part number there are no links to more info. I found a page with data sheets, but none for the MCUs. Very strange. -- Rick C
Reply by ●June 1, 20172017-06-01
On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote:>Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: >> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: >>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund >>> <klauskvik@hotmail.com> wrote: >>> >>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... >>> >>> Huh? ARMs are flash rich and SRAM poor. If you want double the >>> performance, go to an M7. SRAM is expensive. >> >> yeh, afair from when I was involved with something similar, SRAM is something >> like 4x the die area and higher standby current than flash >> >> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash > >Is there any reason to argue the concept when the details can be viewed?You found details?>Er, ah, I can't seem to find any data sheets on their MCUs. The web site is >rather goofy. It has a selection guide, but once you locate a part number >there are no links to more info. I found a page with data sheets, but none >for the MCUs. Very strange.I didn't think so. The whole idea is goofy.
Reply by ●June 1, 20172017-06-01
Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com:> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: > > >Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: > >> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: > >>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund > >>> <klauskvik@hotmail.com> wrote: > >>> > >>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... > >>> > >>> Huh? ARMs are flash rich and SRAM poor. If you want double the > >>> performance, go to an M7. SRAM is expensive. > >> > >> yeh, afair from when I was involved with something similar, SRAM is something > >> like 4x the die area and higher standby current than flash > >> > >> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash > > > >Is there any reason to argue the concept when the details can be viewed? > > You found details? > > >Er, ah, I can't seem to find any data sheets on their MCUs. The web site is > >rather goofy. It has a selection guide, but once you locate a part number > >there are no links to more info. I found a page with data sheets, but none > >for the MCUs. Very strange. > > I didn't think so. The whole idea is goofy.why?
Reply by ●June 1, 20172017-06-01
On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: >> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: >> >> >Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: >> >> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: >> >>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund >> >>> <klauskvik@hotmail.com> wrote: >> >>> >> >>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... >> >>> >> >>> Huh? ARMs are flash rich and SRAM poor. If you want double the >> >>> performance, go to an M7. SRAM is expensive. >> >> >> >> yeh, afair from when I was involved with something similar, SRAM is something >> >> like 4x the die area and higher standby current than flash >> >> >> >> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash >> > >> >Is there any reason to argue the concept when the details can be viewed? >> >> You found details? >> >> >Er, ah, I can't seem to find any data sheets on their MCUs. The web site is >> >rather goofy. It has a selection guide, but once you locate a part number >> >there are no links to more info. I found a page with data sheets, but none >> >for the MCUs. Very strange. >> >> I didn't think so. The whole idea is goofy. > >why?1. It's a kludge 2. SRAM is expensive/Flash is cheap 3. Faster uCs are available, if necessary 4. Off-chip flash is trivial and incredibly cheap. Bottom line: it's a solution looking for a problem.
Reply by ●June 1, 20172017-06-01
Den fredag den 2. juni 2017 kl. 00.40.54 UTC+2 skrev k...@notreal.com:> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: > >> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: > >> > >> >Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: > >> >> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: > >> >>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund > >> >>> <klauskvik@hotmail.com> wrote: > >> >>> > >> >>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... > >> >>> > >> >>> Huh? ARMs are flash rich and SRAM poor. If you want double the > >> >>> performance, go to an M7. SRAM is expensive. > >> >> > >> >> yeh, afair from when I was involved with something similar, SRAM is something > >> >> like 4x the die area and higher standby current than flash > >> >> > >> >> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash > >> > > >> >Is there any reason to argue the concept when the details can be viewed? > >> > >> You found details? > >> > >> >Er, ah, I can't seem to find any data sheets on their MCUs. The web site is > >> >rather goofy. It has a selection guide, but once you locate a part number > >> >there are no links to more info. I found a page with data sheets, but none > >> >for the MCUs. Very strange. > >> > >> I didn't think so. The whole idea is goofy. > > > >why? > > 1. It's a kludgeit's a solution> 2. SRAM is expensive/Flash is cheapassuming the process supports flash> 3. Faster uCs are available, if necessarythere's always faster uCs available> 4. Off-chip flash is trivial and incredibly cheap.stacking save a package, removes the need to support multiple types and saves space on the board> Bottom line: it's a solution looking for a problem.I've seen other IC go from extern to internal serial flash, if it wasn't something that solves a problem why would they do it?
