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OpAmp design - from theory to practice (Re-post)

Started by Francesco Zappon March 30, 2017
(Re-posted using a proper news provider, because i was told googlegroups 
is blocked by many on this list)

Hello everyone,

first post here. I hope I do not break any rule; let me know if this is 
the case.

Disclaimer: not native English speaker, forgive any mistake.

My background: master degree in physics (with a few courses in 
electronics). PhD in electronics/physics, doing 99% of digital design. 
My last encounter with analog design: 10 years ago (ie: my knowledge is 
a bit "rusty").

The problem: I work in high energy physics. Currently, my new project is 
to design a new version (in a new technology: from 250nm to 130nm) of a 
chip which has to perform current-to-frequency (CFC from now on) 
conversion. (for background information, if interested, you can read the 
previous designer work here: 
http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access).

Basically, I need to design a CFC with input currents ranging from 1nA 
to 1mA, with a 40 us integration window and low input leakage (target: 
100fA). Other details can be provided if needed.

The main problem is the design of the amplifier. I am studying the 
common designs and the usual architectures; BUT I have a difficult time 
in connecting the high-level specification of the device (CFC, min/max 
input current, etc..) with the low level specs of the amplifier (a fully 
differential OTA, if we keep the previous architecture) such as GBP, 
phase margin, slew rate, etc...

I understand that there is no such thing as a "magical" formula to 
design such circuits, but I assume that there must be, somewhere, a 
point from where to start, which is what I am missing here.

All the examples and designs I see (in tutorials or articles) start from 
the wanted specifications of the OpAmp, which would be good, if I had an 
idea on how to obtain them!

I hope that the question make sense to you.

Any help you can give is greatly appreciated!

thanks

Francesco
On Thursday, March 30, 2017 at 5:02:01 AM UTC-4, Francesco Zappon wrote:
> (Re-posted using a proper news provider, because i was told googlegroups > is blocked by many on this list) > > Hello everyone, > > first post here. I hope I do not break any rule; let me know if this is > the case. > > Disclaimer: not native English speaker, forgive any mistake. > > My background: master degree in physics (with a few courses in > electronics). PhD in electronics/physics, doing 99% of digital design. > My last encounter with analog design: 10 years ago (ie: my knowledge is > a bit "rusty"). > > The problem: I work in high energy physics. Currently, my new project is > to design a new version (in a new technology: from 250nm to 130nm) of a > chip which has to perform current-to-frequency (CFC from now on) > conversion. (for background information, if interested, you can read the > previous designer work here: > http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access). > > Basically, I need to design a CFC with input currents ranging from 1nA > to 1mA, with a 40 us integration window and low input leakage (target: > 100fA). Other details can be provided if needed. > > The main problem is the design of the amplifier. I am studying the > common designs and the usual architectures; BUT I have a difficult time > in connecting the high-level specification of the device (CFC, min/max > input current, etc..) with the low level specs of the amplifier (a fully > differential OTA, if we keep the previous architecture) such as GBP, > phase margin, slew rate, etc... > > I understand that there is no such thing as a "magical" formula to > design such circuits, but I assume that there must be, somewhere, a > point from where to start, which is what I am missing here. > > All the examples and designs I see (in tutorials or articles) start from > the wanted specifications of the OpAmp, which would be good, if I had an > idea on how to obtain them! > > I hope that the question make sense to you. > > Any help you can give is greatly appreciated! > > thanks > > Francesco
Hi Francesco, (I don't know much about ASIC design... though some here do that kind of thing and should be able to help.) It sounds like you have been thrown into the deep end, with some weights on your legs for good measure. Were you doing analog ASIC design 10 years ago or just discrete parts? Is there someone there helping you? I couldn't see your link, perhaps you can post the relevant parts (schematic and circuit description) in dropbox (or other service). Do you have a copy of Grey and Meyers, "Analysis and Design of Analog Integrated Circuits"? That's the only text I have that talks about such stuff. Good luck. George H.
On Thursday, 30 March 2017 15:02:03 UTC+2, George Herold  wrote:

> > Francesco > > Hi Francesco, (I don't know much about ASIC design... though some here do > that kind of thing and should be able to help.) > It sounds like you have been thrown into the deep end, with some weights on > your legs for good measure. Were you doing analog ASIC design 10 years ago > or just discrete parts? Is there someone there helping you?
Hi George! 10 years ago I was at the University doing my physics exams :) As a specialization I chose electronics; I did a few courses, but only 1 had elements of analog design at the transistor level; the others were more devoted to the "theory" of electronics (feedback, OpAmp as "black boxes" in various configuration, digital logic). I hope I will get some help from some colleagues, but for now I am on my own!
>I couldn't see your link, perhaps you can post the relevant parts (schematic > and circuit description) in >dropbox (or other service). Do you have a copy of Grey and Meyers, > "Analysis and Design of Analog Integrated Circuits"? That's the only text I > have that talks about such stuff.
I will see how to get the document in a public place. And yes, I have that book on my desk, I am in the initial stage of this project, so it looks like I will have to give it a good, long read! thanks for the support :) Francesco
On Thu, 30 Mar 2017 11:01:56 +0200, Francesco Zappon
<cescozep@gmail.com> wrote:

>(Re-posted using a proper news provider, because i was told googlegroups >is blocked by many on this list) > >Hello everyone, > >first post here. I hope I do not break any rule; let me know if this is >the case. > >Disclaimer: not native English speaker, forgive any mistake. > >My background: master degree in physics (with a few courses in >electronics). PhD in electronics/physics, doing 99% of digital design. >My last encounter with analog design: 10 years ago (ie: my knowledge is >a bit "rusty"). > >The problem: I work in high energy physics. Currently, my new project is >to design a new version (in a new technology: from 250nm to 130nm) of a >chip which has to perform current-to-frequency (CFC from now on) >conversion. (for background information, if interested, you can read the >previous designer work here: >http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access).
It would cost me $40 to see that.
> >Basically, I need to design a CFC with input currents ranging from 1nA >to 1mA, with a 40 us integration window and low input leakage (target: >100fA). Other details can be provided if needed.
How would that work, a current-to-frequency converter with a 40 us integration window? Can you sketch a timing diagram for how that would work? -- John Larkin Highland Technology, Inc lunatic fringe electronics
On 2017-03-30 17:27, John Larkin wrote:
> On Thu, 30 Mar 2017 11:01:56 +0200, Francesco Zappon > <cescozep@gmail.com> wrote: > >> (Re-posted using a proper news provider, because i was told googlegroups >> is blocked by many on this list) >> >> Hello everyone, >> >> first post here. I hope I do not break any rule; let me know if this is >> the case. >> >> Disclaimer: not native English speaker, forgive any mistake. >> >> My background: master degree in physics (with a few courses in >> electronics). PhD in electronics/physics, doing 99% of digital design. >> My last encounter with analog design: 10 years ago (ie: my knowledge is >> a bit "rusty"). >> >> The problem: I work in high energy physics. Currently, my new project is >> to design a new version (in a new technology: from 250nm to 130nm) of a >> chip which has to perform current-to-frequency (CFC from now on) >> conversion. (for background information, if interested, you can read the >> previous designer work here: >> http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access). > > It would cost me $40 to see that. >
Here is a preprint: <http://cds.cern.ch/record/1495072?ln=en> Jeroen Belleman