Forums

OpAmp design - from theory to practice

Started by Francesco Zappon March 29, 2017
Am 30.03.2017 um 16:16 schrieb Francesco Zappon:
> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann wrote:
> I will give a general answer valid also for the others that commented on radiation hardness: we are operating with a 7 TeV beam of protons (you might guess where I am working, at this point :D) and the radiation areas are *very* harsh. This is not a problem that can be solved just by shielding or some smart tricks (but we are diverging from my question). > > People way smarter than me tell me that no FPGA can withstand that kind of radiation for a reasonably long amount of time. > > The comment on the FPGA was just meant to say that I cannot mount in the proximity of the chip I am designing an FPGA to control it. Nothing more than that; you are right when you say that a CFC and an FPGA have nothing to do with each other :)
I assume then that you are abt. 2 or 3 hours by car from me in the south/western direction. Yes, if the FPGA gets warm from the radiation, that won't work. :-) But good enough for space probes or devices on the ISS. After all, there live some people. SEUs happen there, and it's bad if you lose the counter that has yourtime/position in orbit. But it surprised me that even robust things like voltage regulators are affected. cheers, Gerhard
On 30/03/2017 18:45, Joerg wrote:
> On 2017-03-29 07:55, Francesco Zappon wrote: >> Hello everyone, >> >> first post here. I hope I do not break any rule; let me know if this >> is the case. >> > > There are not many rules out here anymore :-) > > <ducking for cover now> > > >> Disclaimer: not native English speaker, forgive any mistake. >> > > Your English looks very good (I am non-native myself). > > >> My background: master degree in physics (with a few courses in >> electronics). PhD in electronics/physics, doing 99% of digital >> design. My last encounter with analog design: 10 years ago (ie: my >> knowledge is a bit "rusty"). >> >> The problem: I work in high energy physics. Currently, my new project >> is to design a new version (in a new technology: from 250nm to 130nm) > > > 130nm isn't considered very new these days but, of course, for radhard > your selection will be limited. New designs are still done in the larger > geometries. The most recent one I was involved in was 300nm. > > >> of a chip which has to perform current-to-frequency (CFC from now on) >> conversion. (for background information, if interested, you can read >> the previous designer work here: >> http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access). >> > > Do you have a link where this paper can be accessed without charge? From > non-subscribers they want about $40 just to take a look. > > >> Basically, I need to design a CFC with input currents ranging from >> 1nA to 1mA, with a 40 us integration window and low input leakage >> (target: 100fA). Other details can be provided if needed. >> >> The main problem is the design of the amplifier. I am studying the >> common designs and the usual architectures; BUT I have a difficult >> time in connecting the high-level specification of the device (CFC, >> min/max input current, etc..) with the low level specs of the >> amplifier (a fully differential OTA, if we keep the previous >> architecture) such as GBP, phase margin, slew rate, etc... >> > > 1nA gets you into noise floor issues with the first stage if the > integration window means >20kHz bandwidth. > > >> I understand that there is no such thing as a "magical" formula to >> design such circuits, but I assume that there must be, somewhere, a >> point from where to start, which is what I am missing here. >> >> All the examples and designs I see (in tutorials or articles) start >> from the wanted specifications of the OpAmp, which would be good, if >> I had an idea on how to obtain them! >> >> I hope that the question make sense to you. >> >> Any help you can give is greatly appreciated! >> > > Usually the first stage needed would be a transimpedance amplifier or > TIA, in other words a glorified current to voltage converter, followed > by a V/F conversion or another more modern method. Phil Hobbs here in > this group is the guru on low noise TIAs, maybe he could chime in. > > It might also help to talk to these guys: > > http://ams.aeroflex.com/pagesproduct/datasheets/MilAero_ASIC_Brochure.pdf >
https://www.dropbox.com/s/52nqfror1jhkqm0/venturini2013.pdf?dl=0
On Thursday, March 30, 2017 at 10:16:47 AM UTC-4, Francesco Zappon wrote:
> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann wrote: > > Am 30.03.2017 um 10:02 schrieb Francesco Zappon: > > [cut] > > > regards, Gerhard > > Hi Gerhard, > > thanks for the answer. > > I will give a general answer valid also for the others that commented on radiation hardness: we are operating with a 7 TeV beam of protons (you might guess where I am working, at this point :D) and the radiation areas are *very* harsh. This is not a problem that can be solved just by shielding or some smart tricks (but we are diverging from my question). > > People way smarter than me tell me that no FPGA can withstand that kind of radiation for a reasonably long amount of time. > > The comment on the FPGA was just meant to say that I cannot mount in the proximity of the chip I am designing an FPGA to control it. Nothing more than that; you are right when you say that a CFC and an FPGA have nothing to do with each other :) > > thanks > > Francesco
If you are at Cern, I would think there are many people there who know more about your problem, than we do here... where's Jeroen Belleman? George H.
On 03/30/2017 02:25 PM, Gerhard Hoffmann wrote:

> But it surprised me that even robust things like voltage > regulators are affected. > > cheers, Gerhard
The old triode pass tube -> error amplifier tube with neon lamp in the cathode makes a great rad-hard voltage regulator! Pummel it with gamma all day long, it don't care. Neon lamps are especially resilient. Little power-hungry, though.
On 2017-03-30 11:32, JM wrote:
> On 30/03/2017 18:45, Joerg wrote: >> On 2017-03-29 07:55, Francesco Zappon wrote: >>> Hello everyone, >>> >>> first post here. I hope I do not break any rule; let me know if this >>> is the case. >>> >> >> There are not many rules out here anymore :-) >> >> <ducking for cover now> >> >> >>> Disclaimer: not native English speaker, forgive any mistake. >>> >> >> Your English looks very good (I am non-native myself). >> >> >>> My background: master degree in physics (with a few courses in >>> electronics). PhD in electronics/physics, doing 99% of digital >>> design. My last encounter with analog design: 10 years ago (ie: my >>> knowledge is a bit "rusty"). >>> >>> The problem: I work in high energy physics. Currently, my new project >>> is to design a new version (in a new technology: from 250nm to 130nm) >> >> >> 130nm isn't considered very new these days but, of course, for radhard >> your selection will be limited. New designs are still done in the larger >> geometries. The most recent one I was involved in was 300nm. >> >> >>> of a chip which has to perform current-to-frequency (CFC from now on) >>> conversion. (for background information, if interested, you can read >>> the previous designer work here: >>> http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access). >>> >> >> Do you have a link where this paper can be accessed without charge? From >> non-subscribers they want about $40 just to take a look. >> >> >>> Basically, I need to design a CFC with input currents ranging from >>> 1nA to 1mA, with a 40 us integration window and low input leakage >>> (target: 100fA). Other details can be provided if needed. >>> >>> The main problem is the design of the amplifier. I am studying the >>> common designs and the usual architectures; BUT I have a difficult >>> time in connecting the high-level specification of the device (CFC, >>> min/max input current, etc..) with the low level specs of the >>> amplifier (a fully differential OTA, if we keep the previous >>> architecture) such as GBP, phase margin, slew rate, etc... >>> >> >> 1nA gets you into noise floor issues with the first stage if the >> integration window means >20kHz bandwidth. >> >> >>> I understand that there is no such thing as a "magical" formula to >>> design such circuits, but I assume that there must be, somewhere, a >>> point from where to start, which is what I am missing here. >>> >>> All the examples and designs I see (in tutorials or articles) start >>> from the wanted specifications of the OpAmp, which would be good, if >>> I had an idea on how to obtain them! >>> >>> I hope that the question make sense to you. >>> >>> Any help you can give is greatly appreciated! >>> >> >> Usually the first stage needed would be a transimpedance amplifier or >> TIA, in other words a glorified current to voltage converter, followed >> by a V/F conversion or another more modern method. Phil Hobbs here in >> this group is the guru on low noise TIAs, maybe he could chime in. >> >> It might also help to talk to these guys: >> >> http://ams.aeroflex.com/pagesproduct/datasheets/MilAero_ASIC_Brochure.pdf >> > > https://www.dropbox.com/s/52nqfror1jhkqm0/venturini2013.pdf?dl=0
Thanks! That helps a great deal. The SNR numbers in there do not look very stellar but they claim to have achieved all objectives stated (using sub-ranging though). Francesco, I am wondering what you'd like to improve above and beyond what these guys did? Is it the sub-ranging and subsequent SNR trade-off that you don't like? If you really want to use a I/F concept (which as others have hinted may not be the optimum here) there are V/F converters where the manufacturer claims 6 decades which corresponds to 120dB: http://www.ti.com/lit/ds/symlink/vfc320.pdf This would have to be preceded by a low noise TIA for a current to voltage conversion and those architectures are described in the field of pre-biased photodiodes. Like here: http://electrooptical.net/www/frontends/frontends.pdf -- Regards, Joerg http://www.analogconsultants.com/
On 2017-03-30 11:25, Gerhard Hoffmann wrote:
> Am 30.03.2017 um 16:16 schrieb Francesco Zappon: >> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann wrote: > >> I will give a general answer valid also for the others that commented >> on radiation hardness: we are operating with a 7 TeV beam of protons >> (you might guess where I am working, at this point :D) and the >> radiation areas are *very* harsh. This is not a problem that can be >> solved just by shielding or some smart tricks (but we are diverging >> from my question). >> >> People way smarter than me tell me that no FPGA can withstand that >> kind of radiation for a reasonably long amount of time. >> >> The comment on the FPGA was just meant to say that I cannot mount in >> the proximity of the chip I am designing an FPGA to control it. >> Nothing more than that; you are right when you say that a CFC and an >> FPGA have nothing to do with each other :) > > I assume then that you are abt. 2 or 3 hours by car from me in the > south/western direction. > > Yes, if the FPGA gets warm from the radiation, that won't work. :-) > But good enough for space probes or devices on the ISS. After all, > there live some people. SEUs happen there, and it's bad if you lose > the counter that has yourtime/position in orbit. > > But it surprised me that even robust things like voltage > regulators are affected. >
Even space-rated ones? http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slyt532d http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548 http://www.linear.com/parametric/Space_Qualified_Linear_Regulators http://www.linear.com/parametric/Space_Qualified_Switching_Regulators I found the old uA723 to be of cast-iron behavior in nasty environments but I don't know about its formal radiation tolerance. -- Regards, Joerg http://www.analogconsultants.com/
  
I'm not an IC designer, but I used to pal around with some. First you need to do the chip on a SOI process and not bulk. Second, use processes with wider features by preference. 

I-to-F is actually reasonably nice, since it uses time and frequency and is immune to voltage offsets. Much better than V-F. 

Cheers

Phil Hobbs
Am 30.03.2017 um 21:58 schrieb Joerg:
> On 2017-03-30 11:25, Gerhard Hoffmann wrote:
>> But it surprised me that even robust things like voltage >> regulators are affected. >> > > Even space-rated ones?
> ... > http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548 > ...
The documentation of the ST RHFL4913 & friends mentions exactly this, including the workaround with the large output capacitors. cheers, Gerhard
On Thursday, 30 March 2017 20:43:34 UTC+2, George Herold  wrote:

> > If you are at Cern, I would think there are many people there who know more > about your problem, than we do here... where's Jeroen Belleman?
You are right. Many experts around. Sadly, everyone is busy and I am not in direct contact with them on a daily basis, so it is difficult to get some collaboration going. But we are working on it :) Francesco
On Thursday, 30 March 2017 19:14:47 UTC+2, Tim Wescott  wrote:

Hi Tim,

> > If you have the bandwidth for the data, using a sigma-delta modulator on > the front end may work better -- just output raw or only lightly > processed bits from the 1-bit ADC, and do the actual processing somewhere > at a lower radiation level.
[cut]
> > I'm thinking like a system-level engineer, and part of that job entails > re-thinking previous assumptions. I'm always confused at this stage of a > project, or at least find myself faced with more choices than I'd prefer. > > Basically, at this stage, you do some feasibility studies of each > approach, and ask yourself which ones are better. Since you're doing an > upgrade of an existing system, you want to give a lot of weight to what's > already there.
thanks a lot for the tips!
> > And it sounds like you're a junior member of the team, so someone else > may have already thought of all of this and either determined from first > principles that the current approach is best, or they're married to it > and won't budge even if it's the worst. So at your level you may not get > to make the decision to change at all (but if you think some other > approach might be better you should prepare your mind to not be dismayed > by any answer, and then ask).
The choice of whether changing approach or not is also due to time constraints. But anyway, thanks for any suggestion so far! Francesco