Forums

Schmitt Trigger Jitter

Started by Tim Williams November 30, 2016
Interesting:

| Delay (us) | Jitter (ns pk)
|    5.7     |     460
|    2.92    |     170
|    1.45    |      26
|    0.72    |    < 10

Input is a linear capacitor charging slope.  Delay is the time taken from 
the reset voltage (about 0.5V) until crossing the input threshold.  Schmitt 
trigger is 74HC7014, a very handy little chip.

Actually, it's not little, they don't make a TSSOP.  But SOIC is good 
enough.

Anyway, the jitter seems to go up much faster than proportional.  Or, that 
it has a threshold.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com 

On Wed, 30 Nov 2016 13:33:02 -0600, Tim Williams wrote:

> Interesting: > > | Delay (us) | Jitter (ns pk) > | 5.7 | 460 | 2.92 | 170 | 1.45 | 26 | > 0.72 | < 10 > > Input is a linear capacitor charging slope. Delay is the time taken > from the reset voltage (about 0.5V) until crossing the input threshold. > Schmitt trigger is 74HC7014, a very handy little chip. > > Actually, it's not little, they don't make a TSSOP. But SOIC is good > enough. > > Anyway, the jitter seems to go up much faster than proportional. Or, > that it has a threshold. > > Tim
You're not giving us a schematic. I suspect that some of the source of jitter is more or less noise on the input side, which will cause jitter that is more or less proportional to the delay. I suspect that the rest of the jitter is more or less internal to the part, which will be more or less constant. All of the "more or less" waffling is because I've never tried to use one of these things where precision really matters. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
On Wed, 30 Nov 2016 13:33:02 -0600, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>Interesting: > >| Delay (us) | Jitter (ns pk) >| 5.7 | 460 >| 2.92 | 170 >| 1.45 | 26 >| 0.72 | < 10 > >Input is a linear capacitor charging slope. Delay is the time taken from >the reset voltage (about 0.5V) until crossing the input threshold. Schmitt >trigger is 74HC7014, a very handy little chip. > >Actually, it's not little, they don't make a TSSOP. But SOIC is good >enough. > >Anyway, the jitter seems to go up much faster than proportional. Or, that >it has a threshold. > >Tim
The 74HC014 creates hysteresis by switching in series and parallel devices to change thresholds. A "soft" transition slowly moves the threshold, thus the jitter. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website.
On Wed, 30 Nov 2016 13:33:02 -0600, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>Interesting: > >| Delay (us) | Jitter (ns pk) >| 5.7 | 460 >| 2.92 | 170 >| 1.45 | 26 >| 0.72 | < 10 > >Input is a linear capacitor charging slope. Delay is the time taken from >the reset voltage (about 0.5V) until crossing the input threshold. Schmitt >trigger is 74HC7014, a very handy little chip. > >Actually, it's not little, they don't make a TSSOP. But SOIC is good >enough. > >Anyway, the jitter seems to go up much faster than proportional. Or, that >it has a threshold. > >Tim
Schmitt gates are not precise, and threshold varies with temperature and Vcc. A tiny amount of induced 60 Hz or EMI will add jitter, especially if you have a small timing capacitor. Do your longer delays use smaller caps? Our ROT for RC-ramp (or current-source-C) delay generators is that RMS jitter is roughly 1/20000 of delay, using a real comparator. A clean fast edge run through a cmos or even ttl gate might have a few ps RMS jitter. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
"Tim Wescott" <seemywebsite@myfooter.really> wrote in message 
news:EeCdnfynQ_Ddt6LFnZ2dnUU7-cGdnZ2d@giganews.com...
> You're not giving us a schematic. I suspect that some of the source of > jitter is more or less noise on the input side, which will cause jitter > that is more or less proportional to the delay. I suspect that the rest > of the jitter is more or less internal to the part, which will be more or > less constant.
The schematic is as simple as I can describe -- a diode discharges a capacitor, then lets it charge (from a PNP CCS). Cap voltage goes to Schmitt trigger and that's that. So it delays the rising edge by I = C * dV/dt. The strange thing is it's not zero at zero. Plot the points -- the intercept is at 1.22us (delay), with a slope of 102 ns jitter per us of delay. I suppose I'd expect the "zero" to floor at the device's intrinsic jitter (which is probably <1ns, and I'm not really equipped to measure that), and have a sqrt(x^2 + y^2) curve between the two. That's fine. The odd bit is why the jitter grows so quickly. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in 
message news:38bu3c1eoa004ep6d46b92tvcuudmco523@4ax.com...
> The 74HC014 creates hysteresis by switching in series and parallel > devices to change thresholds. A "soft" transition slowly moves the > threshold, thus the jitter.
Sure, but why does that make it more prone to jitter? Because it's putting the input stage in the class A range, with very damn near zero offset (between input level and threshold, because the threshold is a sliding target), so the loop gain is very high, greatly amplifying internal noise? Then, could a very poor gate (poorly designed, or poorly constructed), and a sufficiently slow input transition, actually cause output bounce because the internal state is amplifying that noise? Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
"John Larkin" <jjlarkinxyxy@highlandtechnology.com> wrote in message 
news:bkcu3c98gn8lqp24d5chlqmc9mb2lnovn5@4ax.com...
> Schmitt gates are not precise, and threshold varies with temperature > and Vcc.
I was very particular to say 74HC7014, not 74HC14. Look it up!
> A tiny amount of induced 60 Hz or EMI will add jitter, > especially if you have a small timing capacitor. Do your longer delays > use smaller caps?
Good question. I didn't mention what was varying in the test. Same cap, different current. It's a 47pF cap, FWIW.
> Our ROT for RC-ramp (or current-source-C) delay generators is that RMS > jitter is roughly 1/20000 of delay, using a real comparator.
The '7014 is peculiar, so it's not clear to me whether it has a comparator structure or a more conventional CMOS Schmitt trigger structure (just cleaned up or compensated somehow to achieve the relatively precision threshold). It's definitely not a "real comparator", in the sense of one with 1000s of voltage gain, and GBW to spare, where you'll get a nice sharp ratio like that. I would expect jitter as a ratio of delay, but the offset is weird. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
On Wednesday, November 30, 2016 at 12:21:49 PM UTC-8, John Larkin wrote:
> On Wed, 30 Nov 2016 13:33:02 -0600, "Tim Williams" > <tiwill@seventransistorlabs.com> wrote:
[about CMOS schmitt jitter]
> >| Delay (us) | Jitter (ns pk) > >| 5.7 | 460 > >| 2.92 | 170 > >| 1.45 | 26 > >| 0.72 | < 10 > > > >Input is a linear capacitor charging slope. Delay is the time taken from > >the reset voltage (about 0.5V) until crossing the input threshold.
> >Anyway, the jitter seems to go up much faster than proportional. Or, that > >it has a threshold.
> Schmitt gates are not precise, and threshold varies with temperature > and Vcc.... > A clean fast edge run through a cmos or even ttl gate might have a few > ps RMS jitter.
At 'slow' slew rates on input, the Schmitt threshold is met when the transistors are only half-conducting. There's positive feedback, which is why the rise time on output is so good, but even positive feedback has some delay (internally), so it might be as simple as resistor noise in the near-threshold transistors. The output pins are buffered, so this high impedance isn't something you can probe. It might be possible, though, to quantify the jitter for a long sequence of transitions, and look for it to have Fourier components (from power supply) or be spectrally white (as resistor noise would suggest).
On Wed, 30 Nov 2016 15:52:14 -0600, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in >message news:38bu3c1eoa004ep6d46b92tvcuudmco523@4ax.com... >> The 74HC014 creates hysteresis by switching in series and parallel >> devices to change thresholds. A "soft" transition slowly moves the >> threshold, thus the jitter. > >Sure, but why does that make it more prone to jitter? Because it's putting >the input stage in the class A range, with very damn near zero offset >(between input level and threshold, because the threshold is a sliding >target), so the loop gain is very high, greatly amplifying internal noise? > >Then, could a very poor gate (poorly designed, or poorly constructed), and a >sufficiently slow input transition, actually cause output bounce because the >internal state is amplifying that noise? > >Tim
I have some device-level schematics, so, with a free moment I'll simulate it. My reflex response was based on the rounded "knee" that results during such a slow transition. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website.
On 11/30/2016 4:48 PM, Tim Williams wrote:
> "Tim Wescott" <seemywebsite@myfooter.really> wrote in message > news:EeCdnfynQ_Ddt6LFnZ2dnUU7-cGdnZ2d@giganews.com... >> You're not giving us a schematic. I suspect that some of the source of >> jitter is more or less noise on the input side, which will cause jitter >> that is more or less proportional to the delay. I suspect that the rest >> of the jitter is more or less internal to the part, which will be more or >> less constant. > > The schematic is as simple as I can describe -- a diode discharges a > capacitor, then lets it charge (from a PNP CCS). Cap voltage goes to > Schmitt trigger and that's that. So it delays the rising edge by I = C > * dV/dt. > > The strange thing is it's not zero at zero. Plot the points -- the > intercept is at 1.22us (delay), with a slope of 102 ns jitter per us of > delay. > > I suppose I'd expect the "zero" to floor at the device's intrinsic > jitter (which is probably <1ns, and I'm not really equipped to measure > that), and have a sqrt(x^2 + y^2) curve between the two. That's fine. > The odd bit is why the jitter grows so quickly.
Your writing is so terse I can barely understand what you are saying. "it's not zero at zero" means what? What is the first zero (or not zero) and what is the second? What are your X and Y? -- Rick C