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I2C bus needs capacitance?

Started by DemonicTubes October 5, 2016
I've got a couple boards that use this method to level shift:
http://imgur.com/a/yjD58

The I2C master is 3.3V while all the slaves are 5V devices.  This works fine, except on the newest board.  Only one of the (3 in this case) slaves respond.  Scoping the wave-forms and comparing with another board with the same circuit (different PCB layout, however) shows they are identical...until I noticed something odd:

With the scope probes attached the new board works fine!  Testing with a bare finger instead of probe yields about an 80% success rate.  The probe/finger must be at the node marked 'Master SDA', nowhere else has any effect.

I'm only running at 100kHz.  Can anybody enlighten me to what may be going on?  Do I really need to hang a cap off a serial data line??

Feels like I'm missing something obvious here...
In article <899648e9-969a-409a-88a3-c492e6d6da5d@googlegroups.com>,
DemonicTubes  <tlackie@gmail.com> wrote:
>I've got a couple boards that use this method to level shift: >http://imgur.com/a/yjD58 > >The I2C master is 3.3V while all the slaves are 5V devices. This works fine, except on the newest board. Only one of the >(3 in this case) slaves respond. Scoping the wave-forms and comparing with another board with the same circuit (different >PCB layout, however) shows they are identical...until I noticed something odd: > >With the scope probes attached the new board works fine! Testing with a bare finger instead of probe yields about an 80% >success rate. The probe/finger must be at the node marked 'Master SDA', nowhere else has any effect. > >I'm only running at 100kHz. Can anybody enlighten me to what may be going on? Do I really need to hang a cap off a serial >data line?? > >Feels like I'm missing something obvious here...
What's the rise/fall time of your signals like, when the master is driving them? Are your I2C lines terminated anywhere, or are they just traces/wires? If your master is hitting the lines with really fast edges, and if you don't have termination resistors installed at appropriate ppints, it's possible that the slave devices are seeing some ringing on the bus, and are mis-clocking.
On Wednesday, October 5, 2016 at 5:19:19 PM UTC-6, Dave Platt wrote:
 
> What's the rise/fall time of your signals like, when the master is > driving them? Are your I2C lines terminated anywhere, or are they > just traces/wires? > > If your master is hitting the lines with really fast edges, and if you > don't have termination resistors installed at appropriate ppints, it's > possible that the slave devices are seeing some ringing on the bus, > and are mis-clocking.
Thank you for your input, Dave. The only terminations are the 10K pullups on all lines as shown in my schematic. Early on I tried lowering them to 5K, no change. I didn't measure the slew rates, but will when I get back to the shop in the morning. They looked 'fast' to me. I wonder if I've inadvertently inverted my clock, so the added capacitance is slowing the data just enough that it is in the right state when the other (correct) clock edge arrives. Perhaps I got lucky with earlier boards having more built-in capacitance? I don't know, that just feels unlikely at 100kHz.
On Wed, 5 Oct 2016 14:18:08 -0700 (PDT), DemonicTubes
<tlackie@gmail.com> wrote:

>I've got a couple boards that use this method to level shift: >http://imgur.com/a/yjD58 > >The I2C master is 3.3V while all the slaves are 5V devices. This works fine, except on the newest board. Only one of the (3 in this case) slaves respond. Scoping the wave-forms and comparing with another board with the same circuit (different PCB layout, however) shows they are identical...until I noticed something odd: > >With the scope probes attached the new board works fine! Testing with a bare finger instead of probe yields about an 80% success rate. The probe/finger must be at the node marked 'Master SDA', nowhere else has any effect. > >I'm only running at 100kHz. Can anybody enlighten me to what may be going on? Do I really need to hang a cap off a serial data line?? > >Feels like I'm missing something obvious here...
Those 10K pullups are pretty wimpy. If the rising edges are slow, you could get clock/data skew. Try smaller resistors? -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Wed, 05 Oct 2016 14:18:08 -0700, DemonicTubes wrote:

> I've got a couple boards that use this method to level shift: > http://imgur.com/a/yjD58 > > The I2C master is 3.3V while all the slaves are 5V devices. This works > fine, except on the newest board. Only one of the (3 in this case) > slaves respond. Scoping the wave-forms and comparing with another board > with the same circuit (different PCB layout, however) shows they are > identical...until I noticed something odd: > > With the scope probes attached the new board works fine! Testing with a > bare finger instead of probe yields about an 80% success rate. The > probe/finger must be at the node marked 'Master SDA', nowhere else has > any effect. > > I'm only running at 100kHz. Can anybody enlighten me to what may be > going on? Do I really need to hang a cap off a serial data line?? > > Feels like I'm missing something obvious here...
Weird. Check the low voltage on the 3.3V side -- I expect it'll be one diode drop, courtesy of the bulk diode in the FET. The low may be marginal for your 3.3V device. NXP has level translators. I've only used them on one board, and it's still in the prototype stage, but I've had zero problems so far. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
On Wednesday, October 5, 2016 at 4:58:29 PM UTC-7, Tim Wescott wrote:
...
> > Weird. Check the low voltage on the 3.3V side -- I expect it'll be one > diode drop, courtesy of the bulk diode in the FET. The low may be > marginal for your 3.3V device. > > NXP has level translators. I've only used them on one board, and it's > still in the prototype stage, but I've had zero problems so far.
... It shouldn't be. The FET is biased on since there is 3.3V on the gate and so should have negligible D-S voltage. I've successfully used that circuit a few times with no problems. It has its limitations since there is only a passive pullup on the slave bus and yet the master has to provide the current for both pull-ups. I would think the most likely problem is that the setup or hold time is being violated. There are filters in the I2C slaves that should ignore ringing and other noise on the bus. kevin
On Wed, 5 Oct 2016 19:07:21 -0700 (PDT), kevin93 <kevin@whitedigs.com>
wrote:

>On Wednesday, October 5, 2016 at 4:58:29 PM UTC-7, Tim Wescott wrote: >... >> >> Weird. Check the low voltage on the 3.3V side -- I expect it'll be one >> diode drop, courtesy of the bulk diode in the FET. The low may be >> marginal for your 3.3V device. >> >> NXP has level translators. I've only used them on one board, and it's >> still in the prototype stage, but I've had zero problems so far. >... >It shouldn't be. The FET is biased on since there is 3.3V on the gate and so should have negligible D-S voltage. > >I've successfully used that circuit a few times with no problems. It has its limitations since there is only a passive pullup on the slave bus and yet the master has to provide the current for both pull-ups. > >I would think the most likely problem is that the setup or hold time is being violated.
Most likely, or the clock is ragged.
> >There are filters in the I2C slaves that should ignore ringing and other noise on the bus.
Believe that if you want to but you're just asking for trouble if the clock isn't perfect. Not everyone follows the spec. I2C can be major aggravation even if everything looks right. Hint: Put 0-ohm series resistors on every node (0404 2 x R-packs are great, here). When things get ugly, at least it's easy to isolate devices.
On 6.10.16 05:07, kevin93 wrote:
> On Wednesday, October 5, 2016 at 4:58:29 PM UTC-7, Tim Wescott wrote: > ... >> >> Weird. Check the low voltage on the 3.3V side -- I expect it'll be one >> diode drop, courtesy of the bulk diode in the FET. The low may be >> marginal for your 3.3V device. >> >> NXP has level translators. I've only used them on one board, and it's >> still in the prototype stage, but I've had zero problems so far. > ... > It shouldn't be. The FET is biased on since there is 3.3V on the gate and so should have negligible D-S voltage. > > I've successfully used that circuit a few times with no problems. It has its limitations since there is only a passive pullup on the slave bus and yet the master has to provide the current for both pull-ups. > > I would think the most likely problem is that the setup or hold time is being violated. > > There are filters in the I2C slaves that should ignore ringing and other noise on the bus. > > kevin
Does the level at master come out correct if the slave clamps the clock? -- -TV
Il giorno gioved&igrave; 6 ottobre 2016 01:58:29 UTC+2, Tim Wescott ha scritto:
> On Wed, 05 Oct 2016 14:18:08 -0700, DemonicTubes wrote: > > > I've got a couple boards that use this method to level shift: > > http://imgur.com/a/yjD58 > > > > The I2C master is 3.3V while all the slaves are 5V devices. This works > > fine, except on the newest board. Only one of the (3 in this case) > > slaves respond. Scoping the wave-forms and comparing with another board > > with the same circuit (different PCB layout, however) shows they are > > identical...until I noticed something odd: > > > > With the scope probes attached the new board works fine! Testing with a > > bare finger instead of probe yields about an 80% success rate. The > > probe/finger must be at the node marked 'Master SDA', nowhere else has > > any effect. > > > > I'm only running at 100kHz. Can anybody enlighten me to what may be > > going on? Do I really need to hang a cap off a serial data line?? > > > > Feels like I'm missing something obvious here... > > Weird. Check the low voltage on the 3.3V side -- I expect it'll be one > diode drop, courtesy of the bulk diode in the FET. The low may be > marginal for your 3.3V device. > > NXP has level translators. I've only used them on one board, and it's > still in the prototype stage, but I've had zero problems so far.
it also has this: http://www.nxp.com/documents/application_note/AN10441.pdf and it works very well. Bye Jack
On Thursday, October 6, 2016 at 12:37:22 AM UTC-7, Tauno Voipio wrote:
...
> > I've successfully used that circuit a few times with no problems. It has its limitations since there is only a passive pullup on the slave bus and yet the master has to provide the current for both pull-ups. > > > > I would think the most likely problem is that the setup or hold time is being violated. > > > > There are filters in the I2C slaves that should ignore ringing and other noise on the bus. > > > > kevin > > > Does the level at master come out correct if the slave clamps the clock? >
... Yes, that circuit supports clock stretching by the slave. The FET is operating in reverse in that case - the effective drain and source are swapped, but it will still work correctly. kevin