Forums

dumb triangle oscillator

Started by John Larkin February 19, 2016
I'm designing a test set for an energy digitizer/integrator box. It
has a 12-bit, 250 MHz ADC and an FPGA and stuff.

We want to make sure that every ADC bit works, and no data bits are
shorted to other bits on the PC board. So we'll apply a triangle wave
that's a bit bigger than the 0..+3 volt ADC range, randomly read
values, and run some sort of code to make sure every bit goes up and
down and also look for shorted bits somehow.

So, here's the triangle generator. R2 would probably be a pot, to set
the amplitude; the frequency doesn't matter much.

Sometimes you've just got to design dumb stuff.


Version 4
SHEET 1 952 680
WIRE 672 -208 608 -208
WIRE 784 -208 736 -208
WIRE 368 -176 336 -176
WIRE 400 -176 368 -176
WIRE 512 -176 464 -176
WIRE 528 -176 512 -176
WIRE 336 -128 336 -176
WIRE 464 -128 464 -176
WIRE 608 -112 608 -208
WIRE 656 -112 608 -112
WIRE 784 -112 784 -208
WIRE 784 -112 736 -112
WIRE 336 -16 336 -48
WIRE 464 -16 464 -48
WIRE 608 -16 608 -112
WIRE 640 -16 608 -16
WIRE 784 -16 784 -112
WIRE 784 -16 704 -16
WIRE 144 0 96 0
WIRE 288 0 224 0
WIRE 704 64 672 64
WIRE 672 80 672 64
WIRE 96 96 96 0
WIRE 128 96 96 96
WIRE 176 96 128 96
WIRE 288 96 288 0
WIRE 288 96 240 96
WIRE 336 96 288 96
WIRE 448 96 400 96
WIRE 608 96 608 -16
WIRE 608 96 528 96
WIRE 640 96 608 96
WIRE 96 112 96 96
WIRE 784 112 784 -16
WIRE 784 112 704 112
WIRE 832 112 784 112
WIRE 848 112 832 112
WIRE 640 128 608 128
WIRE 608 160 608 128
WIRE 672 176 672 144
WIRE 704 176 672 176
WIRE 96 192 96 176
FLAG 96 192 0
FLAG 832 112 out
FLAG 128 96 rc
FLAG 608 160 0
FLAG 336 -16 0
FLAG 464 -16 0
FLAG 368 -176 +5
FLAG 512 -176 -5
FLAG 704 64 +5
FLAG 704 176 -5
SYMBOL Digital\\schmtinv 176 32 R0
SYMATTR InstName A2
SYMATTR Value2 Vhigh=5 Vt=2.5 Vh=0.5
SYMATTR SpiceLine Td=5n
SYMBOL cap 80 112 R0
WINDOW 0 68 39 Left 2
WINDOW 3 63 73 Left 2
SYMATTR InstName C1
SYMATTR Value 20n
SYMBOL res 128 16 R270
WINDOW 0 74 58 VTop 2
WINDOW 3 67 58 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 400 80 R90
WINDOW 0 77 33 VBottom 2
WINDOW 3 86 31 VTop 2
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL res 544 80 R90
WINDOW 0 75 54 VBottom 2
WINDOW 3 87 54 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL Opamps\\UniversalOpamp2 672 112 R0
WINDOW 0 36 24 Left 2
SYMATTR InstName U1
SYMBOL cap 704 -32 R90
WINDOW 0 4 -8 VBottom 2
WINDOW 3 26 -12 VTop 2
SYMATTR InstName C3
SYMATTR Value 5n
SYMBOL res 752 -128 R90
WINDOW 0 -12 89 VBottom 2
WINDOW 3 -40 32 VTop 2
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL diode 672 -192 R270
WINDOW 0 47 -23 VTop 2
WINDOW 3 75 57 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL voltage 336 -144 R0
WINDOW 0 -77 37 Left 2
WINDOW 3 -71 69 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 464 -144 R0
WINDOW 0 50 37 Left 2
WINDOW 3 55 70 Left 2
SYMATTR InstName V2
SYMATTR Value -5
TEXT -192 152 Left 2 !.tran 0 10m 0 20n
TEXT -248 -88 Left 2 ;NC7S14  Hyst~~1V at Vcc=5
TEXT -256 -128 Left 2 ;ADC Test Triangle Generator
TEXT -184 -48 Left 2 ;period ~~ 0.81 RC
TEXT -152 -8 Left 2 ;F ~~ 7 KHz
TEXT -208 64 Left 2 ;J Larkin  Feb 19, 2016

-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

Den l�rdag den 20. februar 2016 kl. 00.53.41 UTC+1 skrev John Larkin:
> I'm designing a test set for an energy digitizer/integrator box. It > has a 12-bit, 250 MHz ADC and an FPGA and stuff. > > We want to make sure that every ADC bit works, and no data bits are > shorted to other bits on the PC board. So we'll apply a triangle wave > that's a bit bigger than the 0..+3 volt ADC range, randomly read > values, and run some sort of code to make sure every bit goes up and > down and also look for shorted bits somehow. > > So, here's the triangle generator. R2 would probably be a pot, to set > the amplitude; the frequency doesn't matter much. > > Sometimes you've just got to design dumb stuff. >
RC and a pin on the fpga -Lasse
On Fri, 19 Feb 2016 16:05:23 -0800 (PST), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>Den l&#2013266168;rdag den 20. februar 2016 kl. 00.53.41 UTC+1 skrev John Larkin: >> I'm designing a test set for an energy digitizer/integrator box. It >> has a 12-bit, 250 MHz ADC and an FPGA and stuff. >> >> We want to make sure that every ADC bit works, and no data bits are >> shorted to other bits on the PC board. So we'll apply a triangle wave >> that's a bit bigger than the 0..+3 volt ADC range, randomly read >> values, and run some sort of code to make sure every bit goes up and >> down and also look for shorted bits somehow. >> >> So, here's the triangle generator. R2 would probably be a pot, to set >> the amplitude; the frequency doesn't matter much. >> >> Sometimes you've just got to design dumb stuff. >> > >RC and a pin on the fpga > >-Lasse
The test set is separate from the DUT (where the ADC is) and the test set won't have an FPGA. I guess a rounded RC sort of thing would be as statistically good as a real triangle, but I need an opamp to drive the load anyhow, so I may as well integrate to a clean triangle. It will look nicer, too. We could compute the duty cycle of each ADC bit, which might be interesting. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Den l&#2013266168;rdag den 20. februar 2016 kl. 01.22.20 UTC+1 skrev John Larkin:
> On Fri, 19 Feb 2016 16:05:23 -0800 (PST), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >Den l&#2013266168;rdag den 20. februar 2016 kl. 00.53.41 UTC+1 skrev John Larkin: > >> I'm designing a test set for an energy digitizer/integrator box. It > >> has a 12-bit, 250 MHz ADC and an FPGA and stuff. > >> > >> We want to make sure that every ADC bit works, and no data bits are > >> shorted to other bits on the PC board. So we'll apply a triangle wave > >> that's a bit bigger than the 0..+3 volt ADC range, randomly read > >> values, and run some sort of code to make sure every bit goes up and > >> down and also look for shorted bits somehow. > >> > >> So, here's the triangle generator. R2 would probably be a pot, to set > >> the amplitude; the frequency doesn't matter much. > >> > >> Sometimes you've just got to design dumb stuff. > >> > > > >RC and a pin on the fpga > > > >-Lasse > > The test set is separate from the DUT (where the ADC is) and the test > set won't have an FPGA.
if the box have any digital output the could be used as a self test
> > I guess a rounded RC sort of thing would be as statistically good as a > real triangle, but I need an opamp to drive the load anyhow, so I may > as well integrate to a clean triangle. It will look nicer, too. > > We could compute the duty cycle of each ADC bit, which might be > interesting. >
noise should work too, just do a histogram and check if all 2^12 values have been hit -Lasse
On Fri, 19 Feb 2016 16:34:30 -0800 (PST), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>Den l&#2013266168;rdag den 20. februar 2016 kl. 01.22.20 UTC+1 skrev John Larkin: >> On Fri, 19 Feb 2016 16:05:23 -0800 (PST), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >Den l&#2013266168;rdag den 20. februar 2016 kl. 00.53.41 UTC+1 skrev John Larkin: >> >> I'm designing a test set for an energy digitizer/integrator box. It >> >> has a 12-bit, 250 MHz ADC and an FPGA and stuff. >> >> >> >> We want to make sure that every ADC bit works, and no data bits are >> >> shorted to other bits on the PC board. So we'll apply a triangle wave >> >> that's a bit bigger than the 0..+3 volt ADC range, randomly read >> >> values, and run some sort of code to make sure every bit goes up and >> >> down and also look for shorted bits somehow. >> >> >> >> So, here's the triangle generator. R2 would probably be a pot, to set >> >> the amplitude; the frequency doesn't matter much. >> >> >> >> Sometimes you've just got to design dumb stuff. >> >> >> > >> >RC and a pin on the fpga >> > >> >-Lasse >> >> The test set is separate from the DUT (where the ADC is) and the test >> set won't have an FPGA. > >if the box have any digital output the could be used as a self test > >> >> I guess a rounded RC sort of thing would be as statistically good as a >> real triangle, but I need an opamp to drive the load anyhow, so I may >> as well integrate to a clean triangle. It will look nicer, too. >> >> We could compute the duty cycle of each ADC bit, which might be >> interesting. >> > >noise should work too, just do a histogram and check if all 2^12 values have >been hit > >-Lasse
I guess one would have to mash a lot of samples to get a good 4K-point histogram. What with the test PC and our indirect access path to the device, we can't get a lot of samples per second, less than 1K maybe in test mode. With a small stored sample set, 1K 12-bit samples maybe, we should be able to compute a decent duty cycle on each bit. Some other algorithm on that same sample set should be able to find shorted bits... somehow... Shorted bit traces (it's LVDS from ADC to FPGA) will probably wreck the bit duty cycles. But other checks should be possible. Given the 1K sample set, the PC can do a lot of math in a reasonable time. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Friday, February 19, 2016 at 6:53:41 PM UTC-5, John Larkin wrote:
> I'm designing a test set for an energy digitizer/integrator box. It > has a 12-bit, 250 MHz ADC and an FPGA and stuff. > > We want to make sure that every ADC bit works, and no data bits are > shorted to other bits on the PC board. So we'll apply a triangle wave > that's a bit bigger than the 0..+3 volt ADC range, randomly read > values, and run some sort of code to make sure every bit goes up and > down and also look for shorted bits somehow. > > So, here's the triangle generator. R2 would probably be a pot, to set > the amplitude; the frequency doesn't matter much. > > Sometimes you've just got to design dumb stuff. > > > Version 4 > SHEET 1 952 680 > WIRE 672 -208 608 -208 > WIRE 784 -208 736 -208 > WIRE 368 -176 336 -176 > WIRE 400 -176 368 -176 > WIRE 512 -176 464 -176 > WIRE 528 -176 512 -176 > WIRE 336 -128 336 -176 > WIRE 464 -128 464 -176 > WIRE 608 -112 608 -208 > WIRE 656 -112 608 -112 > WIRE 784 -112 784 -208 > WIRE 784 -112 736 -112 > WIRE 336 -16 336 -48 > WIRE 464 -16 464 -48 > WIRE 608 -16 608 -112 > WIRE 640 -16 608 -16 > WIRE 784 -16 784 -112 > WIRE 784 -16 704 -16 > WIRE 144 0 96 0 > WIRE 288 0 224 0 > WIRE 704 64 672 64 > WIRE 672 80 672 64 > WIRE 96 96 96 0 > WIRE 128 96 96 96 > WIRE 176 96 128 96 > WIRE 288 96 288 0 > WIRE 288 96 240 96 > WIRE 336 96 288 96 > WIRE 448 96 400 96 > WIRE 608 96 608 -16 > WIRE 608 96 528 96 > WIRE 640 96 608 96 > WIRE 96 112 96 96 > WIRE 784 112 784 -16 > WIRE 784 112 704 112 > WIRE 832 112 784 112 > WIRE 848 112 832 112 > WIRE 640 128 608 128 > WIRE 608 160 608 128 > WIRE 672 176 672 144 > WIRE 704 176 672 176 > WIRE 96 192 96 176 > FLAG 96 192 0 > FLAG 832 112 out > FLAG 128 96 rc > FLAG 608 160 0 > FLAG 336 -16 0 > FLAG 464 -16 0 > FLAG 368 -176 +5 > FLAG 512 -176 -5 > FLAG 704 64 +5 > FLAG 704 176 -5 > SYMBOL Digital\\schmtinv 176 32 R0 > SYMATTR InstName A2 > SYMATTR Value2 Vhigh=5 Vt=2.5 Vh=0.5 > SYMATTR SpiceLine Td=5n > SYMBOL cap 80 112 R0 > WINDOW 0 68 39 Left 2 > WINDOW 3 63 73 Left 2 > SYMATTR InstName C1 > SYMATTR Value 20n > SYMBOL res 128 16 R270 > WINDOW 0 74 58 VTop 2 > WINDOW 3 67 58 VBottom 2 > SYMATTR InstName R1 > SYMATTR Value 10k > SYMBOL cap 400 80 R90 > WINDOW 0 77 33 VBottom 2 > WINDOW 3 86 31 VTop 2 > SYMATTR InstName C2 > SYMATTR Value 100n > SYMBOL res 544 80 R90 > WINDOW 0 75 54 VBottom 2 > WINDOW 3 87 54 VTop 2 > SYMATTR InstName R2 > SYMATTR Value 10K > SYMBOL Opamps\\UniversalOpamp2 672 112 R0 > WINDOW 0 36 24 Left 2 > SYMATTR InstName U1 > SYMBOL cap 704 -32 R90 > WINDOW 0 4 -8 VBottom 2 > WINDOW 3 26 -12 VTop 2 > SYMATTR InstName C3 > SYMATTR Value 5n > SYMBOL res 752 -128 R90 > WINDOW 0 -12 89 VBottom 2 > WINDOW 3 -40 32 VTop 2 > SYMATTR InstName R3 > SYMATTR Value 1Meg > SYMBOL diode 672 -192 R270 > WINDOW 0 47 -23 VTop 2 > WINDOW 3 75 57 VBottom 2 > SYMATTR InstName D1 > SYMATTR Value 1N4148 > SYMBOL voltage 336 -144 R0 > WINDOW 0 -77 37 Left 2 > WINDOW 3 -71 69 Left 2 > SYMATTR InstName V1 > SYMATTR Value 5 > SYMBOL voltage 464 -144 R0 > WINDOW 0 50 37 Left 2 > WINDOW 3 55 70 Left 2 > SYMATTR InstName V2 > SYMATTR Value -5 > TEXT -192 152 Left 2 !.tran 0 10m 0 20n > TEXT -248 -88 Left 2 ;NC7S14 Hyst~~1V at Vcc=5 > TEXT -256 -128 Left 2 ;ADC Test Triangle Generator > TEXT -184 -48 Left 2 ;period ~~ 0.81 RC > TEXT -152 -8 Left 2 ;F ~~ 7 KHz > TEXT -208 64 Left 2 ;J Larkin Feb 19, 2016 > > -- > > John Larkin Highland Technology, Inc > picosecond timing precision measurement > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.com
Dumb is good word for it. What's your problem you can't use the time tested technique of dual amp, integrator + comparator, switching at and slewing between two precision thresholds?
On Sat, 20 Feb 2016 07:48:51 -0800 (PST),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Friday, February 19, 2016 at 6:53:41 PM UTC-5, John Larkin wrote: >> I'm designing a test set for an energy digitizer/integrator box. It >> has a 12-bit, 250 MHz ADC and an FPGA and stuff. >> >> We want to make sure that every ADC bit works, and no data bits are >> shorted to other bits on the PC board. So we'll apply a triangle wave >> that's a bit bigger than the 0..+3 volt ADC range, randomly read >> values, and run some sort of code to make sure every bit goes up and >> down and also look for shorted bits somehow. >> >> So, here's the triangle generator. R2 would probably be a pot, to set >> the amplitude; the frequency doesn't matter much. >> >> Sometimes you've just got to design dumb stuff. >> >> >> Version 4 >> SHEET 1 952 680 >> WIRE 672 -208 608 -208 >> WIRE 784 -208 736 -208 >> WIRE 368 -176 336 -176 >> WIRE 400 -176 368 -176 >> WIRE 512 -176 464 -176 >> WIRE 528 -176 512 -176 >> WIRE 336 -128 336 -176 >> WIRE 464 -128 464 -176 >> WIRE 608 -112 608 -208 >> WIRE 656 -112 608 -112 >> WIRE 784 -112 784 -208 >> WIRE 784 -112 736 -112 >> WIRE 336 -16 336 -48 >> WIRE 464 -16 464 -48 >> WIRE 608 -16 608 -112 >> WIRE 640 -16 608 -16 >> WIRE 784 -16 784 -112 >> WIRE 784 -16 704 -16 >> WIRE 144 0 96 0 >> WIRE 288 0 224 0 >> WIRE 704 64 672 64 >> WIRE 672 80 672 64 >> WIRE 96 96 96 0 >> WIRE 128 96 96 96 >> WIRE 176 96 128 96 >> WIRE 288 96 288 0 >> WIRE 288 96 240 96 >> WIRE 336 96 288 96 >> WIRE 448 96 400 96 >> WIRE 608 96 608 -16 >> WIRE 608 96 528 96 >> WIRE 640 96 608 96 >> WIRE 96 112 96 96 >> WIRE 784 112 784 -16 >> WIRE 784 112 704 112 >> WIRE 832 112 784 112 >> WIRE 848 112 832 112 >> WIRE 640 128 608 128 >> WIRE 608 160 608 128 >> WIRE 672 176 672 144 >> WIRE 704 176 672 176 >> WIRE 96 192 96 176 >> FLAG 96 192 0 >> FLAG 832 112 out >> FLAG 128 96 rc >> FLAG 608 160 0 >> FLAG 336 -16 0 >> FLAG 464 -16 0 >> FLAG 368 -176 +5 >> FLAG 512 -176 -5 >> FLAG 704 64 +5 >> FLAG 704 176 -5 >> SYMBOL Digital\\schmtinv 176 32 R0 >> SYMATTR InstName A2 >> SYMATTR Value2 Vhigh=5 Vt=2.5 Vh=0.5 >> SYMATTR SpiceLine Td=5n >> SYMBOL cap 80 112 R0 >> WINDOW 0 68 39 Left 2 >> WINDOW 3 63 73 Left 2 >> SYMATTR InstName C1 >> SYMATTR Value 20n >> SYMBOL res 128 16 R270 >> WINDOW 0 74 58 VTop 2 >> WINDOW 3 67 58 VBottom 2 >> SYMATTR InstName R1 >> SYMATTR Value 10k >> SYMBOL cap 400 80 R90 >> WINDOW 0 77 33 VBottom 2 >> WINDOW 3 86 31 VTop 2 >> SYMATTR InstName C2 >> SYMATTR Value 100n >> SYMBOL res 544 80 R90 >> WINDOW 0 75 54 VBottom 2 >> WINDOW 3 87 54 VTop 2 >> SYMATTR InstName R2 >> SYMATTR Value 10K >> SYMBOL Opamps\\UniversalOpamp2 672 112 R0 >> WINDOW 0 36 24 Left 2 >> SYMATTR InstName U1 >> SYMBOL cap 704 -32 R90 >> WINDOW 0 4 -8 VBottom 2 >> WINDOW 3 26 -12 VTop 2 >> SYMATTR InstName C3 >> SYMATTR Value 5n >> SYMBOL res 752 -128 R90 >> WINDOW 0 -12 89 VBottom 2 >> WINDOW 3 -40 32 VTop 2 >> SYMATTR InstName R3 >> SYMATTR Value 1Meg >> SYMBOL diode 672 -192 R270 >> WINDOW 0 47 -23 VTop 2 >> WINDOW 3 75 57 VBottom 2 >> SYMATTR InstName D1 >> SYMATTR Value 1N4148 >> SYMBOL voltage 336 -144 R0 >> WINDOW 0 -77 37 Left 2 >> WINDOW 3 -71 69 Left 2 >> SYMATTR InstName V1 >> SYMATTR Value 5 >> SYMBOL voltage 464 -144 R0 >> WINDOW 0 50 37 Left 2 >> WINDOW 3 55 70 Left 2 >> SYMATTR InstName V2 >> SYMATTR Value -5 >> TEXT -192 152 Left 2 !.tran 0 10m 0 20n >> TEXT -248 -88 Left 2 ;NC7S14 Hyst~~1V at Vcc=5 >> TEXT -256 -128 Left 2 ;ADC Test Triangle Generator >> TEXT -184 -48 Left 2 ;period ~~ 0.81 RC >> TEXT -152 -8 Left 2 ;F ~~ 7 KHz >> TEXT -208 64 Left 2 ;J Larkin Feb 19, 2016 >> >> -- >> >> John Larkin Highland Technology, Inc >> picosecond timing precision measurement >> >> jlarkin att highlandtechnology dott com >> http://www.highlandtechnology.com > >Dumb is good word for it.
Gosh, you must have a lot of friends.
>What's your problem you can't use the time tested technique of dual amp, integrator + comparator, switching at and slewing between two precision thresholds?
Partly, I don't need all that. I could do that, but it's just a little more work. It's also a matter of what parts we have in stock. If I had a 4000-series d-flop, I could use that and an LM393, running off +-6V, and it wouldn't be bad. The triangle isn't especially interesting. What is more interesting is the algorithm that will look at the 12-bit samples, 1000 or so, and spot bit failures. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On Saturday, February 20, 2016 at 11:48:53 AM UTC-5, John Larkin wrote:
> On Sat, 20 Feb 2016 07:48:51 -0800 (PST), > bloggs.fredbloggs.fred@gmail.com wrote: > > >On Friday, February 19, 2016 at 6:53:41 PM UTC-5, John Larkin wrote: > >> I'm designing a test set for an energy digitizer/integrator box. It > >> has a 12-bit, 250 MHz ADC and an FPGA and stuff. > >> > >> We want to make sure that every ADC bit works, and no data bits are > >> shorted to other bits on the PC board. So we'll apply a triangle wave > >> that's a bit bigger than the 0..+3 volt ADC range, randomly read > >> values, and run some sort of code to make sure every bit goes up and > >> down and also look for shorted bits somehow. > >> > >> So, here's the triangle generator. R2 would probably be a pot, to set > >> the amplitude; the frequency doesn't matter much. > >> > >> Sometimes you've just got to design dumb stuff. > >> > >> > >> Version 4 > >> SHEET 1 952 680 > >> WIRE 672 -208 608 -208 > >> WIRE 784 -208 736 -208 > >> WIRE 368 -176 336 -176 > >> WIRE 400 -176 368 -176 > >> WIRE 512 -176 464 -176 > >> WIRE 528 -176 512 -176 > >> WIRE 336 -128 336 -176 > >> WIRE 464 -128 464 -176 > >> WIRE 608 -112 608 -208 > >> WIRE 656 -112 608 -112 > >> WIRE 784 -112 784 -208 > >> WIRE 784 -112 736 -112 > >> WIRE 336 -16 336 -48 > >> WIRE 464 -16 464 -48 > >> WIRE 608 -16 608 -112 > >> WIRE 640 -16 608 -16 > >> WIRE 784 -16 784 -112 > >> WIRE 784 -16 704 -16 > >> WIRE 144 0 96 0 > >> WIRE 288 0 224 0 > >> WIRE 704 64 672 64 > >> WIRE 672 80 672 64 > >> WIRE 96 96 96 0 > >> WIRE 128 96 96 96 > >> WIRE 176 96 128 96 > >> WIRE 288 96 288 0 > >> WIRE 288 96 240 96 > >> WIRE 336 96 288 96 > >> WIRE 448 96 400 96 > >> WIRE 608 96 608 -16 > >> WIRE 608 96 528 96 > >> WIRE 640 96 608 96 > >> WIRE 96 112 96 96 > >> WIRE 784 112 784 -16 > >> WIRE 784 112 704 112 > >> WIRE 832 112 784 112 > >> WIRE 848 112 832 112 > >> WIRE 640 128 608 128 > >> WIRE 608 160 608 128 > >> WIRE 672 176 672 144 > >> WIRE 704 176 672 176 > >> WIRE 96 192 96 176 > >> FLAG 96 192 0 > >> FLAG 832 112 out > >> FLAG 128 96 rc > >> FLAG 608 160 0 > >> FLAG 336 -16 0 > >> FLAG 464 -16 0 > >> FLAG 368 -176 +5 > >> FLAG 512 -176 -5 > >> FLAG 704 64 +5 > >> FLAG 704 176 -5 > >> SYMBOL Digital\\schmtinv 176 32 R0 > >> SYMATTR InstName A2 > >> SYMATTR Value2 Vhigh=5 Vt=2.5 Vh=0.5 > >> SYMATTR SpiceLine Td=5n > >> SYMBOL cap 80 112 R0 > >> WINDOW 0 68 39 Left 2 > >> WINDOW 3 63 73 Left 2 > >> SYMATTR InstName C1 > >> SYMATTR Value 20n > >> SYMBOL res 128 16 R270 > >> WINDOW 0 74 58 VTop 2 > >> WINDOW 3 67 58 VBottom 2 > >> SYMATTR InstName R1 > >> SYMATTR Value 10k > >> SYMBOL cap 400 80 R90 > >> WINDOW 0 77 33 VBottom 2 > >> WINDOW 3 86 31 VTop 2 > >> SYMATTR InstName C2 > >> SYMATTR Value 100n > >> SYMBOL res 544 80 R90 > >> WINDOW 0 75 54 VBottom 2 > >> WINDOW 3 87 54 VTop 2 > >> SYMATTR InstName R2 > >> SYMATTR Value 10K > >> SYMBOL Opamps\\UniversalOpamp2 672 112 R0 > >> WINDOW 0 36 24 Left 2 > >> SYMATTR InstName U1 > >> SYMBOL cap 704 -32 R90 > >> WINDOW 0 4 -8 VBottom 2 > >> WINDOW 3 26 -12 VTop 2 > >> SYMATTR InstName C3 > >> SYMATTR Value 5n > >> SYMBOL res 752 -128 R90 > >> WINDOW 0 -12 89 VBottom 2 > >> WINDOW 3 -40 32 VTop 2 > >> SYMATTR InstName R3 > >> SYMATTR Value 1Meg > >> SYMBOL diode 672 -192 R270 > >> WINDOW 0 47 -23 VTop 2 > >> WINDOW 3 75 57 VBottom 2 > >> SYMATTR InstName D1 > >> SYMATTR Value 1N4148 > >> SYMBOL voltage 336 -144 R0 > >> WINDOW 0 -77 37 Left 2 > >> WINDOW 3 -71 69 Left 2 > >> SYMATTR InstName V1 > >> SYMATTR Value 5 > >> SYMBOL voltage 464 -144 R0 > >> WINDOW 0 50 37 Left 2 > >> WINDOW 3 55 70 Left 2 > >> SYMATTR InstName V2 > >> SYMATTR Value -5 > >> TEXT -192 152 Left 2 !.tran 0 10m 0 20n > >> TEXT -248 -88 Left 2 ;NC7S14 Hyst~~1V at Vcc=5 > >> TEXT -256 -128 Left 2 ;ADC Test Triangle Generator > >> TEXT -184 -48 Left 2 ;period ~~ 0.81 RC > >> TEXT -152 -8 Left 2 ;F ~~ 7 KHz > >> TEXT -208 64 Left 2 ;J Larkin Feb 19, 2016 > >> > >> -- > >> > >> John Larkin Highland Technology, Inc > >> picosecond timing precision measurement > >> > >> jlarkin att highlandtechnology dott com > >> http://www.highlandtechnology.com > > > >Dumb is good word for it. > > Gosh, you must have a lot of friends. > > >What's your problem you can't use the time tested technique of dual amp, integrator + comparator, switching at and slewing between two precision thresholds? > > Partly, I don't need all that. I could do that, but it's just a little > more work. It's also a matter of what parts we have in stock. If I had > a 4000-series d-flop, I could use that and an LM393, running off +-6V, > and it wouldn't be bad. > > The triangle isn't especially interesting. What is more interesting is > the algorithm that will look at the 12-bit samples, 1000 or so, and > spot bit failures.
Do you have any I/O available? Seems a real test would use some sort of DAC, this could be a digital POT and voltage reference- seem to recall there are ways to cascade the pots to get very high resolution steps.
> > -- > > John Larkin Highland Technology, Inc > > lunatic fringe electronics
On Friday, February 19, 2016 at 3:53:41 PM UTC-8, John Larkin wrote:
> I'm designing a test set for an energy digitizer/integrator box. > > So, here's the triangle generator. R2 would probably be a pot
You can get a well-regulated triangle voltage with the right Schmitt trigger... R1 adjusts frequency, apply bias instead of grounding R2 for symmetry adjustment Version 4 SHEET 1 944 680 WIRE 160 0 -144 0 WIRE 592 0 160 0 WIRE 448 64 384 64 WIRE 560 64 512 64 WIRE -112 80 -160 80 WIRE 192 80 112 80 WIRE -144 144 -144 0 WIRE -112 144 -144 144 WIRE 384 144 384 64 WIRE 384 144 304 144 WIRE 448 144 384 144 WIRE 560 160 560 64 WIRE 560 160 512 160 WIRE 592 160 592 0 WIRE 592 160 560 160 WIRE 624 160 592 160 WIRE 400 176 304 176 WIRE 448 176 400 176 WIRE -112 208 -144 208 WIRE 160 208 160 0 WIRE 160 208 112 208 WIRE 224 224 224 144 WIRE -112 272 -160 272 WIRE -144 336 -144 208 WIRE 304 336 304 256 WIRE 304 336 -144 336 WIRE 576 336 304 336 FLAG 400 256 0 FLAG 624 160 Tri_out IOPIN 624 160 Out FLAG 224 224 0 FLAG 192 80 +5V IOPIN 192 80 In FLAG -160 80 -5V IOPIN -160 80 In FLAG 576 336 Square_out IOPIN 576 336 Out FLAG -160 272 +5V IOPIN -160 272 In SYMBOL Misc\\NE555 0 176 R0 SYMATTR InstName U1 SYMBOL Opamps\\opamp 480 96 R0 SYMATTR InstName U2 SYMBOL res 320 128 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMBOL res 384 160 R0 SYMATTR InstName R2 SYMBOL cap 512 48 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMBOL res 288 160 R0 SYMATTR InstName R3
On Sat, 20 Feb 2016 14:18:37 -0800 (PST), whit3rd <whit3rd@gmail.com>
wrote:

>On Friday, February 19, 2016 at 3:53:41 PM UTC-8, John Larkin wrote: >> I'm designing a test set for an energy digitizer/integrator box. >> >> So, here's the triangle generator. R2 would probably be a pot > >You can get a well-regulated triangle voltage with the right >Schmitt trigger... R1 adjusts frequency, apply bias instead >of grounding R2 for symmetry adjustment
That doesn't run on my LT Spice, but I think it doesn't make a triangle. This would probably work... https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/ESM_Triangle_1.JPG and it's fairly precise as regards levels and frequency. -- John Larkin Highland Technology, Inc lunatic fringe electronics