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LTSpice Simulation Hanging

Started by Tim Wescott February 8, 2016
LTSpice files not included because -- it's files, not file.

So, I have a fairly complicated circuit in LTSpice.  I'm playing some 
tricks on an LT3757A -- basically I need an externally settable voltage 
output, so I'm hijacking the FBX line and driving it from an op-amp 
summing circuit.  Everything was fine until I put that op-amp in there, 
but I suspect that I've just made the circuit too damned complicated, or 
too weird from LT's point of view.

The simulation is not quite hanging, but it's getting stuck in a state 
where it's progressing at tens of femptosecond/second, on a fairly speedy 
machine.

So my question is -- is there anything I can jigger in the various 
tolerances or other "don't touch this unless you know what you're doing 
and/or don't mind your simulation being meaningless" settings?

At the moment I've managed to make it work much better by removing some 
circuitry and replacing it with a fixed supply -- but it would be nice if 
I knew some more general ways of making all well, and as things stand 
I've just blown my overall efficiency calculations out of the water.

TIA.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott
<seemywebsite@myfooter.really> wrote:

>LTSpice files not included because -- it's files, not file. > >So, I have a fairly complicated circuit in LTSpice. I'm playing some >tricks on an LT3757A -- basically I need an externally settable voltage >output, so I'm hijacking the FBX line and driving it from an op-amp >summing circuit. Everything was fine until I put that op-amp in there, >but I suspect that I've just made the circuit too damned complicated, or >too weird from LT's point of view. > >The simulation is not quite hanging, but it's getting stuck in a state >where it's progressing at tens of femptosecond/second, on a fairly speedy >machine. > >So my question is -- is there anything I can jigger in the various >tolerances or other "don't touch this unless you know what you're doing >and/or don't mind your simulation being meaningless" settings? > >At the moment I've managed to make it work much better by removing some >circuitry and replacing it with a fixed supply -- but it would be nice if >I knew some more general ways of making all well, and as things stand >I've just blown my overall efficiency calculations out of the water. > >TIA.
Try setting, in Tools/Control_Panel/Spice, Solver = Alternate. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Mon, 08 Feb 2016 15:29:38 -0700, Jim Thompson wrote:

> On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott > <seemywebsite@myfooter.really> wrote: > >>LTSpice files not included because -- it's files, not file. >> >>So, I have a fairly complicated circuit in LTSpice. I'm playing some >>tricks on an LT3757A -- basically I need an externally settable voltage >>output, so I'm hijacking the FBX line and driving it from an op-amp >>summing circuit. Everything was fine until I put that op-amp in there, >>but I suspect that I've just made the circuit too damned complicated, or >>too weird from LT's point of view. >> >>The simulation is not quite hanging, but it's getting stuck in a state >>where it's progressing at tens of femptosecond/second, on a fairly >>speedy machine. >> >>So my question is -- is there anything I can jigger in the various >>tolerances or other "don't touch this unless you know what you're doing >>and/or don't mind your simulation being meaningless" settings? >> >>At the moment I've managed to make it work much better by removing some >>circuitry and replacing it with a fixed supply -- but it would be nice >>if I knew some more general ways of making all well, and as things stand >>I've just blown my overall efficiency calculations out of the water. >> >>TIA. > > Try setting, in Tools/Control_Panel/Spice, Solver = Alternate. > > ...Jim Thompson
Tried that, it didn't seem to help much. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
On 02/08/2016 11:38 PM, Tim Wescott wrote:
> > Tried that, it didn't seem to help much. >
try putting small inductors on every wire.
On Mon, 08 Feb 2016 16:38:38 -0600, Tim Wescott
<seemywebsite@myfooter.really> wrote:

>On Mon, 08 Feb 2016 15:29:38 -0700, Jim Thompson wrote: > >> On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott >> <seemywebsite@myfooter.really> wrote: >> >>>LTSpice files not included because -- it's files, not file. >>> >>>So, I have a fairly complicated circuit in LTSpice. I'm playing some >>>tricks on an LT3757A -- basically I need an externally settable voltage >>>output, so I'm hijacking the FBX line and driving it from an op-amp >>>summing circuit. Everything was fine until I put that op-amp in there, >>>but I suspect that I've just made the circuit too damned complicated, or >>>too weird from LT's point of view. >>> >>>The simulation is not quite hanging, but it's getting stuck in a state >>>where it's progressing at tens of femptosecond/second, on a fairly >>>speedy machine. >>> >>>So my question is -- is there anything I can jigger in the various >>>tolerances or other "don't touch this unless you know what you're doing >>>and/or don't mind your simulation being meaningless" settings? >>> >>>At the moment I've managed to make it work much better by removing some >>>circuitry and replacing it with a fixed supply -- but it would be nice >>>if I knew some more general ways of making all well, and as things stand >>>I've just blown my overall efficiency calculations out of the water. >>> >>>TIA. >> >> Try setting, in Tools/Control_Panel/Spice, Solver = Alternate. >> >> ...Jim Thompson > >Tried that, it didn't seem to help much.
Set max timestep at 10ns, do a short simulation, look for oscillation. All amplifiers oscillate, all oscillators won't start ;-) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On 08/02/2016 22:24, Tim Wescott wrote:
> LTSpice files not included because -- it's files, not file. > > So, I have a fairly complicated circuit in LTSpice. I'm playing some > tricks on an LT3757A -- basically I need an externally settable voltage > output, so I'm hijacking the FBX line and driving it from an op-amp > summing circuit. Everything was fine until I put that op-amp in there, > but I suspect that I've just made the circuit too damned complicated, or > too weird from LT's point of view.
The thing to try and do is simplify the circuit in a way that either preserves the bad behaviour or cures it if you are very lucky. (seems like you have already done this)
> > The simulation is not quite hanging, but it's getting stuck in a state > where it's progressing at tens of femptosecond/second, on a fairly speedy > machine.
My hunch would be that the matrix is close to singular and/or there is a non-linearity somewhere making it very stiff. Reminds me of a set of ODEs we once solved only get get back in the morning to find a half a plot with a message from the operators saying "your plot was cancelled because the red pen began to work loose - please resubmit". Then we looked at the plot on a Tek screen only to find the line steps were um as we zoomed in on spirals of doom. No wonder the plotter was unhappy. Things that ought to be decaying exponentially but due to numerical instabilities are trying to grow exponentially instead are the canonical source of stiffness. The numerical method halves the stepsize to regain control of the error but this isn't always helpful.
> > So my question is -- is there anything I can jigger in the various > tolerances or other "don't touch this unless you know what you're doing > and/or don't mind your simulation being meaningless" settings?
Hobble the gain bandwidth of the opamp?
> At the moment I've managed to make it work much better by removing some > circuitry and replacing it with a fixed supply -- but it would be nice if > I knew some more general ways of making all well, and as things stand > I've just blown my overall efficiency calculations out of the water. > > TIA. >
-- Regards, Martin Brown
On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott wrote:

> LTSpice files not included because -- it's files, not file. > > So, I have a fairly complicated circuit in LTSpice. I'm playing some > tricks on an LT3757A -- basically I need an externally settable voltage > output, so I'm hijacking the FBX line and driving it from an op-amp > summing circuit. Everything was fine until I put that op-amp in there, > but I suspect that I've just made the circuit too damned complicated, or > too weird from LT's point of view. > > The simulation is not quite hanging, but it's getting stuck in a state > where it's progressing at tens of femptosecond/second, on a fairly > speedy machine. > > So my question is -- is there anything I can jigger in the various > tolerances or other "don't touch this unless you know what you're doing > and/or don't mind your simulation being meaningless" settings? > > At the moment I've managed to make it work much better by removing some > circuitry and replacing it with a fixed supply -- but it would be nice > if I knew some more general ways of making all well, and as things stand > I've just blown my overall efficiency calculations out of the water. > > TIA.
Could you replace the added opamp with some kind of infinite-bandwidth circuit (e.g. controlled source)? Of course this might negate the whole advantage of doing the simulation, but it might be good as a starting point. Once that's going you can make it more realistic.
On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott
<seemywebsite@myfooter.really> wrote:

>LTSpice files not included because -- it's files, not file. > >So, I have a fairly complicated circuit in LTSpice. I'm playing some >tricks on an LT3757A -- basically I need an externally settable voltage >output, so I'm hijacking the FBX line and driving it from an op-amp >summing circuit. Everything was fine until I put that op-amp in there, >but I suspect that I've just made the circuit too damned complicated, or >too weird from LT's point of view.
Post your .ASC Did "driving it from an op-amp summing circuit" change the loop gain or mung the phase?
> >The simulation is not quite hanging, but it's getting stuck in a state >where it's progressing at tens of femptosecond/second, on a fairly speedy >machine. > >So my question is -- is there anything I can jigger in the various >tolerances or other "don't touch this unless you know what you're doing >and/or don't mind your simulation being meaningless" settings? > >At the moment I've managed to make it work much better by removing some >circuitry and replacing it with a fixed supply -- but it would be nice if >I knew some more general ways of making all well, and as things stand >I've just blown my overall efficiency calculations out of the water. > >TIA.
...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Mon, 08 Feb 2016 16:15:46 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott ><seemywebsite@myfooter.really> wrote: > >>LTSpice files not included because -- it's files, not file. >> >>So, I have a fairly complicated circuit in LTSpice. I'm playing some >>tricks on an LT3757A -- basically I need an externally settable voltage >>output, so I'm hijacking the FBX line and driving it from an op-amp >>summing circuit. Everything was fine until I put that op-amp in there, >>but I suspect that I've just made the circuit too damned complicated, or >>too weird from LT's point of view. > >Post your .ASC > >Did "driving it from an op-amp summing circuit" change the loop gain >or mung the phase? >
[snip] You should be able to set the output voltage _without_ putting the OpAmp in the feedback loop. What range of output voltages are you seeking? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Mon, 08 Feb 2016 16:15:46 -0700, Jim Thompson wrote:

> On Mon, 08 Feb 2016 16:24:26 -0600, Tim Wescott > <seemywebsite@myfooter.really> wrote: > >>LTSpice files not included because -- it's files, not file. >> >>So, I have a fairly complicated circuit in LTSpice. I'm playing some >>tricks on an LT3757A -- basically I need an externally settable voltage >>output, so I'm hijacking the FBX line and driving it from an op-amp >>summing circuit. Everything was fine until I put that op-amp in there, >>but I suspect that I've just made the circuit too damned complicated, or >>too weird from LT's point of view. > > Post your .ASC > > Did "driving it from an op-amp summing circuit" change the loop gain or > mung the phase?
I could pretty much replicate the behavior of the plain old LT3757, only working off of a variable voltage source instead of the fixed 1.6V. There are three files here: the asc file, a symbol file for a ZXGD3001E6, and a spice library file for a ZXGD3001E6. The seeming excess of passive components around the op-amp is for a reason (good start-up behavior), and doesn't seem to have much of a bearing on whether the thing locks up or not. .asc: Version 4 SHEET 1 4556 1460 WIRE 1808 -352 1696 -352 WIRE 2512 -352 1872 -352 WIRE 2560 -352 2512 -352 WIRE 2768 -352 2560 -352 WIRE 2992 -352 2768 -352 WIRE -96 -304 -240 -304 WIRE 176 -304 -96 -304 WIRE 1520 -304 176 -304 WIRE 2144 -304 1520 -304 WIRE 2416 -304 2320 -304 WIRE 2560 -304 2560 -352 WIRE 2560 -304 2480 -304 WIRE 1520 -272 1520 -304 WIRE 1696 -272 1696 -352 WIRE 2144 -272 2144 -304 WIRE 2320 -272 2320 -304 WIRE -96 -256 -96 -304 WIRE 2560 -256 2560 -304 WIRE 2992 -224 2992 -352 WIRE 1712 -192 1696 -192 WIRE 2336 -192 2320 -192 WIRE -96 -160 -96 -192 WIRE 1392 -160 1328 -160 WIRE 1520 -160 1520 -192 WIRE 1520 -160 1456 -160 WIRE 1712 -160 1712 -192 WIRE 2016 -160 1952 -160 WIRE 2144 -160 2144 -192 WIRE 2144 -160 2080 -160 WIRE 2336 -160 2336 -192 WIRE 2560 -160 2560 -192 WIRE 1328 -112 1328 -160 WIRE 1728 -112 1328 -112 WIRE 1952 -112 1952 -160 WIRE 1952 -112 1728 -112 WIRE 2352 -112 1952 -112 WIRE 2512 -112 2352 -112 WIRE 2512 -80 2512 -112 WIRE 192 -48 64 -48 WIRE 256 -48 192 -48 WIRE 416 -48 256 -48 WIRE 672 -48 416 -48 WIRE 896 -48 672 -48 WIRE 1136 -48 896 -48 WIRE 1872 -48 1136 -48 WIRE 2992 -48 2992 -144 WIRE 416 -32 416 -48 WIRE 256 -16 256 -48 WIRE 1136 -16 1136 -48 WIRE 1520 -16 1520 -160 WIRE 1872 -16 1872 -48 WIRE 2144 -16 2144 -160 WIRE 672 0 672 -48 WIRE 2352 0 2352 -112 WIRE 2512 16 2512 0 WIRE -240 32 -240 -304 WIRE 64 32 64 -48 WIRE 1040 32 1008 32 WIRE 1296 32 1232 32 WIRE 1776 32 1744 32 WIRE 2032 32 1968 32 WIRE 2944 32 2896 32 WIRE 416 64 416 48 WIRE 512 64 416 64 WIRE 896 64 896 -48 WIRE 896 64 832 64 WIRE 1008 64 1008 32 WIRE 1040 64 1008 64 WIRE 1296 64 1296 32 WIRE 1296 64 1232 64 WIRE 1472 64 1296 64 WIRE 1744 64 1744 32 WIRE 1776 64 1744 64 WIRE 2032 64 2032 32 WIRE 2032 64 1968 64 WIRE 2096 64 2032 64 WIRE 2896 80 2896 32 WIRE 256 96 256 48 WIRE 2768 96 2768 -352 WIRE 2768 96 2672 96 WIRE 2992 96 2992 48 WIRE 2352 112 2352 64 WIRE 2512 112 2512 80 WIRE 1136 128 1136 112 WIRE 1872 128 1872 112 WIRE -240 144 -240 112 WIRE 64 144 64 112 WIRE 928 160 832 160 WIRE 1008 160 1008 64 WIRE 1008 160 928 160 WIRE 1744 160 1744 64 WIRE 1744 160 1008 160 WIRE 2672 176 2672 96 WIRE 2896 192 2896 160 WIRE 2496 208 2400 208 WIRE 1520 240 1520 80 WIRE 2144 240 2144 80 WIRE 2144 240 1520 240 WIRE 2400 240 2400 208 WIRE 512 256 64 256 WIRE 1520 256 1520 240 WIRE 1520 256 832 256 WIRE 3312 272 3264 272 WIRE 3312 288 3312 272 WIRE 64 304 64 256 WIRE 2768 304 2768 96 WIRE 2672 320 2672 256 WIRE 240 352 224 352 WIRE 352 352 320 352 WIRE 480 352 352 352 WIRE 512 352 480 352 WIRE 960 352 832 352 WIRE 1792 352 960 352 WIRE 1904 352 1792 352 WIRE 1952 352 1904 352 WIRE 2096 352 2032 352 WIRE 2400 352 2400 320 WIRE 352 400 352 352 WIRE 3312 400 3312 368 WIRE 896 416 896 64 WIRE 1520 416 1520 256 WIRE 1792 416 1792 352 WIRE 1904 432 1904 352 WIRE 2048 432 1904 432 WIRE 2192 432 2128 432 WIRE 2240 432 2192 432 WIRE 2384 432 2240 432 WIRE 2544 432 2448 432 WIRE 2672 432 2672 384 WIRE 2768 432 2768 384 WIRE 2768 432 2672 432 WIRE 64 464 64 384 WIRE 416 464 416 64 WIRE 672 464 672 416 WIRE 2496 464 2496 208 WIRE 2544 480 2544 432 WIRE 2544 480 2528 480 WIRE 3088 480 2544 480 WIRE 3216 480 3168 480 WIRE 352 496 352 464 WIRE 2240 496 2240 432 WIRE 2464 496 2240 496 WIRE 2672 512 2528 512 WIRE 2768 512 2768 432 WIRE 2768 512 2672 512 WIRE 3216 512 3216 480 WIRE 896 528 896 480 WIRE 1520 528 1520 496 WIRE 2768 528 2768 512 WIRE 2672 544 2672 512 WIRE 1792 560 1792 496 WIRE 2496 560 2496 528 WIRE 416 592 416 544 WIRE 2672 640 2672 608 WIRE 2768 640 2768 608 WIRE 3216 640 3216 592 FLAG -240 144 0 FLAG 672 464 0 FLAG 1520 528 0 FLAG 896 528 0 FLAG 64 464 0 FLAG 928 160 Vg1 FLAG 2560 -160 0 FLAG 2992 96 0 FLAG 2896 192 0 FLAG -96 -160 0 FLAG 256 96 0 FLAG 1712 -160 0 FLAG 2352 112 0 FLAG 2512 -352 Vout FLAG 1728 -112 Vsnub FLAG 2336 -160 0 FLAG 176 -304 Vin FLAG 480 352 Vc FLAG 960 352 Vfbx FLAG 1136 128 0 FLAG 1872 128 0 FLAG 192 -48 Vgs FLAG 416 592 0 FLAG 2512 112 0 FLAG 3216 640 0 FLAG 2496 560 0 FLAG 3264 272 Vvg FLAG 3312 400 0 FLAG 2768 640 0 FLAG 2192 432 Vvcmd FLAG 2096 352 Vvg FLAG 224 352 Vvg FLAG 2400 352 0 FLAG 1792 560 0 FLAG 352 496 0 FLAG 2672 640 0 FLAG 64 144 0 SYMBOL voltage -240 16 R0 WINDOW 123 0 0 Left 2 WINDOW 39 24 124 Left 2 SYMATTR SpiceLine Rser=10m SYMATTR InstName V1 SYMATTR Value PWL(0 0 1m 3.2) SYMBOL PowerProducts\\LT3757A 672 208 R0 SYMATTR InstName U1 SYMBOL cap 880 416 R0 SYMATTR InstName C1 SYMATTR Value 4.7&#7745; SYMBOL res 1504 400 R0 SYMATTR InstName R1 SYMATTR Value 3m SYMBOL nmos 1472 -16 R0 SYMATTR InstName M1 SYMATTR Value BSZ067N06LS3 SYMBOL ind2 1504 -176 M180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L1 SYMATTR Value 2.4&#7745; SYMATTR SpiceLine Rser=12.5m SYMATTR Type ind SYMBOL res 2144 416 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 100k SYMBOL res 48 288 R0 SYMATTR InstName R4 SYMATTR Value 100k SYMBOL cap 2544 -256 R0 SYMATTR InstName C4 SYMATTR Value 2.2&#7745; SYMBOL res 2976 -240 R0 SYMATTR InstName R11 SYMATTR Value 1.42k SYMBOL nmos 2944 -48 R0 SYMATTR InstName M3 SYMATTR Value FDS2734 SYMBOL voltage 2896 64 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(0 12 4m 1u 1u 100u 1m) SYMBOL cap -112 -256 R0 SYMATTR InstName C7 SYMATTR Value 2200&#7745; SYMBOL cap 240 -16 R0 SYMATTR InstName C9 SYMATTR Value 1&#7745; SYMBOL ind2 1712 -288 M0 SYMATTR InstName L2 SYMATTR Value 1310&#7745; SYMATTR Type ind SYMATTR SpiceLine Rser=3 SYMBOL schottky 1808 -336 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value UPSC600 SYMATTR Description Diode SYMATTR Type diode SYMBOL cap 2336 0 R0 SYMATTR InstName C3 SYMATTR Value 10&#7745; SYMBOL nmos 2096 -16 R0 SYMATTR InstName M2 SYMATTR Value BSZ067N06LS3 SYMBOL ind2 2128 -176 M180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L3 SYMATTR Value 2.4&#7745; SYMATTR SpiceLine Rser=12.5m SYMATTR Type ind SYMBOL ind2 2336 -288 M0 SYMATTR InstName L4 SYMATTR Value 1310&#7745; SYMATTR Type ind SYMATTR SpiceLine Rser=3 SYMBOL schottky 2416 -288 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D4 SYMATTR Value UPSC600 SYMATTR Description Diode SYMATTR Type diode SYMBOL schottky 1456 -176 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D5 SYMATTR Value UPSC600 SYMATTR Description Diode SYMATTR Type diode SYMBOL schottky 2080 -176 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D6 SYMATTR Value UPSC600 SYMATTR Description Diode SYMATTR Type diode SYMBOL ZXGD3001E6 1136 48 R0 SYMATTR InstName U2 SYMBOL ZXGD3001E6 1872 48 R0 SYMATTR InstName U3 SYMBOL res 400 -48 R0 SYMATTR InstName R8 SYMATTR Value 301k SYMBOL res 400 448 R0 SYMATTR InstName R10 SYMATTR Value 100k SYMBOL zener 2528 80 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D7 SYMATTR Value EDZV30B SYMATTR Description Diode SYMATTR Type diode SYMBOL res 2496 -96 R0 SYMATTR InstName R13 SYMATTR Value 100 SYMBOL voltage 3216 496 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PWL(0 4) SYMBOL Opamps\\UniversalOpamp2 2496 496 M0 SYMATTR InstName U5 SYMBOL voltage 3312 272 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V4 SYMATTR Value 1.6 SYMBOL res 2752 512 R0 SYMATTR InstName R14 SYMATTR Value 20.5k SYMBOL res 2752 288 R0 SYMATTR InstName R15 SYMATTR Value 1.00meg SYMBOL res 3184 464 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R17 SYMATTR Value 20.5k SYMBOL res 2048 336 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 4.99k SYMBOL res 224 368 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R6 SYMATTR Value 100k SYMBOL cap 2448 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 330p SYMBOL voltage 2400 224 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V5 SYMATTR Value 5 SYMBOL res 1776 400 R0 SYMATTR InstName R12 SYMATTR Value 200k SYMBOL cap 336 400 R0 SYMATTR InstName C10 SYMATTR Value 33p SYMBOL cap 2656 544 R0 SYMATTR InstName C11 SYMATTR Value 330p SYMBOL cap 2656 320 R0 SYMATTR InstName C12 SYMATTR Value 47p SYMBOL res 2656 160 R0 SYMATTR InstName R16 SYMATTR Value 100k SYMBOL voltage 64 16 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V6 SYMATTR Value 12 TEXT -208 560 Left 2 !.tran 10m startup TEXT 1312 -240 Left 2 !K1 L1 L2 0.985 TEXT 1296 -272 Left 2 ;Wurth 760871113 TEXT 1936 -240 Left 2 !K2 L3 L4 0.985 TEXT 1912 -272 Left 2 ;Wurth 760871113 TEXT -208 592 Left 2 !.lib ZXGD3001E6.spicemodel.lib ZXGD3001E6.asy: Version 4 SymbolType CELL LINE Normal -96 64 -96 -64 LINE Normal 96 64 -96 64 LINE Normal 96 -63 96 64 LINE Normal 96 -64 96 -63 LINE Normal -96 -64 96 -64 WINDOW 0 32 -80 Left 2 WINDOW 1 32 80 Left 2 SYMATTR Prefix X SYMATTR SpiceModel ZXGD3001E6 PIN 0 -64 TOP 8 PINATTR PinName VCC PINATTR SpiceOrder 1 PIN -96 -16 LEFT 8 PINATTR PinName IN1 PINATTR SpiceOrder 2 PIN -96 16 LEFT 8 PINATTR PinName IN2 PINATTR SpiceOrder 5 PIN 0 64 BOTTOM 8 PINATTR PinName GND PINATTR SpiceOrder 3 PIN 96 16 RIGHT 8 PINATTR PinName SINK PINATTR SpiceOrder 4 PIN 96 -16 RIGHT 8 PINATTR PinName SOURCE PINATTR SpiceOrder 6 ZXGD3001E6.spicemodel.lib: * *Zetex ZXGD3001E6 Spice Model v2.0 Last Revised 17/09/08 * .SUBCKT ZXGD3001E6 1 2 3 4 5 6 *pins Vcc, In1, Gnd, Sink, In2, Source Q1 1 2 6 ZXGD3001N Q2 3 5 4 ZXGD3001P * .MODEL ZXGD3001N NPN IS=9E-13 BF=990 NF=1 VAF=25 IKF=3.8 ISE=8E-14 NE=1.35 + BR=410 NR=1 VAR=8 IKR=1.25 ISC=8e-14 NC=1.35 RE=0.0117 RB=0.1 RC=0.0081 + CJE=168E-12 VJE=0.7 MJE=0.38 CJC=61E-12 VJC=0.52 MJC=0.31 TF=0.5E-9 TR=1.7e-9 + XTB=1.4 * .MODEL ZXGD3001P PNP IS=5.5E-13 NF=1 BF=650 VAF=20 ISE=1.9E-13 + IKF=2.5 NE=1.53 BR=72 VAR=4.1 ISC=7E-14 NC=1.2 IKR=0.25 RC=0.010 + RB=0.15 RE=0.006 QUASIMOD=1 RCO=0.7 GAMMA=1.7E-9 CJC=57E-12 MJC=0.35 + VJC=0.53 CJE=168E-12 MJE=0.54 VJE=0.95 TF=0.42E-9 TR=8.4E-9 TRC1=0.005 + TRB1=0.005 TRE1=0.005 XTB=1.4 * .ENDS ZXGD3001E6 * *$ * * (c) 2008 Diodes Incorporated * * The copyright in these models and the designs embodied belong * to Diodes Incorporated (" Diodes "). They are supplied * free of charge by Diodes for the purpose of research and design * and may be used or copied intact (including this notice) for * that purpose only. All other rights are reserved. The models * are believed accurate but no condition or warranty as to their * merchantability or fitness for purpose is given and no liability * in respect of any use is accepted by Diodes Incorporated, its distributors * or agents. * * Diodes Incorporated, 1566 N. Dallas Parkway, Suite 850, Dallas, TX 75248, USA -- Tim Wescott Wescott Design Services http://www.wescottdesign.com