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TS555IN question (CMOS timer)

Started by M Philbrook November 21, 2015
 We have a remote signaling device that operates from a 
3.2V battery source using a CMOS version of the timer..

 
http://www.st.com/web/en/resource/technical/document/datasheet/CD0000089
3.pdf

 At random and I mean very random, the circuit may need a power
cycle. 

 I was able to probe it while in a failed state and it appears that the 
chip could be latching?
 
 The only input that is exposed to what could be a possible issue
is the threshold input.

  I thought that if this is a latching issue that maybe it was losing 
the power source while moving around and the input was exceeding the 
Vdd? But that proved to be not the case.

 I can't go into what this is used for other than it sits on a rotating
mass powered via a cell pack and operates a tracking laser (small 
diode). etc.

 Has anyone experience this chip performing the magical latching that 
some Fet entities have?

Jamie


 
On Sat, 21 Nov 2015 18:34:16 -0500, M Philbrook
<jamie_ka1lpa@charter.net> wrote:

> > We have a remote signaling device that operates from a >3.2V battery source using a CMOS version of the timer.. > > >http://www.st.com/web/en/resource/technical/document/datasheet/CD00000893.pdf > > At random and I mean very random, the circuit may need a power >cycle. > > I was able to probe it while in a failed state and it appears that the >chip could be latching? > > The only input that is exposed to what could be a possible issue >is the threshold input. > > I thought that if this is a latching issue that maybe it was losing >the power source while moving around and the input was exceeding the >Vdd? But that proved to be not the case. > > I can't go into what this is used for other than it sits on a rotating >mass powered via a cell pack and operates a tracking laser (small >diode). etc. > > Has anyone experience this chip performing the magical latching that >some Fet entities have? > >Jamie > > >
...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Sat, 21 Nov 2015 18:34:16 -0500, M Philbrook
<jamie_ka1lpa@charter.net> wrote:

> > We have a remote signaling device that operates from a >3.2V battery source using a CMOS version of the timer.. > > >http://www.st.com/web/en/resource/technical/document/datasheet/CD00000893.pdf > > At random and I mean very random, the circuit may need a power >cycle. > > I was able to probe it while in a failed state and it appears that the >chip could be latching? > > The only input that is exposed to what could be a possible issue >is the threshold input. > > I thought that if this is a latching issue that maybe it was losing >the power source while moving around and the input was exceeding the >Vdd? But that proved to be not the case. > > I can't go into what this is used for other than it sits on a rotating >mass powered via a cell pack and operates a tracking laser (small >diode). etc. > > Has anyone experience this chip performing the magical latching that >some Fet entities have? > >Jamie > > >
Can you post your complete circuit... at least around the TS555? If you're just dropping power (VDD), it could be that charge on the timing cap is causing the hang. Try a Germanium or Schottky diode from threshold (anode) to VDD (cathode). ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Sat, 21 Nov 2015 18:34:16 -0500, M Philbrook
<jamie_ka1lpa@charter.net> wrote:

> > We have a remote signaling device that operates from a >3.2V battery source using a CMOS version of the timer.. > > >http://www.st.com/web/en/resource/technical/document/datasheet/CD0000089 >3.pdf > > At random and I mean very random, the circuit may need a power >cycle. > > I was able to probe it while in a failed state and it appears that the >chip could be latching? > > The only input that is exposed to what could be a possible issue >is the threshold input. > > I thought that if this is a latching issue that maybe it was losing >the power source while moving around and the input was exceeding the >Vdd? But that proved to be not the case. > > I can't go into what this is used for other than it sits on a rotating >mass powered via a cell pack and operates a tracking laser (small >diode). etc. > > Has anyone experience this chip performing the magical latching that >some Fet entities have? > >Jamie > > >
Could be classic CMOS parasitic SCR latchup. Do any of the pins connect or couple to the outside world, or to any spikey stuff? A small spike into a pin can trigger some CMOS devices. If the data sheet doesn't specify a limit for ESD diode current, that usually means the chip is not hardened against latchup. You could bench test one and see if it has latchup modes.
In article <MPG.30bac96f3e43bc50989dbc@news.eternal-september.org>,
 M Philbrook <jamie_ka1lpa@charter.net> wrote:

> We have a remote signaling device that operates from a > 3.2V battery source using a CMOS version of the timer.. > > > http://www.st.com/web/en/resource/technical/document/datasheet/CD0000089 > 3.pdf > > At random and I mean very random, the circuit may need a power > cycle. > > I was able to probe it while in a failed state and it appears that the > chip could be latching? > > The only input that is exposed to what could be a possible issue > is the threshold input. > > I thought that if this is a latching issue that maybe it was losing > the power source while moving around and the input was exceeding the > Vdd? But that proved to be not the case. > > I can't go into what this is used for other than it sits on a rotating > mass powered via a cell pack and operates a tracking laser (small > diode). etc. > > Has anyone experience this chip performing the magical latching that > some Fet entities have? > > Jamie > > >
Are you driving a transistor from the timer Output line? If the drain/collector voltage suddenly drops while the gate/base is at 0 volts, capacitive/diode coupling will send the voltage negative. The transistors on pins 3 and 7 are driven from the same line. At the very least, pin 3 going out of range messes with pin 7. Some 555 varieties burn out too. -- I will not see posts from astraweb, theremailer, dizum, or google because they host Usenet flooders.
In article <de525bh85h1rtr4ve7c38pup0l6ajsfdoj@4ax.com>, 
jjlarkin@highlandtechnology.com says...
> > On Sat, 21 Nov 2015 18:34:16 -0500, M Philbrook > <jamie_ka1lpa@charter.net> wrote: > > > > > We have a remote signaling device that operates from a > >3.2V battery source using a CMOS version of the timer.. > > > > > >http://www.st.com/web/en/resource/technical/document/datasheet/CD0000089 > >3.pdf > > > > At random and I mean very random, the circuit may need a power > >cycle. > > > > I was able to probe it while in a failed state and it appears that the > >chip could be latching? > > > > The only input that is exposed to what could be a possible issue > >is the threshold input. > > > > I thought that if this is a latching issue that maybe it was losing > >the power source while moving around and the input was exceeding the > >Vdd? But that proved to be not the case. > > > > I can't go into what this is used for other than it sits on a rotating > >mass powered via a cell pack and operates a tracking laser (small > >diode). etc. > > > > Has anyone experience this chip performing the magical latching that > >some Fet entities have? > > > >Jamie > > > > > > > > Could be classic CMOS parasitic SCR latchup. Do any of the pins > connect or couple to the outside world, or to any spikey stuff? A > small spike into a pin can trigger some CMOS devices. > > If the data sheet doesn't specify a limit for ESD diode current, that > usually means the chip is not hardened against latchup. > > You could bench test one and see if it has latchup modes.
I did and yes, it seems that it stops working, then I need to power cycle it. The threshold is expose to something on the outside but I do have a clamp on the line however, after more research, it could be the clamp isn't proper when the cell voltage start to drop over time. I will take Jims T advice and put a diode on the threshold over to the Vdd,VSS and see what happens. Thanks
In article <mcmurtrie-D613B8.23052521112015@news.sonic.net>, 
mcmurtrie@pixelmemory.us says...
> > In article <MPG.30bac96f3e43bc50989dbc@news.eternal-september.org>, > M Philbrook <jamie_ka1lpa@charter.net> wrote: > > > We have a remote signaling device that operates from a > > 3.2V battery source using a CMOS version of the timer.. > > > > > > http://www.st.com/web/en/resource/technical/document/datasheet/CD0000089 > > 3.pdf > > > > At random and I mean very random, the circuit may need a power > > cycle. > > > > I was able to probe it while in a failed state and it appears that the > > chip could be latching? > > > > The only input that is exposed to what could be a possible issue > > is the threshold input. > > > > I thought that if this is a latching issue that maybe it was losing > > the power source while moving around and the input was exceeding the > > Vdd? But that proved to be not the case. > > > > I can't go into what this is used for other than it sits on a rotating > > mass powered via a cell pack and operates a tracking laser (small > > diode). etc. > > > > Has anyone experience this chip performing the magical latching that > > some Fet entities have? > > > > Jamie > > > > > > > > Are you driving a transistor from the timer Output line? If the > drain/collector voltage suddenly drops while the gate/base is at 0 > volts, capacitive/diode coupling will send the voltage negative. > > The transistors on pins 3 and 7 are driven from the same line. At the > very least, pin 3 going out of range messes with pin 7. Some 555 > varieties burn out too.
Good point, we'll scope that line to see if any abnormals are there, I don't think I'll see any. The output drives a smt 2222 for a sink source to the following circuit.I do have a sink R at the base. Jamie
In article <r2025bdj8phq0lsh0cmrrfmlfqagjdgplr@4ax.com>, To-Email-Use-
The-Envelope-Icon@On-My-Web-Site.com says...
> > On Sat, 21 Nov 2015 18:34:16 -0500, M Philbrook > <jamie_ka1lpa@charter.net> wrote: > > > > > We have a remote signaling device that operates from a > >3.2V battery source using a CMOS version of the timer.. > > > > > >http://www.st.com/web/en/resource/technical/document/datasheet/CD00000893.pdf > > > > At random and I mean very random, the circuit may need a power > >cycle. > > > > I was able to probe it while in a failed state and it appears that the > >chip could be latching? > > > > The only input that is exposed to what could be a possible issue > >is the threshold input. > > > > I thought that if this is a latching issue that maybe it was losing > >the power source while moving around and the input was exceeding the > >Vdd? But that proved to be not the case. > > > > I can't go into what this is used for other than it sits on a rotating > >mass powered via a cell pack and operates a tracking laser (small > >diode). etc. > > > > Has anyone experience this chip performing the magical latching that > >some Fet entities have? > > > >Jamie > > > > > > > > Can you post your complete circuit... at least around the TS555? If > you're just dropping power (VDD), it could be that charge on the > timing cap is causing the hang. > > Try a Germanium or Schottky diode from threshold (anode) to VDD > (cathode). > > ...Jim Thompson
Yes, good idea, Thanks Jamie