Forums

signal pickoff

Started by John Larkin November 13, 2015
On Sunday, 15 November 2015 20:42:03 UTC, John Larkin  wrote:
> >> On Sun, 15 Nov 2015 nt wrote: > >On Sunday, 15 November 2015 16:27:39 UTC, John Larkin wrote: > >> On Sun, 15 Nov 2015 02:47:06 -0800 (PST), nt wrote: > >> >On Sunday, 15 November 2015 02:19:14 UTC, John Larkin wrote: > >> >> On Sat, 14 Nov 2015 16:04:44 -0800 (PST), nt wrote:
> >> >> >Preset pots are a long term reliability disaster. > >> >> > >> >> Why? > >> > > >> >I'm not sure why, but experience shows they are. It's why they've fallen out of favour. > >> > >> Pots are fine as long as you don't expect more than about 0.25% > >> longterm stability. In my current situation, I'm just trying to make a > >> pulse look good on a scope, so a few per cent of the pot range would > >> be close enough. > > > >Pots aren't too bad, little presets are > > What is a "little preset"?
A preset pot has no shaft, is soldered direct to PCB and twiddled before the appliance leaves the factory, then never touched again. Those have really lousy long term reliability, which is one reason why they disappeared from most appliances. NT
On Sun, 15 Nov 2015 14:11:07 -0800 (PST), dagmargoodboat@yahoo.com
wrote:

>On Sunday, November 15, 2015 at 3:41:06 PM UTC-5, John Larkin wrote: >> On Sun, 15 Nov 2015 09:24:39 -0800 (PST), dagmargoodboat@yahoo.com >> wrote: >> >> >On Saturday, November 14, 2015 at 11:30:34 AM UTC-5, John Larkin wrote: >> >> On Sat, 14 Nov 2015 03:03:27 -0800 (PST), dagmargoodboat@yahoo.com >> >> wrote: >> >> >> >> >On Friday, November 13, 2015 at 10:34:07 PM UTC-5, John Larkin wrote: >> >> >> On Fri, 13 Nov 2015 16:54:29 -0800 (PST), Lasse Langwadt Christensen >> >> >> <langwadt@fonz.dk> wrote: >> >> >> >> >> >> >Den l&#2013266168;rdag den 14. november 2015 kl. 01.22.28 UTC+1 skrev John Larkin: >> >> >> >> I'm designing a high-voltage pulser, 1200 volts or so, and I'd like to >> >> >> >> pick off a divided signal for the customer to monitor. >> >> >> >> >> >> >> >> https://dl.dropboxusercontent.com/u/53724080/Circuits/Resistors/Pickoff.JPG >> >> >> >> >> >> >> >> Rise/fall times will be a few us maybe. >> >> >> >> >> >> >> >> I'd like to have the pulse response be pretty good, so the >> >> >> >> capacitances matter. The OPA171 opamp and R2 have capacitance, roughly >> >> >> >> 4 pF total, and I guess the 1G 2010 resistor will, too. These have to >> >> >> >> be balanced at 500:1 to match the resistors. The cap across R2 can be >> >> >> >> chosen to work, but I don't want a discrete cap across R1. >> >> >> >> >> >> >> >> Maybe the 1G resistor has enough self-capacitance that I can pick the >> >> >> >> lower cap to work. Or maybe I should add some PCB traces to add >> >> >> >> capacitance across R1. I need about 0.02 pF if, say, I pad the bottom >> >> >> >> up to 10 pF. >> >> >> >> >> >> >> >> This will be a 4-layer board with L2 ground plane, but I can cut out >> >> >> >> some plane if that would help. >> >> >> >> >> >> >> >> Has anyone done something like this? >> >> >> >> >> >> >> > >> >> >> >why such big resistors? >> >> >> > >> >> >> >a standard 500:1 scope probe is 10M afaict >> >> >> > >> >> >> >why not a string of say 2M resistors and capacitors >> >> >> >> >> >> I have rational reasons for wanting a 1G resistor. Even more would be >> >> >> good, but I can get a 1G 3KV 2010. >> >> > >> >> >Wouldn't a trans impedance amp be faster? Then you wouldn't have to move the >> >> >summing node. You might have to make an ultra-low capacitance buffer, lest the >> >> >input capacitance make the thing unstable. >> >> > >> >> >Cheers, >> >> >James >> >> >> >> That's about a wash, and I'd need to re-invert the TIA output with >> >> another amp. >> >> >> >> The 1G resistor has some (currently unknown) shunt capacitance, and >> >> that makes a tau that any amplifier has to deal with. If the shunt C >> >> were zero, an ideal TIA would work. >> > >> >You're right, the problem here is peaking, the opposite of the usual TI >> >amp problem. >> > >> >> If I have a reasonable capacitance across the 1G, then the lowside >> >> compensating cap (either amp config) gets up into the tens or hundreds >> >> of pF, where I can get a reasonable selection of compensation cap >> >> choices. >> >> >> >> This is just a freebie current monitor so the customer can check that >> >> the pulse is working. It's not worth extreme measures. >> > >> >Then why not change the 2M divider resistor to 200k? 200K * 4pF = 800nS, >> >problem solved. Make the op-amp stage x10. Or 100k and x20. >> >> The parasitic shunt cap across the 1G resistor will differentiate the >> HV rising edge and still make a pulse overshoot. 0.1 pF and 1 Gohms >> has a tau of 100 usec > >1) Yes, it's differentiated and yes it'll overshoot. But the time constant is >.1pF and (1G in parallel with 200k), not 1G, so the overshoot is short-lived, >and maybe even too small to notice, depending on your slew rate. > >(The pulse / overshoot is also, technically, not 1,200V, but 1,200V * the >capacitive divider ratio between .1pF and ~4pF, or about 1/40th * 1,200V). > >But we're talking past each other--I've attached a sim file. Look at the >settling time difference between my suggestion V(A) and the original, V(B). >V(B_scaled) lets you see the two on the same scale. > >2) If it's really .1pF that's horrible; different measures are called for, >like a diff amp where a 2nd 1G resistor is a.c.-coupled, and subtracts the 1G >resistor's capacitively-coupled current from the output. > >> >> There are PCB techniques for reducing the effective capacitance across >> >> resistors. I want to increase it! >> > >> >Constructing the divider from 500 instances of the same resistor would >> >automatically balance their shunt capacitances according to the divider >> >ratio (and look very silly!). >> >> I saw an appnote recently, somewhere, for reducing resistor shunt >> capacitance, by a lot, by filling under the resistor with some topside >> ground. But that would wreck my high voltage clearance. >> >> I think some people do that trick with multiple series resistors, too. >> >> The worst way to tune a design is by re-etching PC boards. I don't >> want to do that. A variable cap or an equivalent pot-controlled >> capacitance would let my test people tweak the step response, >> independent of PCB variations. People who don't approve of trimmers >> will whine, but I am The President, after all. >> >> Caddock makes axial thickfilm resistors that have essentially no L or >> C. One of them can make a high voltage divider, into a 50 ohm scope, >> that's flat to something like 6 GHz. But I don't think they can do >> that at 1G ohms. Or in surface mount. > >Cheers, >James Arthur
The waveform at B is good if C4 is 50 pF. C is fine, but it's only 120 millivolts. I just have no idea if C1 is really 0.1 pF.
> >Version 4 >SHEET 1 1032 680 >WIRE 192 0 -48 0 >WIRE 272 0 192 0 >WIRE 368 0 272 0 >WIRE 448 0 368 0 >WIRE 800 0 448 0 >WIRE 880 0 800 0 >WIRE 272 16 272 0 >WIRE 880 16 880 0 >WIRE 192 32 192 0 >WIRE 368 32 368 0 >WIRE 448 32 448 0 >WIRE 800 32 800 0 >WIRE -48 96 -48 0 >WIRE 192 128 192 96 >WIRE 272 128 272 96 >WIRE 272 128 192 128 >WIRE 368 128 368 96 >WIRE 448 128 448 112 >WIRE 448 128 368 128 >WIRE 800 128 800 96 >WIRE 880 128 880 96 >WIRE 880 128 800 128 >WIRE 272 160 272 128 >WIRE 272 160 192 160 >WIRE 640 160 272 160 >WIRE 880 160 880 128 >WIRE 880 160 800 160 >WIRE 992 160 880 160 >WIRE 272 176 272 160 >WIRE 880 176 880 160 >WIRE 192 192 192 160 >WIRE 448 192 448 128 >WIRE 448 192 368 192 >WIRE 640 192 448 192 >WIRE 800 192 800 160 >WIRE -48 208 -48 176 >WIRE 448 208 448 192 >WIRE 368 224 368 192 >WIRE 192 272 192 256 >WIRE 800 272 800 256 >WIRE 272 288 272 256 >WIRE 880 288 880 256 >WIRE 448 304 448 288 >WIRE 640 304 448 304 >WIRE 368 320 368 288 >WIRE 448 320 448 304 >WIRE 448 432 448 400 >FLAG -48 208 0 >FLAG 272 288 0 >FLAG 192 272 0 >FLAG 448 432 0 >FLAG 368 320 0 >FLAG 640 160 A >FLAG 640 304 B_scaled >FLAG 640 192 B >FLAG 880 288 0 >FLAG 800 272 0 >FLAG 992 160 C >SYMBOL voltage -48 80 R0 >WINDOW 3 -154 169 Left 2 >WINDOW 123 0 0 Left 2 >WINDOW 39 0 0 Left 2 >SYMATTR InstName V1 >SYMATTR Value PULSE(0 1200 0 2uS 2uS 50uS) >SYMBOL res 256 0 R0 >SYMATTR InstName R1 >SYMATTR Value 1G >SYMBOL res 256 160 R0 >SYMATTR InstName R2 >SYMATTR Value 100k >SYMBOL cap 176 32 R0 >SYMATTR InstName C1 >SYMATTR Value .1pF >SYMBOL cap 176 192 R0 >SYMATTR InstName C2 >SYMATTR Value 4pF >SYMBOL res 432 16 R0 >SYMATTR InstName R3 >SYMATTR Value 1G >SYMBOL res 432 192 R0 >SYMATTR InstName R4 >SYMATTR Value 1.9meg >SYMBOL cap 352 32 R0 >SYMATTR InstName C3 >SYMATTR Value .1pF >SYMBOL cap 352 224 R0 >SYMATTR InstName C4 >SYMATTR Value 4pF >SYMBOL res 432 304 R0 >SYMATTR InstName R5 >SYMATTR Value 100k >SYMBOL res 864 0 R0 >SYMATTR InstName R6 >SYMATTR Value 1G >SYMBOL res 864 160 R0 >SYMATTR InstName R7 >SYMATTR Value 100k >SYMBOL cap 784 32 R0 >SYMATTR InstName C5 >SYMATTR Value .1pF >SYMBOL cap 784 192 R0 >SYMATTR InstName C6 >SYMATTR Value 1nF >TEXT 30 360 Left 2 !.tran 150uS >TEXT 608 384 Left 2 ;15-Nov-2015 jda
On Sunday, November 15, 2015 at 5:34:58 PM UTC-5, John Larkin wrote:
> On Sun, 15 Nov 2015 14:11:07 -0800 (PST), dagmargoodboat@yahoo.com > wrote: > > >On Sunday, November 15, 2015 at 3:41:06 PM UTC-5, John Larkin wrote: > >> On Sun, 15 Nov 2015 09:24:39 -0800 (PST), dagmargoodboat@yahoo.com > >> wrote: > >> > >> >On Saturday, November 14, 2015 at 11:30:34 AM UTC-5, John Larkin wrote: > >> >> On Sat, 14 Nov 2015 03:03:27 -0800 (PST), dagmargoodboat@yahoo.com > >> >> wrote: > >> >> > >> >> >On Friday, November 13, 2015 at 10:34:07 PM UTC-5, John Larkin wrote: > >> >> >> On Fri, 13 Nov 2015 16:54:29 -0800 (PST), Lasse Langwadt Christensen > >> >> >> <langwadt@fonz.dk> wrote: > >> >> >> > >> >> >> >Den l&#2013266168;rdag den 14. november 2015 kl. 01.22.28 UTC+1 skrev John Larkin: > >> >> >> >> I'm designing a high-voltage pulser, 1200 volts or so, and I'd like to > >> >> >> >> pick off a divided signal for the customer to monitor. > >> >> >> >> > >> >> >> >> https://dl.dropboxusercontent.com/u/53724080/Circuits/Resistors/Pickoff.JPG > >> >> >> >> > >> >> >> >> Rise/fall times will be a few us maybe. > >> >> >> >> > >> >> >> >> I'd like to have the pulse response be pretty good, so the > >> >> >> >> capacitances matter. The OPA171 opamp and R2 have capacitance, roughly > >> >> >> >> 4 pF total, and I guess the 1G 2010 resistor will, too. These have to > >> >> >> >> be balanced at 500:1 to match the resistors. The cap across R2 can be > >> >> >> >> chosen to work, but I don't want a discrete cap across R1. > >> >> >> >> > >> >> >> >> Maybe the 1G resistor has enough self-capacitance that I can pick the > >> >> >> >> lower cap to work. Or maybe I should add some PCB traces to add > >> >> >> >> capacitance across R1. I need about 0.02 pF if, say, I pad the bottom > >> >> >> >> up to 10 pF. > >> >> >> >> > >> >> >> >> This will be a 4-layer board with L2 ground plane, but I can cut out > >> >> >> >> some plane if that would help. > >> >> >> >> > >> >> >> >> Has anyone done something like this? > >> >> >> >> > >> >> >> > > >> >> >> >why such big resistors? > >> >> >> > > >> >> >> >a standard 500:1 scope probe is 10M afaict > >> >> >> > > >> >> >> >why not a string of say 2M resistors and capacitors > >> >> >> > >> >> >> I have rational reasons for wanting a 1G resistor. Even more would be > >> >> >> good, but I can get a 1G 3KV 2010. > >> >> > > >> >> >Wouldn't a trans impedance amp be faster? Then you wouldn't have to move the > >> >> >summing node. You might have to make an ultra-low capacitance buffer, lest the > >> >> >input capacitance make the thing unstable. > >> >> > > >> >> >Cheers, > >> >> >James > >> >> > >> >> That's about a wash, and I'd need to re-invert the TIA output with > >> >> another amp. > >> >> > >> >> The 1G resistor has some (currently unknown) shunt capacitance, and > >> >> that makes a tau that any amplifier has to deal with. If the shunt C > >> >> were zero, an ideal TIA would work. > >> > > >> >You're right, the problem here is peaking, the opposite of the usual TI > >> >amp problem. > >> > > >> >> If I have a reasonable capacitance across the 1G, then the lowside > >> >> compensating cap (either amp config) gets up into the tens or hundreds > >> >> of pF, where I can get a reasonable selection of compensation cap > >> >> choices. > >> >> > >> >> This is just a freebie current monitor so the customer can check that > >> >> the pulse is working. It's not worth extreme measures. > >> > > >> >Then why not change the 2M divider resistor to 200k? 200K * 4pF = 800nS, > >> >problem solved. Make the op-amp stage x10. Or 100k and x20. > >> > >> The parasitic shunt cap across the 1G resistor will differentiate the > >> HV rising edge and still make a pulse overshoot. 0.1 pF and 1 Gohms > >> has a tau of 100 usec > > > >1) Yes, it's differentiated and yes it'll overshoot. But the time constant is > >.1pF and (1G in parallel with 200k), not 1G, so the overshoot is short-lived, > >and maybe even too small to notice, depending on your slew rate. > > > >(The pulse / overshoot is also, technically, not 1,200V, but 1,200V * the > >capacitive divider ratio between .1pF and ~4pF, or about 1/40th * 1,200V). > > > >But we're talking past each other--I've attached a sim file. Look at the > >settling time difference between my suggestion V(A) and the original, V(B). > >V(B_scaled) lets you see the two on the same scale. > > > >2) If it's really .1pF that's horrible; different measures are called for, > >like a diff amp where a 2nd 1G resistor is a.c.-coupled, and subtracts the 1G > >resistor's capacitively-coupled current from the output. > > > >> >> There are PCB techniques for reducing the effective capacitance across > >> >> resistors. I want to increase it! > >> > > >> >Constructing the divider from 500 instances of the same resistor would > >> >automatically balance their shunt capacitances according to the divider > >> >ratio (and look very silly!). > >> > >> I saw an appnote recently, somewhere, for reducing resistor shunt > >> capacitance, by a lot, by filling under the resistor with some topside > >> ground. But that would wreck my high voltage clearance. > >> > >> I think some people do that trick with multiple series resistors, too. > >> > >> The worst way to tune a design is by re-etching PC boards. I don't > >> want to do that. A variable cap or an equivalent pot-controlled > >> capacitance would let my test people tweak the step response, > >> independent of PCB variations. People who don't approve of trimmers > >> will whine, but I am The President, after all. > >> > >> Caddock makes axial thickfilm resistors that have essentially no L or > >> C. One of them can make a high voltage divider, into a 50 ohm scope, > >> that's flat to something like 6 GHz. But I don't think they can do > >> that at 1G ohms. Or in surface mount. > > > > > The waveform at B is good if C4 is 50 pF.
Right, obviously. That's why I put in V(C)--to illustrate the perfectly-sized compensating cap. My point in posting this was to show that my scheme settles 20x faster. But your original values and a 50pF trimcap might be the ideal solution. An approximate compensation cap AND lower equivalent resistance divider might be an alternative. It'll over- or undershoot if there's a capacitance mismatch, but the transient settles out much faster.
> C is fine, but it's only 120 millivolts. > > I just have no idea if C1 is really 0.1 pF.
I'd hope it's 1/5th that or less, but it's not going to be nil; compensation will be needed one way or the other. <snip sim file> Cheers, James Arthur
Effect of Gigohm
and 1/10th environmental stray C

RL

Version 4
SHEET 1 1380 680
WIRE 816 -80 272 -80
WIRE 16 0 -48 0
WIRE 96 0 16 0
WIRE 192 0 96 0
WIRE 272 0 272 -80
WIRE 272 0 192 0
WIRE 384 0 272 0
WIRE 416 0 384 0
WIRE 512 0 496 0
WIRE 528 0 512 0
WIRE 656 0 608 0
WIRE 720 0 656 0
WIRE 816 0 816 -80
WIRE 880 0 816 0
WIRE 912 0 880 0
WIRE 1008 0 992 0
WIRE 1024 0 1008 0
WIRE 1152 0 1104 0
WIRE 1216 0 1152 0
WIRE 96 16 96 0
WIRE 272 16 272 0
WIRE 720 16 720 0
WIRE 1216 16 1216 0
WIRE 16 32 16 0
WIRE 192 32 192 0
WIRE 384 32 384 0
WIRE 880 32 880 0
WIRE -48 96 -48 0
WIRE 16 128 16 96
WIRE 96 128 96 96
WIRE 96 128 16 128
WIRE 192 128 192 96
WIRE 272 128 272 96
WIRE 272 128 192 128
WIRE 384 128 384 96
WIRE 720 128 720 96
WIRE 720 128 384 128
WIRE 880 128 880 96
WIRE 1216 128 1216 96
WIRE 1216 128 880 128
WIRE 96 160 96 128
WIRE 96 160 16 160
WIRE 144 160 96 160
WIRE 272 160 272 128
WIRE 272 160 192 160
WIRE 320 160 272 160
WIRE 720 160 720 128
WIRE 720 160 640 160
WIRE 832 160 720 160
WIRE 1216 160 1216 128
WIRE 1216 160 1136 160
WIRE 1328 160 1216 160
WIRE 96 176 96 160
WIRE 272 176 272 160
WIRE 720 176 720 160
WIRE 1216 176 1216 160
WIRE 16 192 16 160
WIRE 192 192 192 160
WIRE 640 192 640 160
WIRE 1136 192 1136 160
WIRE -48 208 -48 176
WIRE 16 272 16 256
WIRE 192 272 192 256
WIRE 640 272 640 256
WIRE 1136 272 1136 256
WIRE 96 288 96 256
WIRE 272 288 272 256
WIRE 720 288 720 256
WIRE 1216 288 1216 256
FLAG -48 208 0
FLAG 272 288 0
FLAG 192 272 0
FLAG 320 160 A
FLAG 720 288 0
FLAG 640 272 0
FLAG 832 160 A2
FLAG -48 0 V1
FLAG 512 64 0
FLAG 656 64 0
FLAG 1216 288 0
FLAG 1136 272 0
FLAG 1328 160 B2
FLAG 1008 64 0
FLAG 1152 64 0
FLAG 96 288 0
FLAG 16 272 0
FLAG 144 160 B
SYMBOL voltage -48 80 R0
WINDOW 3 -162 235 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 1200 0 2uS 2uS 50uS)
SYMATTR InstName V1
SYMBOL res 256 0 R0
SYMATTR InstName R1
SYMATTR Value 1G
SYMBOL res 256 160 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL cap 176 32 R0
SYMATTR InstName C1
SYMATTR Value .1pF
SYMBOL cap 176 192 R0
SYMATTR InstName C2
SYMATTR Value 1nF
SYMBOL res 704 0 R0
SYMATTR InstName R6
SYMATTR Value 0.33G
SYMBOL res 704 160 R0
SYMATTR InstName R7
SYMATTR Value 100k
SYMBOL cap 368 32 R0
SYMATTR InstName C5
SYMATTR Value .1pF
SYMBOL cap 624 192 R0
SYMATTR InstName C6
SYMATTR Value 1nF
SYMBOL res 512 -16 R90
WINDOW 0 -6 92 VBottom 2
WINDOW 3 -30 34 VTop 2
SYMATTR InstName R8
SYMATTR Value 0.33G
SYMBOL res 624 -16 R90
WINDOW 0 -3 77 VBottom 2
WINDOW 3 -27 20 VTop 2
SYMATTR InstName R9
SYMATTR Value 0.33G
SYMBOL cap 496 0 R0
WINDOW 0 -12 51 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C7
SYMATTR Value .01pF
SYMBOL cap 640 0 R0
WINDOW 0 -22 18 Left 2
WINDOW 3 -42 48 Left 2
SYMATTR InstName C8
SYMATTR Value .01pF
SYMBOL res 1200 0 R0
SYMATTR InstName R3
SYMATTR Value 0.033G
SYMBOL res 1200 160 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 864 32 R0
SYMATTR InstName C3
SYMATTR Value .1pF
SYMBOL cap 1120 192 R0
SYMATTR InstName C4
SYMATTR Value 1nF
SYMBOL res 1008 -16 R90
WINDOW 0 -6 92 VBottom 2
WINDOW 3 -30 34 VTop 2
SYMATTR InstName R5
SYMATTR Value 0.033G
SYMBOL res 1120 -16 R90
WINDOW 0 -3 77 VBottom 2
WINDOW 3 -27 20 VTop 2
SYMATTR InstName R10
SYMATTR Value 0.033G
SYMBOL cap 992 0 R0
WINDOW 0 -12 51 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C9
SYMATTR Value .01pF
SYMBOL cap 1136 0 R0
WINDOW 0 -22 18 Left 2
WINDOW 3 -42 48 Left 2
SYMATTR InstName C10
SYMATTR Value .01pF
SYMBOL res 80 0 R0
SYMATTR InstName R11
SYMATTR Value 0.1G
SYMBOL res 80 160 R0
SYMATTR InstName R12
SYMATTR Value 10k
SYMBOL cap 0 32 R0
SYMATTR InstName C11
SYMATTR Value .1pF
SYMBOL cap 0 192 R0
SYMATTR InstName C12
SYMATTR Value 1nF
TEXT 32 360 Left 2 !.tran 150uS

.............plot file

[Transient Analysis]
{
   Npanes: 1
   {
      traces: 5 {524290,0,"V(a)*1.05"} {589831,0,"V(v1)/10000"}
{524291,0,"V(a2)*1.1"} {589830,0,"V(b)*.95"} {524292,0,"V(b2)*.9"}
      X: ('&#2013266101;',0,0,1e-005,0.00015)
      Y[0]: ('m',0,-0.01,0.01,0.14)
      Y[1]: ('_',0,1e+308,0,-1e+308)
      Volts: ('m',0,0,0,-0.01,0.01,0.14)
      Log: 0 0 0
      GridStyle: 1
   }
}
On Sun, 15 Nov 2015 14:22:43 -0800 (PST), tabbypurr@gmail.com wrote:

>On Sunday, 15 November 2015 20:42:03 UTC, John Larkin wrote: >> >> On Sun, 15 Nov 2015 nt wrote: >> >On Sunday, 15 November 2015 16:27:39 UTC, John Larkin wrote: >> >> On Sun, 15 Nov 2015 02:47:06 -0800 (PST), nt wrote: >> >> >On Sunday, 15 November 2015 02:19:14 UTC, John Larkin wrote: >> >> >> On Sat, 14 Nov 2015 16:04:44 -0800 (PST), nt wrote: > >> >> >> >Preset pots are a long term reliability disaster. >> >> >> >> >> >> Why? >> >> > >> >> >I'm not sure why, but experience shows they are. It's why they've fallen out of favour. >> >> >> >> Pots are fine as long as you don't expect more than about 0.25% >> >> longterm stability. In my current situation, I'm just trying to make a >> >> pulse look good on a scope, so a few per cent of the pot range would >> >> be close enough. >> > >> >Pots aren't too bad, little presets are >> >> What is a "little preset"? > >A preset pot has no shaft, is soldered direct to PCB and twiddled before the appliance leaves the factory, then never touched again. Those have really lousy long term reliability, which is one reason why they disappeared from most appliances. > > >NT
OK, we call that a "trimpot." My records show that we've used over 90,000 trimpots so far, mostly surface mount. I don't think they have caused any problems. We buy sealed, cermet trimpots. Old unsealed carbon pots tended to get flakey. A decent single-turn trimpot can be set, with care, to 0.1% of its range, and pretty much stays there if you whack the board. 0.5% is a very conservative design assumption, easy to set. I agree that trimpots are over-used, especially in online amateur schematics. But sometimes you need to set a gain or something, where dacs and eeproms and software aren't convenient. The nonvolatile digital pots still need a programmer and software, and most are bandwidth limited to not much past audio. We use one little pot that works fine up to 1 GHz or so. That's a lot of performance for seven cents.
On 2015-11-15, John Larkin <jjlarkin@highlandtechnology.com> wrote:
> On Sun, 15 Nov 2015 10:43:05 -0800 (PST), tabbypurr@gmail.com wrote: > >>On Sunday, 15 November 2015 16:27:39 UTC, John Larkin wrote: >>> On Sun, 15 Nov 2015 02:47:06 -0800 (PST), nt wrote: >>> >>> >On Sunday, 15 November 2015 02:19:14 UTC, John Larkin wrote: >>> >> On Sat, 14 Nov 2015 16:04:44 -0800 (PST), nt wrote: >>> >> >On Saturday, 14 November 2015 22:02:42 UTC, John Larkin wrote: >>> >> >> On Sat, 14 Nov 2015 13:30:40 -0800 (PST), Phil Hobbs >>> >> >> <pcdhobbs@gmail.com> wrote: >>> >> >> >>> >> >> >The major imponderable will probably be the poorly-controlled epsilon of the board. If you make the air gaps big enough, you can probably control that well enough. >>> >> > >>> >> >> A pot or a trimmer cap makes sense. I get pushback from young things >>> >> >> that are prejudiced against pots. But really, when testing is making >>> >> >> pulses, it would only take them a few seconds to turn a pot to make >>> >> >> the pulses look right. >>> >> > >>> >> >Preset pots are a long term reliability disaster. >>> >> >>> >> Why? >>> > >>> >I'm not sure why, but experience shows they are. It's why they've fallen out of favour. >>> >>> Pots are fine as long as you don't expect more than about 0.25% >>> longterm stability. In my current situation, I'm just trying to make a >>> pulse look good on a scope, so a few per cent of the pot range would >>> be close enough. >> >>Pots aren't too bad, little presets are > > > What is a "little preset"? >
Less than 10c each in quantity eg: digikey 490-7795-2-ND -- \_(&#12484;)_
On 2015-11-15 23:34, John Larkin wrote:
> On Sun, 15 Nov 2015 14:11:07 -0800 (PST), dagmargoodboat@yahoo.com > wrote: >
[snip!
> > > The waveform at B is good if C4 is 50 pF. > > C is fine, but it's only 120 millivolts. > > I just have no idea if C1 is really 0.1 pF. >
I got a fair estimate of the parasitic capacitance of a 1206 SMD resistor by just assuming it's a flat plate capacitor with all the field confined to the SiO2 substrate. I calculated 30fF and subsequent measurement indicated 50fF. For what it's worth.. Jeroen Belleman
> confined to the SiO2 substrate
I thought they were usually Al2O3. Cheers Phil Hobbs
>I saw an appnote recently, somewhere, for reducing resistor shunt >capacitance, by a lot, by filling under the resistor with some topside >ground. But that would wreck my high voltage clearance.
That's basically the three-terminal capacitance measurement trick. Like the Hi/Lo Z trick, it helps the frequency response but not the noise, and the C loading to ground may be a problem in itself. I much prefer to make the capacitance stable and predictable using air. Cheers Phil Hobbs
On 2015-11-16 13:59, Phil Hobbs wrote:
>> confined to the SiO2 substrate > > I thought they were usually Al2O3. > > Cheers > > Phil Hobbs >
Erm, yes. That's my reward for trying to make sense on a Monday morning before coffee. Jeroen Belleman