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LTspice simulation is taking too long to run

Started by MUHAMMAD FAHAD BHUTTA August 14, 2015
Greetings people !

So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple. 

Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using Instrument Amplifier to get better result but that is not a necessity)

Now, the output is not as what we want (that is another issue with Quantizer but we can solve that later) but the time LTspice is taking to simulate the whole circuit is round about 10 minutes or something which is kind of an unacceptable ( giving a look at the transient response parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to start saving data, max time step 1ms , skip initial operating point solution; True). This is the best transient settings I did and it is still taking around 10minutes. And without this setting, the simulation time grows relatively high.

Also , the CPU usage during simulation is 100% (means other programs are hard to run). Although the machine I am using is a SAMSUNG series 5 ultra book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is not the problem with CPU to handle a low level simulation.(BTW I burrowed it from a friend for some time till I get my new DELL XPS 13"...So don't blame me on buying an AMD)

One more thing is that I used the simulation on my friend's core 2 duo desktop and it is taking almost the same time. Also on my friend's notebook which has 2nd generation core i3 processor and still the same time taken to simulate. RAM is not the issue though !

So, Can any one please tell me what are the reasons? Is the circuit not properly optimized? Am I giving the wrong transient parameters ? Is this the CPU problem ? Any advice perhaps because I am relatively new to this spice simulation environment (only a month of little bit of experience).

Thanks in advance :)
On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
<111619124@umt.edu.pk> wrote:

>Greetings people ! > >So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple. > >Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using Instrument Amplifier to get better result but that is not a necessity) > >Now, the output is not as what we want (that is another issue with Quantizer but we can solve that later) but the time LTspice is taking to simulate the whole circuit is round about 10 minutes or something which is kind of an unacceptable ( giving a look at the transient response parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to start saving data, max time step 1ms , skip initial operating point solution; True). This is the best transient settings I did and it is still taking around 10minutes. And without this setting, the simulation time grows relatively high. > >Also , the CPU usage during simulation is 100% (means other programs are hard to run). Although the machine I am using is a SAMSUNG series 5 ultra book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is not the problem with CPU to handle a low level simulation.(BTW I burrowed it from a friend for some time till I get my new DELL XPS 13"...So don't blame me on buying an AMD) > >One more thing is that I used the simulation on my friend's core 2 duo desktop and it is taking almost the same time. Also on my friend's notebook which has 2nd generation core i3 processor and still the same time taken to simulate. RAM is not the issue though ! > >So, Can any one please tell me what are the reasons? Is the circuit not properly optimized? Am I giving the wrong transient parameters ? Is this the CPU problem ? Any advice perhaps because I am relatively new to this spice simulation environment (only a month of little bit of experience). > >Thanks in advance :)
Well, post your circuit! The thing below is a 1st order delta-sigma used to make an analog signal isolator, to get an analog signal up into an isolated channel. It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my ancient HP machine. We're not going to do it this way, but it was interesting. We'll use a DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI interface. Version 4 SHEET 1 1572 700 WIRE 1360 -16 1264 -16 WIRE 1408 -16 1360 -16 WIRE 1264 32 1264 -16 WIRE 192 48 128 48 WIRE 224 48 192 48 WIRE 416 48 352 48 WIRE 480 48 416 48 WIRE 592 48 528 48 WIRE 656 48 592 48 WIRE 912 48 656 48 WIRE 1152 48 1072 48 WIRE 1216 48 1152 48 WIRE 848 96 816 96 WIRE 912 96 848 96 WIRE 1216 96 1184 96 WIRE 128 112 128 48 WIRE 352 112 352 48 WIRE 528 112 528 48 WIRE 656 112 656 48 WIRE 816 112 816 96 WIRE 480 128 480 48 WIRE 1184 144 1184 96 WIRE 1264 144 1264 112 WIRE 1328 224 1264 224 WIRE 1408 224 1328 224 WIRE 128 240 128 192 WIRE 352 240 352 192 WIRE 480 240 480 176 WIRE 528 240 528 192 WIRE 656 240 656 176 WIRE 816 240 816 192 WIRE 1264 272 1264 224 WIRE 1152 288 1120 288 WIRE 1216 288 1152 288 WIRE 1216 336 1184 336 WIRE 1264 400 1264 352 WIRE 176 480 160 480 WIRE 224 480 176 480 WIRE 384 480 304 480 WIRE 480 480 384 480 WIRE 688 480 560 480 WIRE 816 480 768 480 WIRE 864 480 816 480 WIRE 1008 480 944 480 WIRE 1104 480 1008 480 WIRE 1184 480 1184 336 WIRE 1248 480 1184 480 WIRE 1328 480 1248 480 WIRE 384 528 384 480 WIRE 560 528 560 480 WIRE 816 528 816 480 WIRE 1008 528 1008 480 WIRE 1184 528 1184 480 WIRE 480 544 480 480 WIRE 512 544 480 544 WIRE 1104 544 1104 480 WIRE 1136 544 1104 544 WIRE 512 592 480 592 WIRE 1136 592 1104 592 WIRE 384 656 384 592 WIRE 480 656 480 592 WIRE 560 656 560 608 WIRE 816 656 816 592 WIRE 864 656 816 656 WIRE 880 656 864 656 WIRE 1008 656 1008 592 WIRE 1104 656 1104 592 WIRE 1184 656 1184 608 FLAG 128 240 0 FLAG 192 48 IN FLAG 352 240 0 FLAG 480 240 0 FLAG 528 240 0 FLAG 656 240 0 FLAG 416 48 SUB FLAG 592 48 INTEG FLAG 816 240 0 FLAG 1264 144 0 FLAG 1184 144 0 FLAG 1152 48 FF FLAG 848 96 CLK FLAG 1360 -16 DS FLAG 384 656 0 FLAG 480 656 0 FLAG 560 656 0 FLAG 1008 656 0 FLAG 1104 656 0 FLAG 1184 656 0 FLAG 1248 480 OUT FLAG 176 480 DS FLAG 864 656 OUT FLAG 1264 400 0 FLAG 1328 224 ERR FLAG 1152 288 IN SYMBOL voltage 128 96 R0 WINDOW 0 55 64 Left 2 WINDOW 3 29 104 Left 2 SYMATTR InstName V1 SYMATTR Value 0.657 SYMBOL bv 352 96 R0 WINDOW 0 -66 118 Left 2 WINDOW 3 -101 196 Left 2 SYMATTR InstName B1 SYMATTR Value V= ( V(IN) - V(FF) ) SYMBOL g 528 96 R0 WINDOW 0 46 45 Left 2 WINDOW 3 52 79 Left 2 SYMATTR InstName G1 SYMATTR Value 1m SYMBOL cap 640 112 R0 WINDOW 0 52 25 Left 2 WINDOW 3 56 54 Left 2 SYMATTR InstName C1 SYMATTR Value 1&#2013266101; SYMBOL Digital\\dflop 992 0 R0 WINDOW 0 -15 61 Left 2 SYMATTR InstName A1 SYMBOL voltage 816 96 R0 WINDOW 0 16 118 Left 2 WINDOW 3 -123 198 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(0 1 0 0 0 10n 10u) SYMBOL e 1264 16 R0 WINDOW 0 61 42 Left 2 WINDOW 3 66 78 Left 2 SYMATTR InstName E1 SYMATTR Value 1 SYMBOL res 320 464 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 8.87K SYMBOL cap 368 528 R0 WINDOW 0 -60 40 Left 2 WINDOW 3 -66 75 Left 2 SYMATTR InstName C2 SYMATTR Value 2.2n SYMBOL e 560 512 R0 WINDOW 0 61 42 Left 2 WINDOW 3 60 83 Left 2 SYMATTR InstName E2 SYMATTR Value 1 SYMBOL res 784 464 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 2.21K SYMBOL res 960 464 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 17.4K SYMBOL e 1184 512 R0 WINDOW 0 61 42 Left 2 WINDOW 3 66 78 Left 2 SYMATTR InstName E3 SYMATTR Value 1 SYMBOL cap 800 528 R0 WINDOW 0 -58 47 Left 2 WINDOW 3 -69 80 Left 2 SYMATTR InstName C3 SYMATTR Value 100n SYMBOL cap 992 528 R0 WINDOW 0 -56 55 Left 2 WINDOW 3 -59 85 Left 2 SYMATTR InstName C4 SYMATTR Value 4.7n SYMBOL e 1264 256 R0 WINDOW 0 61 42 Left 2 WINDOW 3 66 78 Left 2 SYMATTR InstName E4 SYMATTR Value 100 TEXT 288 -8 Left 2 ;SUBTRACT TEXT 520 -8 Left 2 ;INTEGRATOR TEXT 1200 -56 Left 2 ;ISOLATOR TEXT 944 -56 Left 2 ;FLIPFLOP TEXT 640 -128 Left 2 !.tran 0 20m 0 50n uic TEXT 104 -8 Left 2 ;INPUT TEXT 864 248 Left 2 ;100 KHz TEXT 384 408 Left 2 ;LPF 3P 1KHz 0.2 dB CHEBY TEXT 240 -128 Left 2 ;Delta-Sigma Isolator TEXT 288 -88 Left 2 ;JL July 2015 -- John Larkin Highland Technology, Inc lunatic fringe electronics jlarkin att highlandtechnology dott com http://www.highlandtechnology.com

"John Larkin"  wrote in message 
news:u99tsahv6gdghs26qssrtmud004iu2f8h6@4ax.com...

On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA
<111619124@umt.edu.pk> wrote:

>Greetings people ! > >So lately, I have been working on my Sigma Delta ADC and before going >advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital >output) . The circuit is quite simple. > >Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> >Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of >Difference Amplifier (I am using Instrument Amplifier to get better result >but that is not a necessity) > >Now, the output is not as what we want (that is another issue with >Quantizer but we can solve that later) but the time LTspice is taking to >simulate the whole circuit is round about 10 minutes or something which is >kind of an unacceptable ( giving a look at the transient response >parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to >start saving data, max time step 1ms , skip initial operating point >solution; True). This is the best transient settings I did and it is still >taking around 10minutes. And without this setting, the simulation time >grows relatively high. > >Also , the CPU usage during simulation is 100% (means other programs are >hard to run). Although the machine I am using is a SAMSUNG series 5 ultra >book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is >not the problem with CPU to handle a low level simulation.(BTW I burrowed >it from a friend for some time till I get my new DELL XPS 13"...So don't >blame me on buying an AMD) > >One more thing is that I used the simulation on my friend's core 2 duo >desktop and it is taking almost the same time. Also on my friend's notebook >which has 2nd generation core i3 processor and still the same time taken to >simulate. RAM is not the issue though ! > >So, Can any one please tell me what are the reasons? Is the circuit not >properly optimized? Am I giving the wrong transient parameters ? Is this >the CPU problem ? Any advice perhaps because I am relatively new to this >spice simulation environment (only a month of little bit of experience). > >Thanks in advance :)
Well, post your circuit! The thing below is a 1st order delta-sigma used to make an analog signal isolator, to get an analog signal up into an isolated channel. It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my ancient HP machine. We're not going to do it this way, but it was interesting. We'll use a DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI interface. 5 sec. sim time with Intel I7 core and SSD Cheers, Harry
On Sat, 15 Aug 2015 12:30:01 -0700, "Harry D" <harryd@tdsystems.org>
wrote:

> > >"John Larkin" wrote in message >news:u99tsahv6gdghs26qssrtmud004iu2f8h6@4ax.com... > >On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA ><111619124@umt.edu.pk> wrote: > >>Greetings people ! >> >>So lately, I have been working on my Sigma Delta ADC and before going >>advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital >>output) . The circuit is quite simple. >> >>Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> >>Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of >>Difference Amplifier (I am using Instrument Amplifier to get better result >>but that is not a necessity) >> >>Now, the output is not as what we want (that is another issue with >>Quantizer but we can solve that later) but the time LTspice is taking to >>simulate the whole circuit is round about 10 minutes or something which is >>kind of an unacceptable ( giving a look at the transient response >>parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to >>start saving data, max time step 1ms , skip initial operating point >>solution; True). This is the best transient settings I did and it is still >>taking around 10minutes. And without this setting, the simulation time >>grows relatively high. >> >>Also , the CPU usage during simulation is 100% (means other programs are >>hard to run). Although the machine I am using is a SAMSUNG series 5 ultra >>book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is >>not the problem with CPU to handle a low level simulation.(BTW I burrowed >>it from a friend for some time till I get my new DELL XPS 13"...So don't >>blame me on buying an AMD) >> >>One more thing is that I used the simulation on my friend's core 2 duo >>desktop and it is taking almost the same time. Also on my friend's notebook >>which has 2nd generation core i3 processor and still the same time taken to >>simulate. RAM is not the issue though ! >> >>So, Can any one please tell me what are the reasons? Is the circuit not >>properly optimized? Am I giving the wrong transient parameters ? Is this >>the CPU problem ? Any advice perhaps because I am relatively new to this >>spice simulation environment (only a month of little bit of experience). >> >>Thanks in advance :) > > >Well, post your circuit! > >The thing below is a 1st order delta-sigma used to make an analog >signal isolator, to get an analog signal up into an isolated channel. >It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my >ancient HP machine. > >We're not going to do it this way, but it was interesting. We'll use a >DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI >interface. > > >5 sec. sim time with Intel I7 core and SSD > >Cheers, Harry >
"The thing below" ???? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Sat, 15 Aug 2015 12:30:01 -0700, "Harry D" <harryd@tdsystems.org>
wrote:

> > >"John Larkin" wrote in message >news:u99tsahv6gdghs26qssrtmud004iu2f8h6@4ax.com... > >On Fri, 14 Aug 2015 18:59:47 -0700 (PDT), MUHAMMAD FAHAD BHUTTA ><111619124@umt.edu.pk> wrote: > >>Greetings people ! >> >>So lately, I have been working on my Sigma Delta ADC and before going >>advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital >>output) . The circuit is quite simple. >> >>Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> >>Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of >>Difference Amplifier (I am using Instrument Amplifier to get better result >>but that is not a necessity) >> >>Now, the output is not as what we want (that is another issue with >>Quantizer but we can solve that later) but the time LTspice is taking to >>simulate the whole circuit is round about 10 minutes or something which is >>kind of an unacceptable ( giving a look at the transient response >>parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to >>start saving data, max time step 1ms , skip initial operating point >>solution; True). This is the best transient settings I did and it is still >>taking around 10minutes. And without this setting, the simulation time >>grows relatively high. >> >>Also , the CPU usage during simulation is 100% (means other programs are >>hard to run). Although the machine I am using is a SAMSUNG series 5 ultra >>book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is >>not the problem with CPU to handle a low level simulation.(BTW I burrowed >>it from a friend for some time till I get my new DELL XPS 13"...So don't >>blame me on buying an AMD) >> >>One more thing is that I used the simulation on my friend's core 2 duo >>desktop and it is taking almost the same time. Also on my friend's notebook >>which has 2nd generation core i3 processor and still the same time taken to >>simulate. RAM is not the issue though ! >> >>So, Can any one please tell me what are the reasons? Is the circuit not >>properly optimized? Am I giving the wrong transient parameters ? Is this >>the CPU problem ? Any advice perhaps because I am relatively new to this >>spice simulation environment (only a month of little bit of experience). >> >>Thanks in advance :) > > >Well, post your circuit! > >The thing below is a 1st order delta-sigma used to make an analog >signal isolator, to get an analog signal up into an isolated channel. >It runs 20 ms of sim in about 30 seconds with a 50 ns time step, on my >ancient HP machine. > >We're not going to do it this way, but it was interesting. We'll use a >DAC1220 (which is an integrated D-S dac) with an ADUM1400 isolated SPI >interface. > > >5 sec. sim time with Intel I7 core and SSD > >Cheers, Harry >
My new Dell (they made me upgrade!) runs Spice about 5x faster than my old HP, so that's in the ballpark. The SSD may help a bit, saving the .RAW data faster. I'm fine-tuning the Dell at work before we clone it to my new home and cabin machines. I'm considering installing Classic Shell to zap the few remaining Win7 annoyances. -- John Larkin Highland Technology, Inc lunatic fringe electronics jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Sat, 15 Aug 2015 13:40:42 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>I'm fine-tuning the Dell at work before we clone it to my new home and >cabin machines.
A word of caution. There are numerous SSD tuning guides and programs found on the internet. They vary from a few obvious and conservative tweaks, to massive overkill with some potentially detrimental to performance tweaks. For example, several such guides suggest disabling system restore, which I consider a lousy idea. If your SSD includes tuning software, such as Samsung Magician, I suggest you use it. <http://www.samsung.com/global/business/semiconductor/minisite/SSD/global/html/support/downloads.html>\ Also use the program to check if your SSD is accumulating too many bad blocks, and to check for firmware updates. For Windoze 7, I'm still undecided on which guide to follow. So far this is the most reasonable that I've found and followed: <http://www.disk-partition.com/kb/tips-ssd-optimization-windows7-1.html> You also need to test if your SSD partitions are aligned on 4K blocks. The easiest test uses "AS SSD" benchmark: <http://www.alex-is.de/PHP/fusion/downloads.php?download_id=9> It should look like this: <http://superuser.com/questions/718505/is-my-ssd-disk-aligned-to-4k-sectors-and-if-not-how-do-i-fix-it> As long as your SSD was formatted with Vista, Win 7 or later, you're probably ok. (I had one that was running XP which took a while, but worked once I decoded the instructions).
>I'm considering installing Classic Shell to zap the >few remaining Win7 annoyances.
Just do it. It's painless: <http://www.classicshell.net/features/> You can also temporarily disabled it if it gets in the way, hit <shift><click> to temporarily revert to the Microsoft start thing, or uninstall it if you hate it. The one annoyance that it fixes for me is removing the wiggly icons from the Win 10 start screen. Consider yourself fortunate not to have a wiggly icons start screen in Win 7. -- Jeff Liebermann jeffl@cruzio.com 150 Felker St #D http://www.LearnByDestroying.com Santa Cruz CA 95060 http://802.11junk.com Skype: JeffLiebermann AE6KS 831-336-2558
On Saturday, 15 August 2015 06:59:56 UTC+5, MUHAMMAD FAHAD BHUTTA  wrote:
> Greetings people ! > > So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple. > > Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using Instrument Amplifier to get better result but that is not a necessity) > > Now, the output is not as what we want (that is another issue with Quantizer but we can solve that later) but the time LTspice is taking to simulate the whole circuit is round about 10 minutes or something which is kind of an unacceptable ( giving a look at the transient response parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to start saving data, max time step 1ms , skip initial operating point solution; True). This is the best transient settings I did and it is still taking around 10minutes. And without this setting, the simulation time grows relatively high. > > Also , the CPU usage during simulation is 100% (means other programs are hard to run). Although the machine I am using is a SAMSUNG series 5 ultra book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is not the problem with CPU to handle a low level simulation.(BTW I burrowed it from a friend for some time till I get my new DELL XPS 13"...So don't blame me on buying an AMD) > > One more thing is that I used the simulation on my friend's core 2 duo desktop and it is taking almost the same time. Also on my friend's notebook which has 2nd generation core i3 processor and still the same time taken to simulate. RAM is not the issue though ! > > So, Can any one please tell me what are the reasons? Is the circuit not properly optimized? Am I giving the wrong transient parameters ? Is this the CPU problem ? Any advice perhaps because I am relatively new to this spice simulation environment (only a month of little bit of experience). > > Thanks in advance :)
Okay so here is the 8x3 encoder I am working on right now ( which I will be installing after Delta-Sigma Modulator. http://sub.allaboutcircuits.com/images/04258.png And here is the netlist * C:\Program Files (x86)\LTC\LTspiceIV\Draft3.asc R1 REF N005 100 R2 N005 N008 100 R3 N008 N011 100 R4 N011 N014 100 R5 N014 N017 100 R6 N017 N020 100 R7 N020 N023 100 R8 N023 0 100 XU1 IN N005 N002 N003 N004 LT1007 XU2 IN N008 N002 N003 N007 LT1007 XU3 IN N011 N002 N003 N010 LT1007 XU4 IN N014 N002 N003 N013 LT1007 XU5 IN N017 N002 N003 N016 LT1007 XU6 IN N020 N002 N003 N019 LT1007 XU7 IN N023 N002 N003 N022 LT1007 XU8 0 N004 N001 XOR XU9 N004 N007 N006 XOR XU10 N007 N010 N009 XOR XU11 N010 N013 N012 XOR XU12 N013 N016 N015 XOR XU13 N016 N019 N018 XOR XU14 N019 N022 N021 XOR D1 N001 LSB 1N4148 D2 N001 2SB 1N4148 D3 N001 MSB 1N4148 R9 MSB 0 1000 R10 2SB 0 1000 R11 LSB 0 1000 D4 N006 MSB 1N4148 D5 N006 2SB 1N4148 D6 N009 MSB 1N4148 D7 N009 LSB 1N4148 D8 N012 MSB 1N4148 D9 N015 2SB 1N4148 D10 N015 LSB 1N4148 D11 N018 2SB 1N4148 D12 N021 LSB 1N4148 V1 N002 0 7 V2 0 N003 1 .model D D .lib C:\Program Files (x86)\LTC\LTspiceIV\lib\cmp\standard.dio * MSB * LSB .lib C:\Users\Ziaullah\Desktop\XOR\XOR.lib .lib LTC.lib .backanno .end I am using XOR gate symbol I made using NOT , AND, OR gates (AND OR using NAND NOR and NOT) https://asicdigitaldesign.files.wordpress.com/2007/05/high-z_solution_02.png which in turn were symbolized by myself using Psudo-NMOS logic. Now the circuit is taking like 10 minutes or something to simulate 20us of waveform....where am I missing ? I have made a 2-bit encoder and it takes much less time for simulation of same amount of time. The worries are that I need to install this circuit after Sigma - Delta modulator , so most probably it will take around 20-30 minutes which is quite unacceptable ! Please guide me as I am new to spice environment. Thanks again ! Also, before simulation starts, a line comes for 3-4 minutes saying "Parsing 475 circuit elements". What does that mean ? P.S :- If you have any working 2-3bit (or more ) Delta sigma ADC , please do post it. I will use it as a reference :) Thanks
On Sat, 15 Aug 2015 18:39:27 -0700, Jeff Liebermann <jeffl@cruzio.com>
wrote:

>On Sat, 15 Aug 2015 13:40:42 -0700, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>I'm fine-tuning the Dell at work before we clone it to my new home and >>cabin machines. > >A word of caution. There are numerous SSD tuning guides and programs >found on the internet. They vary from a few obvious and conservative >tweaks, to massive overkill with some potentially detrimental to >performance tweaks. For example, several such guides suggest >disabling system restore, which I consider a lousy idea. > >If your SSD includes tuning software, such as Samsung Magician, I >suggest you use it. ><http://www.samsung.com/global/business/semiconductor/minisite/SSD/global/html/support/downloads.html>\ >Also use the program to check if your SSD is accumulating too many bad >blocks, and to check for firmware updates. > >For Windoze 7, I'm still undecided on which guide to follow. So far >this is the most reasonable that I've found and followed: ><http://www.disk-partition.com/kb/tips-ssd-optimization-windows7-1.html> > >You also need to test if your SSD partitions are aligned on 4K blocks. >The easiest test uses "AS SSD" benchmark: ><http://www.alex-is.de/PHP/fusion/downloads.php?download_id=9> >It should look like this: ><http://superuser.com/questions/718505/is-my-ssd-disk-aligned-to-4k-sectors-and-if-not-how-do-i-fix-it> >As long as your SSD was formatted with Vista, Win 7 or later, you're >probably ok. (I had one that was running XP which took a while, but >worked once I decoded the instructions). > >>I'm considering installing Classic Shell to zap the >>few remaining Win7 annoyances. > >Just do it. It's painless: ><http://www.classicshell.net/features/> >You can also temporarily disabled it if it gets in the way, hit ><shift><click> to temporarily revert to the Microsoft start thing, or >uninstall it if you hate it. The one annoyance that it fixes for me >is removing the wiggly icons from the Win 10 start screen. Consider >yourself fortunate not to have a wiggly icons start screen in Win 7.
We have raid hdds in the new Dells, but no ssds. The built-in "classic" desktop is pretty good in Win7; it kills the absurd Aero thing, so you can actually see most of the icons. I miss not seeing file/folder sizes at the botttom of the Explorer panes, and the up-directory arrow. -- John Larkin Highland Technology, Inc lunatic fringe electronics jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On 8/15/2015 11:27 PM, MUHAMMAD FAHAD BHUTTA wrote:
> On Saturday, 15 August 2015 06:59:56 UTC+5, MUHAMMAD FAHAD BHUTTA wrote: >> Greetings people ! >> >> So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple. >> >> Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using Instrument Amplifier to get better result but that is not a necessity) >> >> Now, the output is not as what we want (that is another issue with Quantizer but we can solve that later) but the time LTspice is taking to simulate the whole circuit is round about 10 minutes or something which is kind of an unacceptable ( giving a look at the transient response parameters are this ;tran 0 100m 95m 1m uic (100ms stop time, 95ms time to start saving data, max time step 1ms , skip initial operating point solution; True). This is the best transient settings I did and it is still taking around 10minutes. And without this setting, the simulation time grows relatively high. >> >> Also , the CPU usage during simulation is 100% (means other programs are hard to run). Although the machine I am using is a SAMSUNG series 5 ultra book with an AMD A6-4455M (2 CPUS-2.1 GHZ each I believe )I believe it is not the problem with CPU to handle a low level simulation.(BTW I burrowed it from a friend for some time till I get my new DELL XPS 13"...So don't blame me on buying an AMD) >> >> One more thing is that I used the simulation on my friend's core 2 duo desktop and it is taking almost the same time. Also on my friend's notebook which has 2nd generation core i3 processor and still the same time taken to simulate. RAM is not the issue though ! >> >> So, Can any one please tell me what are the reasons? Is the circuit not properly optimized? Am I giving the wrong transient parameters ? Is this the CPU problem ? Any advice perhaps because I am relatively new to this spice simulation environment (only a month of little bit of experience). >> >> Thanks in advance :) > > Okay so here is the 8x3 encoder I am working on right now ( which I will be installing after Delta-Sigma Modulator. > > http://sub.allaboutcircuits.com/images/04258.png > > And here is the netlist > > * C:\Program Files (x86)\LTC\LTspiceIV\Draft3.asc > R1 REF N005 100 > R2 N005 N008 100 > R3 N008 N011 100 > R4 N011 N014 100 > R5 N014 N017 100 > R6 N017 N020 100 > R7 N020 N023 100 > R8 N023 0 100 > XU1 IN N005 N002 N003 N004 LT1007 > XU2 IN N008 N002 N003 N007 LT1007 > XU3 IN N011 N002 N003 N010 LT1007 > XU4 IN N014 N002 N003 N013 LT1007 > XU5 IN N017 N002 N003 N016 LT1007 > XU6 IN N020 N002 N003 N019 LT1007 > XU7 IN N023 N002 N003 N022 LT1007 > XU8 0 N004 N001 XOR > XU9 N004 N007 N006 XOR > XU10 N007 N010 N009 XOR > XU11 N010 N013 N012 XOR > XU12 N013 N016 N015 XOR > XU13 N016 N019 N018 XOR > XU14 N019 N022 N021 XOR > D1 N001 LSB 1N4148 > D2 N001 2SB 1N4148 > D3 N001 MSB 1N4148 > R9 MSB 0 1000 > R10 2SB 0 1000 > R11 LSB 0 1000 > D4 N006 MSB 1N4148 > D5 N006 2SB 1N4148 > D6 N009 MSB 1N4148 > D7 N009 LSB 1N4148 > D8 N012 MSB 1N4148 > D9 N015 2SB 1N4148 > D10 N015 LSB 1N4148 > D11 N018 2SB 1N4148 > D12 N021 LSB 1N4148 > V1 N002 0 7 > V2 0 N003 1 > .model D D > .lib C:\Program Files (x86)\LTC\LTspiceIV\lib\cmp\standard.dio > * MSB > * LSB > .lib C:\Users\Ziaullah\Desktop\XOR\XOR.lib > .lib LTC.lib > .backanno > .end > > I am using XOR gate symbol I made using NOT , AND, OR gates (AND OR using NAND NOR and NOT) > https://asicdigitaldesign.files.wordpress.com/2007/05/high-z_solution_02.png > > which in turn were symbolized by myself using Psudo-NMOS logic. > > Now the circuit is taking like 10 minutes or something to simulate 20us of waveform....where am I missing ? I have made a 2-bit encoder and it takes much less time for simulation of same amount of time. > > The worries are that I need to install this circuit after Sigma - Delta modulator , so most probably it will take around 20-30 minutes which is quite unacceptable ! > > Please guide me as I am new to spice environment. Thanks again ! > > Also, before simulation starts, a line comes for 3-4 minutes saying "Parsing 475 circuit elements". What does that mean ? > > P.S :- If you have any working 2-3bit (or more ) Delta sigma ADC , please do post it. I will use it as a reference :) Thanks >
Try running a DC Sweep and see what you get.
Well guys, here is the NETLIST of my 3-bit ADC....sure it is not a very good looking one (my first complete ADC with only 2 weeks of LTspice experience) but it works :)
Here is the NETLIST. Please run it and tell me how much time does the simulation takes for , say , 10ms transient. Please tell ASAP :)


* D:\3 bit sigma delta modulator.asc
M1 N113 N002 N116 N116 BSB012N03LX3
M2 N116 N020 0 0 BSB012N03LX3
M3 P001 N020 0 0 BSB012N03LX3
M4 N098 N047 N102 N102 BSB012N03LX3
M7 N012 N008 P002 P002 BSB012N03LX3
M8 P002 N019 P003 P003 BSB012N03LX3
M9 N032 N004 P004 P004 BSB012N03LX3
M10 P004 N006 P005 P005 BSB012N03LX3
M12 N001 0 N113 N113 FDS4435A
M13 N001 0 N098 N098 FDS4435A
M14 N001 0 N012 N012 FDS4435A
M15 N001 0 N032 N032 FDS4435A
M16 P005 N024 P006 P006 BSB012N03LX3
M17 P006 N020 0 0 BSB012N03LX3
M18 N011 N016 N018 N018 BSB012N03LX3
M20 N018 N020 0 0 BSB012N03LX3
M22 N037 N047 N058 N058 BSB012N03LX3
M24 N058 N020 0 0 BSB012N03LX3
M26 N100 N003 P007 P007 BSB012N03LX3
M27 P007 N020 0 0 BSB012N03LX3
M28 N114 N002 P008 P008 BSB012N03LX3
M29 P008 N020 0 0 BSB012N03LX3
M30 N010 N007 P009 P009 BSB012N03LX3
M31 P009 N006 P010 P010 BSB012N03LX3
M32 P010 N005 P011 P011 BSB012N03LX3
M33 P011 N020 0 0 BSB012N03LX3
M34 N036 N004 P012 P012 BSB012N03LX3
M35 P012 N006 P013 P013 BSB012N03LX3
M36 P013 N005 P014 P014 BSB012N03LX3
M37 P014 N020 0 0 BSB012N03LX3
M39 N103 N003 P015 P015 BSB012N03LX3
M40 P015 N020 0 0 BSB012N03LX3
M41 N115 N002 P016 P016 BSB012N03LX3
M42 P016 N020 0 0 BSB012N03LX3
M43 P003 N006 P017 P017 BSB012N03LX3
M44 P017 N024 P018 P018 BSB012N03LX3
M38 N001 0 N010 N010 FDS4435A
M45 N001 0 N036 N036 FDS4435A
M46 N001 0 N037 N037 FDS4435A
M47 N001 0 N011 N011 FDS4435A
M48 N001 0 N100 N100 FDS4435A
M49 N001 0 N103 N103 FDS4435A
M50 N001 0 N114 N114 FDS4435A
M51 N001 0 N115 N115 FDS4435A
M5 N001 0 N015 N015 FDS4435A
M6 N001 0 N021 N021 FDS4435A
M11 N001 0 N022 N022 FDS4435A
M52 N001 0 N023 N023 FDS4435A
M53 N001 0 N049 N049 FDS4435A
M54 N001 0 N048 N048 FDS4435A
M55 N001 0 N025 N025 FDS4435A
M56 N001 0 N013 N013 FDS4435A
M57 N001 0 N014 N014 FDS4435A
M58 N001 0 N033 N033 FDS4435A
M59 N001 0 N094 N094 FDS4435A
M60 N001 0 N095 N095 FDS4435A
M61 N095 N114 0 0 BSB012N03LX3
M62 N049 N115 0 0 BSB012N03LX3
M63 N048 N103 0 0 BSB012N03LX3
M64 N025 N036 0 0 BSB012N03LX3
M65 N013 N010 0 0 BSB012N03LX3
M66 N014 N011 0 0 BSB012N03LX3
M67 N033 N037 0 0 BSB012N03LX3
M68 N094 N100 0 0 BSB012N03LX3
M69 N022 N098 0 0 BSB012N03LX3
M70 N023 N113 0 0 BSB012N03LX3
M71 N021 N032 0 0 BSB012N03LX3
M72 N015 N012 0 0 BSB012N03LX3
M73 N017 N015 0 0 BSB012N03LX3
M74 N017 N021 0 0 BSB012N03LX3
M75 N017 N022 0 0 BSB012N03LX3
M76 N017 N023 0 0 BSB012N03LX3
M77 N034 N013 0 0 BSB012N03LX3
M78 N034 N025 0 0 BSB012N03LX3
M79 N034 N048 0 0 BSB012N03LX3
M80 N034 N049 0 0 BSB012N03LX3
M81 N076 N014 0 0 BSB012N03LX3
M82 N076 N033 0 0 BSB012N03LX3
M83 N076 N094 0 0 BSB012N03LX3
M84 N076 N095 0 0 BSB012N03LX3
M85 N001 0 N076 N076 FDS4435A
M86 N001 0 N034 N034 FDS4435A
M87 N001 0 N017 N017 FDS4435A
M88 N001 0 N008 N008 FDS4435A
M89 N001 0 N007 N007 FDS4435A
M90 N001 0 N004 N004 FDS4435A
M91 N001 0 N016 N016 FDS4435A
M92 N001 0 N047 N047 FDS4435A
M93 N001 0 N003 N003 FDS4435A
M94 N001 0 N002 N002 FDS4435A
M95 N001 0 N020 N020 FDS4435A
M96 N001 0 N019 N019 FDS4435A
M97 N001 0 N006 N006 FDS4435A
M98 N001 0 N005 N005 FDS4435A
M99 N001 0 N024 N024 FDS4435A
M100 N008 N009 0 0 BSB012N03LX3
M101 N007 N028 0 0 BSB012N03LX3
M102 N019 N007 0 0 BSB012N03LX3
M103 N004 N093 0 0 BSB012N03LX3
M104 N016 N104 0 0 BSB012N03LX3
M106 N005 N047 0 0 BSB012N03LX3
M107 N047 N097 0 0 BSB012N03LX3
M108 N003 N089 0 0 BSB012N03LX3
M109 N002 N079 0 0 BSB012N03LX3
M110 N020 0 0 0 BSB012N03LX3
M105 N024 N003 0 0 BSB012N03LX3
M111 N006 N016 0 0 BSB012N03LX3
M19 P018 N020 0 0 BSB012N03LX3
M21 N102 N024 P001 P001 BSB012N03LX3
V1 N001 0 5
XU1 N074 N075 N060 N071 N079 LT1007
XU2 N088 N085 N060 N071 N089 LT1007
XU3 N099 N096 N060 N071 N097 LT1007
XU4 N064 N066 N060 N071 N069 LT1007
V2 N060 0 12 Rser=10
V4 N064 0 7.5
R1 N064 N074 100
R2 N074 N088 100
R3 N088 N099 100
R4 N099 N105 100
R5 N096 N043 1k
R6 N066 N043 1k
R7 N075 N043 1k
R8 N085 N043 1k
XU5 N105 N101 N060 N071 N104 LT1007
XU6 N107 N106 N060 N071 N093 LT1007
XU7 N110 N109 N060 N071 N028 LT1007
XU8 N112 N111 N060 N071 N009 LT1007
R9 N101 N043 1k
R10 N106 N043 1k
R11 N109 N043 1k
R12 N111 N043 1k
R13 N105 N107 100
R14 N107 N110 100
R15 N110 N112 100
R16 N112 0 100
V5 0 N071 12 Rser=10
Q1 N029 3 N056 0 NP
Q2 N029 2 N057 0 NP
Q3 N067 N061 N057 0 PN
Q4 N070 N061 N056 0 PN
Q5 N070 N082 N090 0 NP
Q6 N067 N082 N091 0 NP
Q7 7 N070 N082 0 NP
Q8 N029 N029 7 0 PN
R17 N090 4 1K
R18 N082 4 50K
R19 N091 4 1K
Q9 N061 N029 7 0 PN
Q10 N030 N030 7 0 PN
Q11 N035 N030 7 0 PN
Q12 N078 N078 4 0 NP
Q13 N061 N078 N092 0 NP
R20 N092 4 5K
Q14 N035 N040 N054 0 NP
Q15 N054 N080 N087 0 NP
Q16 N054 N067 N080 0 NP
R21 N080 4 50K
R22 N087 4 50
Q17 N067 N087 4 0 NP
C1 N035 N067 30p
R23 N054 N040 7.5K
R24 N035 N040 4.5K
Q18 7 N035 N044 0 NP
Q19 4 N054 N068 0 PN
R25 N044 6 25
R26 6 N068 50
Q20 N035 N044 6 0 NP
V6 4 0 -15 Rser=10
V7 7 0 15 Rser=100
R27 6 2 10K
R28 2 6 1K
R29 N030 N078 39K
R30 3 6 1k
R31 3 0 10k
Q21 N026 3 N052 0 NP
Q22 N026 2 N053 0 NP
Q23 N062 N055 N053 0 PN
Q24 N065 N055 N052 0 PN
Q25 N065 N077 N083 0 NP
Q26 N062 N077 N084 0 NP
Q27 7 N065 N077 0 NP
Q28 N026 N026 7 0 PN
R32 N083 4 1K
R33 N077 4 50K
R34 N084 4 1K
Q29 N055 N026 7 0 PN
Q30 N027 N027 7 0 PN
Q31 N031 N027 7 0 PN
Q32 N072 N072 4 0 NP
Q33 N055 N072 N086 0 NP
R35 N086 4 5K
Q34 N031 N038 N051 0 NP
Q35 N051 N073 N081 0 NP
Q36 N051 N062 N073 0 NP
R36 N073 4 50K
R37 N081 4 50
Q37 N062 N081 4 0 NP
C2 N031 N062 30p
R38 N051 N038 7.5K
R39 N031 N038 4.5K
Q38 7 N031 N039 0 NP
Q39 4 N051 N063 0 PN
R40 N039 6 25
R41 6 N063 50
Q40 N031 N039 6 0 NP
V8 4 0 -15 Rser=100
V9 7 0 15 Rser=100
R42 6 2 10K
V10 N045 0 SINE(0 8 500)
R43 N027 N072 39K
R44 3 N045 1k
Q41 N117 3 N124 0 NP
Q42 N117 2 N125 0 NP
Q43 N127 N126 N125 0 PN
Q44 N129 N126 N124 0 PN
Q45 N129 N132 N134 0 NP
Q46 N127 N132 N135 0 NP
Q47 7 N129 N132 0 NP
Q48 N117 N117 7 0 PN
R45 N134 4 1K
R46 N132 4 50K
R47 N135 4 1K
Q49 N126 N117 7 0 PN
Q50 N118 N118 7 0 PN
Q51 N119 N118 7 0 PN
Q52 N130 N130 4 0 NP
Q53 N126 N130 N136 0 NP
R48 N136 4 5K
Q54 N119 N120 N123 0 NP
Q55 N123 N131 N133 0 NP
Q56 N123 N127 N131 0 NP
R49 N131 4 50K
R50 N133 4 50
Q57 N127 N133 4 0 NP
C3 N119 N127 30p
R51 N123 N120 7.5K
R52 N119 N120 4.5K
Q58 7 N119 N121 0 NP
Q59 4 N123 N128 0 PN
R53 N121 6 25
R54 6 N128 50
Q60 N119 N121 6 0 NP
V11 4 0 -15 Rser=100
V12 7 0 15 Rser=100
R55 6 2 10K
R56 N118 N130 39K
R57 3 N122 1k
R58 2 2 2k
XU9 0 N046 N050 N059 N041 LT1007
R59 N041 N046 10k
R60 N046 6 1k
V13 N050 0 12 Rser=10
V14 N059 0 -12 Rser=10
C4 N041 N046 318n V=20
XU10 0 N138 N060 N071 N139 LT1007
R61 N137 N104 20k
R62 N137 N093 20k
R63 N137 N028 20k
R64 N137 N009 20k
R65 N137 N138 20k
R66 N138 N139 40k
C5 0 N122 318&#2013266101; V=50 Rser=0.1m
R67 N122 N139 1k
R68 N097 N137 20k
R69 N089 N137 20k
R70 N079 N137 20k
R71 N069 N137 20k
XU11 0 N042 N050 N059 N043 LT1007
R73 N042 N041 10k
R74 N043 N042 10k
.model NPN NPN
.model PNP PNP
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
* IN+
* IN-
* OUT
* This example schematic is supplied for informational/educational purposes only.
* V-
* V+
.model NP NPN(BF=125 Cje=.5p Cjc=.5p Rb=500)
.model PN LPNP(BF=25 Cje=.3p Cjc=1.5p Rb=250)
* IN+
* IN-
* OUT
* This example schematic is supplied for informational/educational purposes only.
* V-
* V+
.model NP NPN(BF=125 Cje=.5p Cjc=.5p Rb=500)
.model PN LPNP(BF=25 Cje=.3p Cjc=1.5p Rb=250)
* IN+
* IN-
* OUT
* This example schematic is supplied for informational/educational purposes only.
* V-
* V+
.model NP NPN(BF=125 Cje=.5p Cjc=.5p Rb=500)
.model PN LPNP(BF=25 Cje=.3p Cjc=1.5p Rb=250)
* Difference Instrument Amplifier
* Integrator
.tran 10m uic
.lib LTC.lib
.backanno
.end