On 7/6/2015 10:30 AM, Bill Sloman wrote:> On Sunday, July 5, 2015 at 7:26:02 PM UTC+2, Phil Hobbs wrote: >> On 07/05/2015 01:14 PM, Jim Thompson wrote: >>> On Sun, 05 Jul 2015 12:55:52 -0400, Phil Hobbs >>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>> >>> [snip] >>>>> >>>>> LTSpice is an example of why engineers should NOT design CAD. >>>>> I've never seen such absolute crap anywhere. The program >>>>> should have flagged the schematic entry error. >>>> >>>> Dunno. Seems as though it wouldn't be that easy in general to >>>> distinguish a missing flag from a decoupling network such as a >>>> cap multiplier, or an externally boosted amp (common-emitter >>>> BJT wraparounds, with their bases driven by resistors in the op >>>> amp supply lead). It would be crazy-making to have to design >>>> around the quirks of a buggy warning system. >>>> >>>> What algorithm would you suggest? >>>> >>>> Something like an assertion in C might be possible, but it's >>>> just as easy to treat a misbehaving sim like a misbehaving >>>> proto--the first thing you check is the power supplies, the >>>> second thing is the enable lines, the third thing is the CM >>>> limits, which can lead to startup problems, etc., etc. >> >>> Spice simulators can't detect faults in circuit schematics. All >>> they can do is detect floating nodes. Apparently LTspice doesn't >>> concern itself with "VP" of a symbol, since there's probably some >>> path to ground within the model. Generally PSpice would call >>> that a float, and balk. >> >> LTspice does detect floating nodes, but it doesn't know that a net >> that goes to the VCC pins of two op amps is actually floating. >> Danglers are easy to spot. > > That was my problem - the circuit contains two AD734s and the +15V > pins on both were connected - to each other - but not to anywhere > else. >Been there. Where do you think the examples came from? ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Defect in Analog Devices Spice model for the AD734
Started by ●July 4, 2015
Reply by ●July 6, 20152015-07-06
Reply by ●July 6, 20152015-07-06
Bill Sloman <bill.sloman@gmail.com> wrote:> That was my problem - the circuit contains two AD734s and the +15V > pins on both were connected - to each other - but not to anywhere > else.Part of the problem is op amps are surrounded by a bunch of components, so snaking a wire to the power pins can get tricky. I usually label the supply voltages and simply tag the power pins with the appropriate label. For example, +5 takes up very little room, and you can clearly tell when it is not connected. There is a little square pin underneath the label that disappears when it is properly connected. An ordinary wire does not have the square pin so you can't see if it is connected as easily. Another method to help eliminate errors is to label *EVERY NODE* in the circuit. This is crucial. For example, if you add two resistors in series, the node that connects them may be N002. You can use that label to plot a waveform or make a measurement. However, if you add two more components in series somewhere else, the node that connects them becomes N002, and the previous node becomes N003. Your waveforms now refer to a different part of the circuit, and it may be very difficult to see what went wrong. But if you label every node, this can't happen. Instead of trying to invent new node names, I simply use two adjoining components for the names. For example, R1C1, D2C4, L1C3, etc. For active devices, I use Q1B, Q1C, Q1E for the base, emitter and collector. The device names take precedence over component names. This makes it much easier to find the desired node in the schematic. Further examples are M1G, M1D, M1S for gate, drain and source. Op amps get U1P for the positive input, U1N for the negative input, and U1O for the output. Logic elements get U1X, U1Y for the inputs, U1A for the outputs. When you copy part of a circuit to use somewhere else, the node names remain the same but the component values change. Then it is very easy to tell which names need to be updated since they won't correspond to the new component names. This solves the problem of using signal names for the nodes. It may be difficult to tell which signal names need to be changed, and if you leave the wrong ones connected, your circuit will do strange things. These simple tricks can save a lot of time wasted trying to track down analysis problems.
Reply by ●July 6, 20152015-07-06
On 7/6/2015 3:54 PM, Tom Swift wrote:> Bill Sloman <bill.sloman@gmail.com> wrote: > >> That was my problem - the circuit contains two AD734s and the +15V >> pins on both were connected - to each other - but not to anywhere >> else. > > Part of the problem is op amps are surrounded by a bunch of components, > so snaking a wire to the power pins can get tricky. I usually label the > supply voltages and simply tag the power pins with the appropriate label.You have to be careful in naming stuff, though--if you call it VDD and not +3.3V, for instance, it'll probably survive changes better. ;)> > For example, +5 takes up very little room, and you can clearly tell when > it is not connected. There is a little square pin underneath the label > that disappears when it is properly connected. An ordinary wire does not > have the square pin so you can't see if it is connected as easily. > > Another method to help eliminate errors is to label *EVERY NODE* in the > circuit. This is crucial.Yikes. Must be a pretty simple circuit!> > For example, if you add two resistors in series, the node that connects > them may be N002. You can use that label to plot a waveform or make a > measurement. > > However, if you add two more components in series somewhere else, the > node that connects them becomes N002, and the previous node becomes N003. > > Your waveforms now refer to a different part of the circuit, and it may > be very difficult to see what went wrong. > > But if you label every node, this can't happen.Seems like a bit of an OCD solution, though. Just clicking the node you want a couple of times fixes it.> > Instead of trying to invent new node names, I simply use two adjoining > components for the names. For example, R1C1, D2C4, L1C3, etc. > > For active devices, I use Q1B, Q1C, Q1E for the base, emitter and > collector. The device names take precedence over component names. This > makes it much easier to find the desired node in the schematic. > > Further examples are M1G, M1D, M1S for gate, drain and source. > > Op amps get U1P for the positive input, U1N for the negative input, and > U1O for the output. > > Logic elements get U1X, U1Y for the inputs, U1A for the outputs. > > When you copy part of a circuit to use somewhere else, the node names > remain the same but the component values change. Then it is very easy to > tell which names need to be updated since they won't correspond to the > new component names. > > This solves the problem of using signal names for the nodes. It may be > difficult to tell which signal names need to be changed, and if you leave > the wrong ones connected, your circuit will do strange things. > > These simple tricks can save a lot of time wasted trying to track down > analysis problems.If you spend a great deal of time sweating over LTspice, I can see where that might be worthwhile, but it looks like a lot of extra work to me. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●July 6, 20152015-07-06
Phil Hobbs <hobbs@electrooptical.net> wrote:> On 7/6/2015 3:54 PM, Tom Swift wrote:>> Part of the problem is op amps are surrounded by a bunch of >> components, so snaking a wire to the power pins can get tricky. I >> usually label the supply voltages and simply tag the power pins with >> the appropriate label.> You have to be careful in naming stuff, though--if you call it VDD and > not +3.3V, for instance, it'll probably survive changes better. ;)User choice. I like to be explicit, especially when there are several supply voltages.>> Another method to help eliminate errors is to label *EVERY NODE* in >> the circuit. This is crucial.> Yikes. Must be a pretty simple circuit!It doesn't take very long, and you can check the waveforms at every node much easier. It is even more helpful in complicated circuits where you can easily get lost trying to troubleshoot.>> Your waveforms now refer to a different part of the circuit, and it >> may be very difficult to see what went wrong.>> But if you label every node, this can't happen.> Seems like a bit of an OCD solution, though. Just clicking the node > you want a couple of times fixes it.It's not clear what you mean. Once you have defined a waveform using a node number, or used the .measure command, you are hosed when you change the circuit. Then good luck trying to find the original node where you wanted to take the measurement.>> These simple tricks can save a lot of time wasted trying to track >> down analysis problems.> If you spend a great deal of time sweating over LTspice, I can see > where that might be worthwhile, but it looks like a lot of extra work > to me.It doesn't matter how much time you spend on LTspice. A simple mistake can cost you a lot more time. You see this fairly often in this newsgroup, and especially in the Yahoo LTspice forum. It's not really that much work. Press F4, enter three or four characters, plop it on the node. Done. Why not eliminate these problems at the beginning. It really helps eliminate time wasted on problems that should not have happened in the first place.> Cheers> Phil Hobbs
Reply by ●July 6, 20152015-07-06
On Mon, 06 Jul 2015 16:10:31 -0400, Phil Hobbs <hobbs@electrooptical.net> wrote:>On 7/6/2015 3:54 PM, Tom Swift wrote: >> Bill Sloman <bill.sloman@gmail.com> wrote: >> >>> That was my problem - the circuit contains two AD734s and the +15V >>> pins on both were connected - to each other - but not to anywhere >>> else. >> >> Part of the problem is op amps are surrounded by a bunch of components, >> so snaking a wire to the power pins can get tricky. I usually label the >> supply voltages and simply tag the power pins with the appropriate label. > >You have to be careful in naming stuff, though--if you call it VDD and >not +3.3V, for instance, it'll probably survive changes better. ;) > >> >> For example, +5 takes up very little room, and you can clearly tell when >> it is not connected. There is a little square pin underneath the label >> that disappears when it is properly connected. An ordinary wire does not >> have the square pin so you can't see if it is connected as easily. >> >> Another method to help eliminate errors is to label *EVERY NODE* in the >> circuit. This is crucial. > >Yikes. Must be a pretty simple circuit! > >> >> For example, if you add two resistors in series, the node that connects >> them may be N002. You can use that label to plot a waveform or make a >> measurement. >> >> However, if you add two more components in series somewhere else, the >> node that connects them becomes N002, and the previous node becomes N003. >> >> Your waveforms now refer to a different part of the circuit, and it may >> be very difficult to see what went wrong. >> >> But if you label every node, this can't happen. > >Seems like a bit of an OCD solution, though. Just clicking the node you >want a couple of times fixes it. >> >> Instead of trying to invent new node names, I simply use two adjoining >> components for the names. For example, R1C1, D2C4, L1C3, etc. >> >> For active devices, I use Q1B, Q1C, Q1E for the base, emitter and >> collector. The device names take precedence over component names. This >> makes it much easier to find the desired node in the schematic. >> >> Further examples are M1G, M1D, M1S for gate, drain and source. >> >> Op amps get U1P for the positive input, U1N for the negative input, and >> U1O for the output. >> >> Logic elements get U1X, U1Y for the inputs, U1A for the outputs. >> >> When you copy part of a circuit to use somewhere else, the node names >> remain the same but the component values change. Then it is very easy to >> tell which names need to be updated since they won't correspond to the >> new component names. >> >> This solves the problem of using signal names for the nodes. It may be >> difficult to tell which signal names need to be changed, and if you leave >> the wrong ones connected, your circuit will do strange things. >> >> These simple tricks can save a lot of time wasted trying to track down >> analysis problems. > >If you spend a great deal of time sweating over LTspice, I can see where >that might be worthwhile, but it looks like a lot of extra work to me. > >Cheers > >Phil HobbsI started out with Spice that didn't have schematic entry, thus I drew schematics by pencil, numbered the nodes, then made a netlist with a text editor (first using a VAX780, then under DOS). It was such a royal pain to keep track of version changes that I had my son Aaron (when he was a teenager... he's now 45 :-) write me a version handler that saved as *.cir.01, *.cir.02 etc. Also saved the *.dat files that way, thus it was easy to back up under a munged change. I do agree with Tom Swift on one point... naming nodes you want to repeatedly observe forces the simulator to retain that name from run-to-run thus avoiding the simulator renumbering nodes every time there's a recompile. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●July 6, 20152015-07-06
On Mon, 06 Jul 2015 16:10:31 -0400, Phil Hobbs <hobbs@electrooptical.net> wrote:>On 7/6/2015 3:54 PM, Tom Swift wrote: >> Bill Sloman <bill.sloman@gmail.com> wrote: >> >>> That was my problem - the circuit contains two AD734s and the +15V >>> pins on both were connected - to each other - but not to anywhere >>> else. >> >> Part of the problem is op amps are surrounded by a bunch of components, >> so snaking a wire to the power pins can get tricky. I usually label the >> supply voltages and simply tag the power pins with the appropriate label. > >You have to be careful in naming stuff, though--if you call it VDD and >not +3.3V, for instance, it'll probably survive changes better. ;)If you have multiple supplies, calling them all "Vdd" causes problems. ;-)>> >> For example, +5 takes up very little room, and you can clearly tell when >> it is not connected. There is a little square pin underneath the label >> that disappears when it is properly connected. An ordinary wire does not >> have the square pin so you can't see if it is connected as easily. >> >> Another method to help eliminate errors is to label *EVERY NODE* in the >> circuit. This is crucial. > >Yikes. Must be a pretty simple circuit!I try to name all nets in a schematic. It makes probing the layout much easier.
Reply by ●July 6, 20152015-07-06
>> pretty simple circuit!>I try to name all nets in a schematic. �It makes probing the layout >much easier.Hmm. Normally I don't spend that much time on a given simulation--there are usually only a couple of things I need to find out that SPICE can tell me. I might spend more effort on an all-discrete design, but IME most IC models give only an impressionistic view of actual chip behaviour, so it's hardly worth the effort. Cheers Phil Hobbs
Reply by ●July 6, 20152015-07-06
On Mon, 6 Jul 2015 19:14:30 -0700 (PDT), Phil Hobbs <pcdhobbs@gmail.com> wrote:>>> pretty simple circuit! > >>I try to name all nets in a schematic. �It makes probing the layout >>much easier. > >Hmm. Normally I don't spend that much time on a given simulation--there are usually only a couple of things I need to find out that SPICE can tell me. > >I might spend more effort on an all-discrete design, but IME most IC models give only an impressionistic view of actual chip behaviour, so it's hardly worth the effort. >I probably use SPICE for even less than you because I don't give the models that much credit. Even the discrete models suck. It's too easy to trust the simulation. OTOH, when I did chip design I relied on SPICE (well, ASTAP at the time). IBMs models were superb. I was referring to the board schematic, though. Naming all the nets makes reviewing the layout much easier. Though not all net names get printed on the schematic, it's easier to deal with them than a thousand similar strings.
Reply by ●July 7, 20152015-07-07
Phil Hobbs <pcdhobbs@gmail.com> wrote:>>I try to name all nets in a schematic. �It makes probing the layout >>much easier.> Hmm. Normally I don't spend that much time on a given > simulation--there are usually only a couple of things I need to find > out that SPICE can tell me. > > I might spend more effort on an all-discrete design, but IME most IC > models give only an impressionistic view of actual chip behaviour, so > it's hardly worth the effort.> Cheers> Phil HobbsHere are some examples where simulation can be very valuable. 1. Use universalopamp2 and set the voltage gain, GBW and slew rate to see the effect on open and closed loop response, gain and phase margin. This can help you decide on how much performance is needed in the op amp and how much money to spend on one. I'm sure you could do this in your head, but most people need help and LTspice does a good job. It gets more complicated when there are multiple op amps involved. 2. Check pll loop damping and step response with variations in op amp gan and bandwidth, as above. 3. Develop new circuit configurations and check the response before going to breadboard. Pencil and paper is a good place to start, but LTspice gives a much better picture of what is going on and where the weak points are. You used this technique yourself when you developed a calibrator for one of your wideband circuits. You found that a tiny amount of series inductance was enough to destroy the performance you were seeking, and ended up putting a bunch of parts in parallel to reduce the inductance. 4. Document circuit response for troubleshooting in manufacturing. Techs can easily see how the circuit is supposed to work and check waveforms at different points. Then compare with the results on a defective pcb to see what needs to be replaced to solve the problem. Finally, check the repaired circuit to verify it performs as expected. I think it would be professional to include node names at every node to help the techs find their way around the circuit. There are many more examples, but I think you will find most engineers feel that LTspice simulation is a valuable tool. Until you get screwed over by sloppy or nonexistent node names.
Reply by ●July 7, 20152015-07-07
Tom Swift <spam@me.com> wrote:> Here are some examples where simulation can be very valuable.> 1. Use universalopamp2 and set the voltage gain, GBW and slew rate to > see the effect on open and closed loop response, gain and phase > margin.This is a bit garbled. It should read 1. Use universalopamp2 and set the voltage gain, GBW and slew rate to see the effect on open loop gain and phase margin and the effect on closed loop response.
