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Defect in Analog Devices Spice model for the AD734

Started by Bill Sloman July 4, 2015
I've been using the Analog Devices Spice model in LTSpice to model the AD734 running with a current output -  see Figure 25 on page 13 of the Rev E AD734 data sheet

http://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf

When running a roughly 15kHz sine wave through the device, the positive current output limits at something between +200uA and +280uA.

The voltage at the W and Z1 outputs of the AD734 is well below the rail.

I've tried 2.2k, 6.8k and 15k current setting resistors. Only with 15k did the voltage at the W and Z1 outputs get high enough to be interesting.

The current clipped at +200uA with 2.2k, +282.77uA at 6.8k and +267.94uA at 15k.

The negative-going excursions looked perfectly sinusoidal, and went down to -350uA.

Working in another region of operation, with more head-room, the currents clamped a lot higher, at about +800uA, when the negative currents were getting down to -2.4mA.

It looks very much as if there's some kind of silly mistake in the AD734 Spice model (which would interest Jim Thompson, who wants to sell Analog Devices better Spice models).

If the actual device acted like the model, the data sheet wouldn't talk about +/-10mA output current limits (as it does on page 13).

It's easy enough to hand-edit .cir files, if you kno0w what you are doing. Any advice will be gratefully received. I probably should have raised this with Analog Devices directly, but the price they charge for the AD734 means that they can't be selling many of them, which doesn't suggest that I'd get a prompt response.

-- 
Bill Sloman, Sydney (but in Paris at this instant)
On Saturday, July 4, 2015 at 12:23:27 PM UTC+2, Bill Sloman wrote:
> I've been using the Analog Devices Spice model in LTSpice to model the AD734 running with a current output - see Figure 25 on page 13 of the Rev E AD734 data sheet > > http://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf > > When running a roughly 15kHz sine wave through the device, the positive current output limits at something between +200uA and +280uA. > > The voltage at the W and Z1 outputs of the AD734 is well below the rail. > > I've tried 2.2k, 6.8k and 15k current setting resistors. Only with 15k did the voltage at the W and Z1 outputs get high enough to be interesting. > > The current clipped at +200uA with 2.2k, +282.77uA at 6.8k and +267.94uA at 15k. > > The negative-going excursions looked perfectly sinusoidal, and went down to -350uA. > > Working in another region of operation, with more head-room, the currents clamped a lot higher, at about +800uA, when the negative currents were getting down to -2.4mA. > > It looks very much as if there's some kind of silly mistake in the AD734 Spice model (which would interest Jim Thompson, who wants to sell Analog Devices better Spice models). > > If the actual device acted like the model, the data sheet wouldn't talk about +/-10mA output current limits (as it does on page 13). > > It's easy enough to hand-edit .cir files, if you kno0w what you are doing. Any advice will be gratefully received. I probably should have raised this with Analog Devices directly, but the price they charge for the AD734 means that they can't be selling many of them, which doesn't suggest that I'd get a prompt response.
Oops. It looks as if the defect wasn't in the Analog Devices model, but in my circuit diagram - a connection to +15V seems to have been edited out at some point and the circuit was getting it's positive power supply from its inputs, making the model inconveniently realistic - I've had that happen on real circuits, and it can take a while to work out what's going wrong. My apologies to one and all. -- Bill Sloman, Sydney
On Sunday, July 5, 2015 at 7:58:07 AM UTC-4, Bill Sloman wrote:
> On Saturday, July 4, 2015 at 12:23:27 PM UTC+2, Bill Sloman wrote: > > I've been using the Analog Devices Spice model in LTSpice to model the AD734 running with a current output - see Figure 25 on page 13 of the Rev E AD734 data sheet > > > > http://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf > > > > When running a roughly 15kHz sine wave through the device, the positive current output limits at something between +200uA and +280uA. > > > > The voltage at the W and Z1 outputs of the AD734 is well below the rail. > > > > I've tried 2.2k, 6.8k and 15k current setting resistors. Only with 15k did the voltage at the W and Z1 outputs get high enough to be interesting. > > > > The current clipped at +200uA with 2.2k, +282.77uA at 6.8k and +267.94uA at 15k. > > > > The negative-going excursions looked perfectly sinusoidal, and went down to -350uA. > > > > Working in another region of operation, with more head-room, the currents clamped a lot higher, at about +800uA, when the negative currents were getting down to -2.4mA. > > > > It looks very much as if there's some kind of silly mistake in the AD734 Spice model (which would interest Jim Thompson, who wants to sell Analog Devices better Spice models). > > > > If the actual device acted like the model, the data sheet wouldn't talk about +/-10mA output current limits (as it does on page 13). > > > > It's easy enough to hand-edit .cir files, if you kno0w what you are doing. Any advice will be gratefully received. I probably should have raised this with Analog Devices directly, but the price they charge for the AD734 means that they can't be selling many of them, which doesn't suggest that I'd get a prompt response. > > Oops. It looks as if the defect wasn't in the Analog Devices model, but in my circuit diagram - a connection to +15V seems to have been edited out at some point and the circuit was getting it's positive power supply from its inputs, making the model inconveniently realistic - I've had that happen on real circuits, and it can take a while to work out what's going wrong. > > My apologies to one and all. > > -- > Bill Sloman, Sydney
LTSpice is an example of why engineers should NOT design CAD. I've never seen such absolute crap anywhere. The program should have flagged the schematic entry error.
On 07/05/2015 10:50 AM, bloggs.fredbloggs.fred@gmail.com wrote:
> On Sunday, July 5, 2015 at 7:58:07 AM UTC-4, Bill Sloman wrote: >> On Saturday, July 4, 2015 at 12:23:27 PM UTC+2, Bill Sloman wrote: >>> I've been using the Analog Devices Spice model in LTSpice to >>> model the AD734 running with a current output - see Figure 25 on >>> page 13 of the Rev E AD734 data sheet >>> >>> http://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf >>> >>> >>>
When running a roughly 15kHz sine wave through the device, the positive current output limits at something between +200uA and +280uA.
>>> >>> The voltage at the W and Z1 outputs of the AD734 is well below >>> the rail.. >>> >>> I've tried 2.2k, 6.8k and 15k current setting resistors. Only >>> with 15k did the voltage at the W and Z1 outputs get high enough >>> to be interesting. >>> >>> The current clipped at +200uA with 2.2k, +282.77uA at 6.8k and >>> +267.94uA at 15k. >>> >>> The negative-going excursions looked perfectly sinusoidal, and >>> went down to -350uA. >>> >>> Working in another region of operation, with more head-room, the >>> currents clamped a lot higher, at about +800uA, when the negative >>> currents were getting down to -2.4mA. >>> >>> It looks very much as if there's some kind of silly mistake in >>> the AD734 Spice model (which would interest Jim Thompson, who >>> wants to sell Analog Devices better Spice models). >>> >>> If the actual device acted like the model, the data sheet >>> wouldn't talk about +/-10mA output current limits (as it does on >>> page 13). >>> >>> It's easy enough to hand-edit .cir files, if you kno0w what you >>> are doing. Any advice will be gratefully received. I probably >>> should have raised this with Analog Devices directly, but the >>> price they charge for the AD734 means that they can't be selling >>> many of them, which doesn't suggest that I'd get a prompt >>> response. >> >> Oops. It looks as if the defect wasn't in the Analog Devices model, >> but in my circuit diagram - a connection to +15V seems to have been >> edited out at some point and the circuit was getting it's positive >> power supply from its inputs, making the model inconveniently >> realistic - I've had that happen on real circuits, and it can take >> a while to work out what's going wrong. >> >> My apologies to one and all. >> >> -- Bill Sloman, Sydney > > LTSpice is an example of why engineers should NOT design CAD. I've > never seen such absolute crap anywhere. The program should have > flagged the schematic entry error. >
Dunno. Seems as though it wouldn't be that easy in general to distinguish a missing flag from a decoupling network such as a cap multiplier, or an externally boosted amp (common-emitter BJT wraparounds, with their bases driven by resistors in the op amp supply lead). It would be crazy-making to have to design around the quirks of a buggy warning system. What algorithm would you suggest? Something like an assertion in C might be possible, but it's just as easy to treat a misbehaving sim like a misbehaving proto--the first thing you check is the power supplies, the second thing is the enable lines, the third thing is the CM limits, which can lead to startup problems, etc., etc. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Sun, 05 Jul 2015 12:55:52 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

[snip]
>> >> LTSpice is an example of why engineers should NOT design CAD. I've >> never seen such absolute crap anywhere. The program should have >> flagged the schematic entry error. >> > >Dunno. Seems as though it wouldn't be that easy in general to >distinguish a missing flag from a decoupling network such as a cap >multiplier, or an externally boosted amp (common-emitter BJT >wraparounds, with their bases driven by resistors in the op amp supply >lead). It would be crazy-making to have to design around the quirks of >a buggy warning system. > >What algorithm would you suggest? > >Something like an assertion in C might be possible, but it's just as >easy to treat a misbehaving sim like a misbehaving proto--the first >thing you check is the power supplies, the second thing is the enable >lines, the third thing is the CM limits, which can lead to startup >problems, etc., etc. > >Cheers > >Phil Hobbs
Spice simulators can't detect faults in circuit schematics. All they can do is detect floating nodes. Apparently LTspice doesn't concern itself with "VP" of a symbol, since there's probably some path to ground within the model. Generally PSpice would call that a float, and balk. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On 07/05/2015 01:14 PM, Jim Thompson wrote:
> On Sun, 05 Jul 2015 12:55:52 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > > [snip] >>> >>> LTSpice is an example of why engineers should NOT design CAD. I've >>> never seen such absolute crap anywhere. The program should have >>> flagged the schematic entry error. >>> >> >> Dunno. Seems as though it wouldn't be that easy in general to >> distinguish a missing flag from a decoupling network such as a cap >> multiplier, or an externally boosted amp (common-emitter BJT >> wraparounds, with their bases driven by resistors in the op amp supply >> lead). It would be crazy-making to have to design around the quirks of >> a buggy warning system. >> >> What algorithm would you suggest? >> >> Something like an assertion in C might be possible, but it's just as >> easy to treat a misbehaving sim like a misbehaving proto--the first >> thing you check is the power supplies, the second thing is the enable >> lines, the third thing is the CM limits, which can lead to startup >> problems, etc., etc. >> >> Cheers >> >> Phil Hobbs > > Spice simulators can't detect faults in circuit schematics. All they > can do is detect floating nodes. Apparently LTspice doesn't concern > itself with "VP" of a symbol, since there's probably some path to > ground within the model. Generally PSpice would call that a float, > and balk. > > ...Jim Thompson >
LTspice does detect floating nodes, but it doesn't know that a net that goes to the VCC pins of two op amps is actually floating. Danglers are easy to spot. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Sun, 05 Jul 2015 13:25:57 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 07/05/2015 01:14 PM, Jim Thompson wrote: >> On Sun, 05 Jul 2015 12:55:52 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >> [snip] >>>> >>>> LTSpice is an example of why engineers should NOT design CAD. I've >>>> never seen such absolute crap anywhere. The program should have >>>> flagged the schematic entry error. >>>> >>> >>> Dunno. Seems as though it wouldn't be that easy in general to >>> distinguish a missing flag from a decoupling network such as a cap >>> multiplier, or an externally boosted amp (common-emitter BJT >>> wraparounds, with their bases driven by resistors in the op amp supply >>> lead). It would be crazy-making to have to design around the quirks of >>> a buggy warning system. >>> >>> What algorithm would you suggest? >>> >>> Something like an assertion in C might be possible, but it's just as >>> easy to treat a misbehaving sim like a misbehaving proto--the first >>> thing you check is the power supplies, the second thing is the enable >>> lines, the third thing is the CM limits, which can lead to startup >>> problems, etc., etc. >>> >>> Cheers >>> >>> Phil Hobbs >> >> Spice simulators can't detect faults in circuit schematics. All they >> can do is detect floating nodes. Apparently LTspice doesn't concern >> itself with "VP" of a symbol, since there's probably some path to >> ground within the model. Generally PSpice would call that a float, >> and balk. >> >> ...Jim Thompson >> > >LTspice does detect floating nodes, but it doesn't know that a net that >goes to the VCC pins of two op amps is actually floating. Danglers are >easy to spot. > >Cheers > >Phil Hobbs
You missed my point... LTspice calls a path thru a symbol as non-floating... for symbols PSpice would call that floating. However, if the part were a "block", PSpice would recognize the path. It's a moot point, bizarre results call for careful examination of your schematic... GIGO ;-) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On 07/05/2015 01:39 PM, Jim Thompson wrote:
> On Sun, 05 Jul 2015 13:25:57 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 07/05/2015 01:14 PM, Jim Thompson wrote: >>> On Sun, 05 Jul 2015 12:55:52 -0400, Phil Hobbs >>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>> >>> [snip] >>>>> >>>>> LTSpice is an example of why engineers should NOT design CAD. I've >>>>> never seen such absolute crap anywhere. The program should have >>>>> flagged the schematic entry error. >>>>> >>>> >>>> Dunno. Seems as though it wouldn't be that easy in general to >>>> distinguish a missing flag from a decoupling network such as a cap >>>> multiplier, or an externally boosted amp (common-emitter BJT >>>> wraparounds, with their bases driven by resistors in the op amp supply >>>> lead). It would be crazy-making to have to design around the quirks of >>>> a buggy warning system. >>>> >>>> What algorithm would you suggest? >>>> >>>> Something like an assertion in C might be possible, but it's just as >>>> easy to treat a misbehaving sim like a misbehaving proto--the first >>>> thing you check is the power supplies, the second thing is the enable >>>> lines, the third thing is the CM limits, which can lead to startup >>>> problems, etc., etc. >>>> >>>> Cheers >>>> >>>> Phil Hobbs >>> >>> Spice simulators can't detect faults in circuit schematics. All they >>> can do is detect floating nodes. Apparently LTspice doesn't concern >>> itself with "VP" of a symbol, since there's probably some path to >>> ground within the model. Generally PSpice would call that a float, >>> and balk. >>> >>> ...Jim Thompson >>> >> >> LTspice does detect floating nodes, but it doesn't know that a net that >> goes to the VCC pins of two op amps is actually floating. Danglers are >> easy to spot. >> >> Cheers >> >> Phil Hobbs > > You missed my point... LTspice calls a path thru a symbol as > non-floating... for symbols PSpice would call that floating.
Even something like the tuning pin of a 555, or an offset adjust on an op amp?
> > However, if the part were a "block", PSpice would recognize the path. > > It's a moot point, bizarre results call for careful examination of > your schematic... GIGO ;-) >
Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Sunday, July 5, 2015 at 12:55:57 PM UTC-4, Phil Hobbs wrote:
> On 07/05/2015 10:50 AM, bloggs.fredbloggs.fred@gmail.com wrote: > > On Sunday, July 5, 2015 at 7:58:07 AM UTC-4, Bill Sloman wrote: > >> On Saturday, July 4, 2015 at 12:23:27 PM UTC+2, Bill Sloman wrote: > >>> I've been using the Analog Devices Spice model in LTSpice to > >>> model the AD734 running with a current output - see Figure 25 on > >>> page 13 of the Rev E AD734 data sheet > >>> > >>> http://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf > >>> > >>> > >>> > When running a roughly 15kHz sine wave through the device, the positive > current output limits at something between +200uA and +280uA. > >>> > >>> The voltage at the W and Z1 outputs of the AD734 is well below > >>> the rail.. > >>> > >>> I've tried 2.2k, 6.8k and 15k current setting resistors. Only > >>> with 15k did the voltage at the W and Z1 outputs get high enough > >>> to be interesting. > >>> > >>> The current clipped at +200uA with 2.2k, +282.77uA at 6.8k and > >>> +267.94uA at 15k. > >>> > >>> The negative-going excursions looked perfectly sinusoidal, and > >>> went down to -350uA. > >>> > >>> Working in another region of operation, with more head-room, the > >>> currents clamped a lot higher, at about +800uA, when the negative > >>> currents were getting down to -2.4mA. > >>> > >>> It looks very much as if there's some kind of silly mistake in > >>> the AD734 Spice model (which would interest Jim Thompson, who > >>> wants to sell Analog Devices better Spice models). > >>> > >>> If the actual device acted like the model, the data sheet > >>> wouldn't talk about +/-10mA output current limits (as it does on > >>> page 13). > >>> > >>> It's easy enough to hand-edit .cir files, if you kno0w what you > >>> are doing. Any advice will be gratefully received. I probably > >>> should have raised this with Analog Devices directly, but the > >>> price they charge for the AD734 means that they can't be selling > >>> many of them, which doesn't suggest that I'd get a prompt > >>> response. > >> > >> Oops. It looks as if the defect wasn't in the Analog Devices model, > >> but in my circuit diagram - a connection to +15V seems to have been > >> edited out at some point and the circuit was getting it's positive > >> power supply from its inputs, making the model inconveniently > >> realistic - I've had that happen on real circuits, and it can take > >> a while to work out what's going wrong. > >> > >> My apologies to one and all. > >> > >> -- Bill Sloman, Sydney > > > > LTSpice is an example of why engineers should NOT design CAD. I've > > never seen such absolute crap anywhere. The program should have > > flagged the schematic entry error. > > > > Dunno. Seems as though it wouldn't be that easy in general to > distinguish a missing flag from a decoupling network such as a cap > multiplier, or an externally boosted amp (common-emitter BJT > wraparounds, with their bases driven by resistors in the op amp supply > lead). It would be crazy-making to have to design around the quirks of > a buggy warning system. > > What algorithm would you suggest? > > Something like an assertion in C might be possible, but it's just as > easy to treat a misbehaving sim like a misbehaving proto--the first > thing you check is the power supplies, the second thing is the enable > lines, the third thing is the CM limits, which can lead to startup > problems, etc., etc. > > Cheers > > Phil Hobbs > > -- > Dr Philip C D Hobbs > Principal Consultant > ElectroOptical Innovations LLC > Optics, Electro-optics, Photonics, Analog Electronics > > 160 North State Road #203 > Briarcliff Manor NY 10510 > > hobbs at electrooptical dot net > http://electrooptical.net
He said "-a connection to +15V seems to have been edited out at some point-" - looks like a NO CONNECTION to me, and on a power supply pin, seems straightforward.
On Sun, 05 Jul 2015 13:46:14 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 07/05/2015 01:39 PM, Jim Thompson wrote: >> On Sun, 05 Jul 2015 13:25:57 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 07/05/2015 01:14 PM, Jim Thompson wrote:
[snip]
>> >> You missed my point... LTspice calls a path thru a symbol as >> non-floating... for symbols PSpice would call that floating. > >Even something like the tuning pin of a 555, or an offset adjust on an >op amp?
In PSpice, at least in original flavor PSpice Schematics before the OrCAD flawed abortion, when you construct a symbol you can define float conditions for each pin. In a "block" (actually a "hole" from whence to descend into another schematic) paths to ground are seen.
> > >> >> However, if the part were a "block", PSpice would recognize the path. >> >> It's a moot point, bizarre results call for careful examination of >> your schematic... GIGO ;-) >> >Cheers > >Phil Hobbs
...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.