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goofy PWM

Started by John Larkin May 29, 2015
On Saturday, 30 May 2015 14:00:53 UTC+10, Jasen Betts  wrote:
> On 2015-05-30, Bill Sloman <bill.sloman@ieee.org> wrote: > > On 30/05/2015 9:20 AM, Jasen Betts wrote: > >> On 2015-05-29, John Larkin <jlarkin@highlandtechnology.com> wrote: > >>> On 29 May 2015 05:54:35 -0700, Winfield Hill > >>> <hill@rowland.harvard.edu> wrote: > >>> > >>>> Bill Sloman wrote... > >>>>> > >>>>> John Larkin wrote: > >>>>>> > >>>>>> I need an isolated analog output (many of them, actually) > >>>>>> with, say, 1 PPM programmability and linearity. An > >>>>>> optocoupled DAC would be silly, so I'll use PWM. > >>>> > >>>>>> The average value will be disturbed by the rise and > >>>>>> fall times of the optocoupler (or whatever) so > >>>>>> getting to 1 PPM linearity is scary.) > >>>>> > >>>>> There are more sources of potential linearity error at > >>>>> the 1ppm level than just differences between rise and > >>>>> fall times. > >>>> > >>>> It's actually the overall ON vs OFF delay times, > >>>> rather than rise time alone. The on vs off delays > >>>> are often quite different for optical-couplers and > >>>> drivers, but they're generally fairly stable and > >>>> repeatable. It'd be easy to add adjustable fixed > >>>> delays to both the on and off times, so they could > >>>> be trimmed to be more or less the same. I'll bet > >>>> a given choice of components in a production run > >>>> would have pretty closely matched delays; measure > >>>> one and apply the delay components to the rest. > >>> > >>> Yeah, the bottom line problem with D-S is on/off asymmetry, which > >>> makes errors at high, and essentially random, pulse rates. But I > >>> wouldn't want to attempt to tune it out. > >>> > >>> 1 0 1 0 has 8 edges, whereas 1 1 0 0 has only 4, so they won't > >>> average the same. Delta-sigma generates too many cases. The IC boys > >>> must do tricks to make D-S ICs as good as they are. > >> > >> ??? I count 4 and and 2 not 8 and 4 > >> > >>> The clustered/boogered PWM always has the same, small number of edges, > >>> so will always be monotonic and noise-free. > >>> > >>> It's really not worth trying to de-cluster the wider pulses, ie > >>> > >>> 50001 50000 50001 50000 ON versus > >>> 50001 50001 50000 50000 > >>> > >>> since the difference in ripple is a couple PPMs, and the lowpass > >>> filter will kill that tiny residual ripple. > >>> > >>> There probably *is* some tricky math algorithm to evenly disperse the > >>> N+1 pulses, some bit-field reversal or something, sort of a Van der > >>> Corput sequence thing. My guys will get into that math fun, even if > >>> it's unnecessary. > >> > >> pure bit field reversal gives an effect a bit like a delta-sigma, most > >> of the noise goes into the high frequencies but the number of transitions > >> is variable. burkes dither used to convert photos one bit depth works > >> like that. > >> > >> If you want a fixed number of transitions > >> > >> pick how many sub-fields you want in your modified PWM and then > >> shift your counter output log_2 that many bits leftwards, reverse > >> the order of the bits that overflowed and insert them into the > >> vacated spots on the right, > >> > >> so for an n bit counter to be split into 8 > >> > >>b n n-3 > >> n-1 .... > >> n-2 ----\ 3 > >> n-3 \ 2 > >> ... / 1 > >> 3 -----/ 0 > >> 2 n-2 > >> 1 n-1 > >> 0 n > > I was diagramming the transformation to make to the clock > my second column is the order the go into the comparitor > > > > My scheme was to reverse just the top four bits of the 10-bit counter output > > > > Counter Comparator > > > > 6 \ 10 > > 7 \ 9 > > 8 \ 8 > > 9 / 7 > > 10 / 6 > > 5 5 > > 4 4 > > 3 3 > > 2 2 > > 1 1 > > > > which gave 16x more transitions, and a well defined maximum transition rate. > > that looks like it would give mismatched pulse lengths: most of the of the 32 > slices would be either full or empty.
Wrong. From 6.25% of full scale to 93.75% you end up with 16 segments whose lengths differ by no more than one interval. Sloman A.W., Buggs P., Molloy J., and Stewart D. "A microcontroller-based driver to stabilise the temperature of an optical stage to 1mK in the range 4C to 38C, using a Peltier heat pump and a thermistor sensor" Measurement Science and Technology, 7 1653-64 (1996) spells it out in detail. E-mail me at bill.sloman@ieee.org if you can't easily get hold of a copy.
> What I have done is reverse all the bits which gives maximum > deterministic dither at the cost of an umpredictable number of edges > per cycle, but then un-reverse the least-signifigant bits to limit the > number of edges. So long as he programme input stays in the middle of > of its range (does fill or empty all its high-order bits there will be > a predictable number of transitions (2^(b+1)) for b bits moved.
Sure. You've just chosen an unnecessarily clumsy way of getting to a sub-optimal solution. -- Bill Sloman, Sydney
On 2015-05-30, Bill Sloman <bill.sloman@gmail.com> wrote:
as diagramming the transformation to make to the clock
>> my second column is the order the go into the comparitor >> >> >> > My scheme was to reverse just the top four bits of the 10-bit counter output >> > >> > Counter Comparator >> > >> > 6 \ 10 >> > 7 \ 9 >> > 8 \ 8 >> > 9 / 7 >> > 10 / 6 >> > 5 5 >> > 4 4 >> > 3 3 >> > 2 2 >> > 1 1 >> > >> > which gave 16x more transitions, and a well defined maximum transition rate. >> >> that looks like it would give mismatched pulse lengths: most of the of the 32 >> slices would be either full or empty. > > Wrong. From 6.25% of full scale to 93.75% you end up with 16 segments whose lengths differ by no more than one interval.
(you said 4 but then diagrammed 5 bits reversed, I'll go with 4 as that's what you're discussing most recently) By my reading of your wiring pattern above the comparitor sees a sequence that starts 0,1,2,3,4,5...,62,63,512,513,..543,256...319, 768...831, (please excuse any trivial arithmeti errors) so if we assume the pwm level input is is at 600 we'd see high for 192 clock periods then low for 64 ... "my" pattern (for some reason we're counting from 1 instead of from 0, I'll keep doing that) b6 b5 b4 b3 b2 b1 b7 b8 b9 b10 My wiring pattern (shifting the low bits to the top and reversing the high bits at the bottom) gives 0,16,32,48,64...992,1008,8,24,40...1016,4,20...1004 ,1020,12... which is 16 steepness 16 staircases of dithered offset, and, I expect, what you intended. it can be improved by usung the msb of the shifted bits to turn that sequence into a double staircase like so. ( ^ represents XOR ) b5 ^ b6 b4 ^ b6 b3 ^ b6 b2 ^ b6 b1 ^ b6 b6 b7 b8 b9 b10 that will stop the input from phase modulating the output to the same extent.. all the bit shuffling has me wondering about how a LFSR would perform in this application, has anyone tried that? -- umop apisdn
make it balanced ?

http://www.crownaudio.com/media/pdf/amps/bcapaper.pdf

-Lasse
John Larkin wrote...
> > Turns out there's an appnote a lot like this. > >http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00119042.pdf
The appnote is ST's AN4507, about PWM dithering. They reference only one paper, by Angel Peterchev, who was a student engineer in my lab for a few years. Here's his 2001 PESC paper on DropBox. https://www.dropbox.com/s/2cfuk9aewgegb1r/Peterchev_Sanders_2001_pesc.pdf?dl=0 -- Thanks, - Win
John Larkin wrote...
> rickman wrote: >> John Larkin wrote:
>>> Right. Delta-sigma ADCs are astonishing. There's nothing that you can >>> afford that's anywhere close to as accurate and linear as they are. >> >> So what's so bad about a DS DAC? They can be had at up to 24 bits. > > Got any parts in mind? I need DC accuracy, and audio parts don't > generally guarantee that.
How about TI's DAC1220, 20-bits, 2ms to 0.012%, $9. -- Thanks, - Win
On Saturday, 30 May 2015 18:31:13 UTC+10, Jasen Betts  wrote:
> On 2015-05-30, Bill Sloman <bill.sloman@gmail.com> wrote: > as diagramming the transformation to make to the clock > >> my second column is the order the go into the comparitor > >> > >> > >> > My scheme was to reverse just the top four bits of the 10-bit counter output > >> > > >> > Counter Comparator > >> > > >> > 6 \ 10 > >> > 7 \ 9 > >> > 8 \ 8 > >> > 9 / 7 > >> > 10 / 6 > >> > 5 5 > >> > 4 4 > >> > 3 3 > >> > 2 2 > >> > 1 1 > >> > > >> > which gave 16x more transitions, and a well defined maximum transition rate. > >> > >> that looks like it would give mismatched pulse lengths: most of the of the 32 > >> slices would be either full or empty. > > > > Wrong. From 6.25% of full scale to 93.75% you end up with 16 segments whose lengths differ by no more than one interval. > > (you said 4 but then diagrammed 5 bits reversed, I'll go with 4 as > that's what you're discussing most recently)
<snip> Read the paper. We squeezed the process into a tiny programmable logic device - an ICT7024 - like it says in the paper, and it took Paul Buggs a couple of days to get it to fit. Since then it should have got a lot easier
> all the bit shuffling has me wondering about how a LFSR would > perform in this application, has anyone tried that?
It's not something where a linear feedback shift register would be any help at all, unless you wanted to do each of the comparisons involved in serial rather than parallel logic, and why would you bother? John Larkin wants to do a comparison every 50nsec on 20-bit long words, which would 2.5nsec per serial comparison - fine in ECLinPs, but much more expensive than programmable logic. -- Bill Sloman, Sydney
On 30 May 2015 04:56:48 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>John Larkin wrote... >> rickman wrote: >>> John Larkin wrote: > >>>> Right. Delta-sigma ADCs are astonishing. There's nothing that you can >>>> afford that's anywhere close to as accurate and linear as they are. >>> >>> So what's so bad about a DS DAC? They can be had at up to 24 bits. >> >> Got any parts in mind? I need DC accuracy, and audio parts don't >> generally guarantee that. > > How about TI's DAC1220, 20-bits, 2ms to 0.012%, $9.
That would probably work. It has the filter built-in, which is its main advantage. Performance-wise, it's about a tie with what I could do with PWM. It will need a triple or quad coupler, including the 2.5 MHz clock, no big deal. Too bad they didn't include an internal clock. The PWM thing would be about $7 cheaper per channel. You never know how many channels you're gonna sell. 100? 20000? -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Sunday, 31 May 2015 01:19:44 UTC+10, John Larkin  wrote:
> On 30 May 2015 04:56:48 -0700, Winfield Hill > <hill@rowland.harvard.edu> wrote: > > >John Larkin wrote... > >> rickman wrote: > >>> John Larkin wrote: > > > >>>> Right. Delta-sigma ADCs are astonishing. There's nothing that you can > >>>> afford that's anywhere close to as accurate and linear as they are. > >>> > >>> So what's so bad about a DS DAC? They can be had at up to 24 bits. > >> > >> Got any parts in mind? I need DC accuracy, and audio parts don't > >> generally guarantee that. > > > > How about TI's DAC1220, 20-bits, 2ms to 0.012%, $9. > > That would probably work. It has the filter built-in, which is its > main advantage. Performance-wise, it's about a tie with what I could > do with PWM.
Accuracy is remarkably good, but only after self-calibration. And - with my faith in TI - I'd worry that the calibration would only be good where it was easy to test.
> It will need a triple or quad coupler, including the 2.5 MHz clock, no > big deal. Too bad they didn't include an internal clock.
Tricky, when it has to communicate with the rest of the world over a serial line.
> The PWM thing would be about $7 cheaper per channel. You never know > how many channels you're gonna sell. 100? 20000?
It's not as if you spend a lot on development ... Our rule was never to develop what you could buy. There are better ways to keep engineers busy than re-inventing the wheel. -- Bill Sloman, Sydney --
On 5/30/2015 11:19 AM, John Larkin wrote:
> On 30 May 2015 04:56:48 -0700, Winfield Hill > <hill@rowland.harvard.edu> wrote: > >> John Larkin wrote... >>> rickman wrote: >>>> John Larkin wrote: >> >>>>> Right. Delta-sigma ADCs are astonishing. There's nothing that you can >>>>> afford that's anywhere close to as accurate and linear as they are. >>>> >>>> So what's so bad about a DS DAC? They can be had at up to 24 bits. >>> >>> Got any parts in mind? I need DC accuracy, and audio parts don't >>> generally guarantee that. >> >> How about TI's DAC1220, 20-bits, 2ms to 0.012%, $9. > > That would probably work. It has the filter built-in, which is its > main advantage. Performance-wise, it's about a tie with what I could > do with PWM. > > It will need a triple or quad coupler, including the 2.5 MHz clock, no > big deal. Too bad they didn't include an internal clock. > > The PWM thing would be about $7 cheaper per channel. You never know > how many channels you're gonna sell. 100? 20000?
The PWM will only be cheaper if you can get it to meet spec and the sales covers the NRE. Right now the NRE is an unknown quantity as is the sales volume it would seem. Then there is the opportunity cost of spending an unknown amount of time on developing the PWM approach, time you could spend on work with a known payoff. BTW, you don't need an opto for the clock. The TI part can work with a crystal although that's pretty much a wash in most regards. Also, you only need one additional opto for each additional channel since the interface has chip selects. So you need 2 or 3 + N optos, not much more than the PWM approach if you have multiple channels per unit. -- Rick
On Friday, May 29, 2015 at 1:20:19 AM UTC-4, John Larkin wrote:
> I need an isolated analog output (many of them, actually) with, say, 1 > PPM programmability and linearity. An optocoupled DAC would be silly, > so I'll use PWM. > > https://dl.dropboxusercontent.com/u/53724080/Circuits/PWM_WB_P470.JPG > > If I start at 200 MHz, and do a 20 bit (1 PPM) pwm, the output > frequency would be 200 Hz. If I use a 3-pole lowpass filter (not too > much delay) it has to be -3 dB at 2 Hz to get the ripple down to 1 > PPM. That's the n-squared dilemma of straight PWM. > > (Delta-sigma is noisy and has a lot of squirmy transitions. The > average value will be disturbed by the rise and fall times of the > optocoupler (or whatever) so getting to 1 PPM linearity is scary.) > > To make, say, 20% output, PWM would be (in decimal) 200000 clocks high > and 800000 clocks low. The ripple is 200 Hz. > > But we could break the 5 msec PWM interval into four chunks, 50000 > ticks high each, with the 800000 lows spread out between. That raises > the ripple frequency to 800 Hz, and the filter bandwidth can go up to > 8 Hz to maintain the 1 PPM ripple. Less delay. > > To increase the straight PWM output by 1 PPM, the ON time would > increase to 200001 ticks. In the boogered version, we'd generate > 50001, 50000, 50000, and 50000 highs. > > 200002 would translate to pulse widths of 50001, 50000, 50001 and > 50000 clocks. That balances the ripple. > > Turns out there's an appnote a lot like this. > > http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00119042.pdf > > An 8-fold booger is shown in Table 6. That would be nice, push my > ripple frequency up to 1600 Hz. There seems to be no resolution or > linearity penalty as long as I stay away from 0 and 100% duty cycle. > > ST was trying to get more resolution out of a fixed-length PWM > generator. In my FPGA, I can make any width PWM machine, but the trick > is used to push the ripple frequency up. > > Unlike true delta-sigma or PWM with a delta-sigma LSB dithering > scheme, this is totally deterministic, hence noise-free, excepting the > ripple. > > > -- > > John Larkin Highland Technology, Inc > picosecond timing laser drivers and controllers > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.com
Nice thread, I don't have anything to add. I wanted to check my understanding. You chop up the PWM finer to make the LP filter easier. There's some error with the turn-on and turn-off time asymmetry in the opto-isolator. So you keep the number of edges (chunks) fixed. (Hmm, could be other on-off timing errors too.) For accuracy it would be nice to have a symmetric opto-iso. George H.