Forums

goofy PWM

Started by John Larkin May 29, 2015
On Fri, 29 May 2015 14:27:10 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 05/29/2015 01:52 PM, rickman wrote: >> On 5/29/2015 12:49 PM, John Larkin wrote: >>> On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams" >>> <tiwill@seventransistorlabs.com> wrote: >>> >>>> Also, were you expecting anywhere near 0% or 100% duty? Obviously >>>> that's >>>> a problem for optos. You'll have to subtract some amount from each end >>>> (10-90% working range?), magnifying the juicy middle, and making it that >>>> much more critical to be linear and all that. >>>> >>>> Tim >>> >>> I'm willing to avoid small zones around 0 and 100%. >>> >>> In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC >>> to feed back the actual output voltage; we have some good reasons to >>> do that. But the ADC will be slow, so the PWM DAC not only needs to be >>> monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so >>> we can close the loop nicely. >>> >>> Having a very linear DAC is good, too. Once we know the DAC slope and >>> offset, easily measured at powerup, the convergence algorithm can >>> really rock. >> >> Rather than PWMing the whole thing and dealing with the issues, it can >> be done easily with a multiple DAC which can also be dithered to get the >> resolution you need. >> >> http://www.linear.com/product/LTC2656 >> >> 8 channels in one chip and one interface. Update at X times per second >> and Bob's your uncle. You might even be able to eliminate the ADC. >> > >1 ppm linearity might be a bit of a challenge, though. >
Right. Delta-sigma ADCs are astonishing. There's nothing that you can afford that's anywhere close to as accurate and linear as they are. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On 5/29/2015 2:50 PM, John Larkin wrote:
> On Fri, 29 May 2015 14:27:10 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 05/29/2015 01:52 PM, rickman wrote: >>> On 5/29/2015 12:49 PM, John Larkin wrote: >>>> On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams" >>>> <tiwill@seventransistorlabs.com> wrote: >>>> >>>>> Also, were you expecting anywhere near 0% or 100% duty? Obviously >>>>> that's >>>>> a problem for optos. You'll have to subtract some amount from each end >>>>> (10-90% working range?), magnifying the juicy middle, and making it that >>>>> much more critical to be linear and all that. >>>>> >>>>> Tim >>>> >>>> I'm willing to avoid small zones around 0 and 100%. >>>> >>>> In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC >>>> to feed back the actual output voltage; we have some good reasons to >>>> do that. But the ADC will be slow, so the PWM DAC not only needs to be >>>> monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so >>>> we can close the loop nicely. >>>> >>>> Having a very linear DAC is good, too. Once we know the DAC slope and >>>> offset, easily measured at powerup, the convergence algorithm can >>>> really rock. >>> >>> Rather than PWMing the whole thing and dealing with the issues, it can >>> be done easily with a multiple DAC which can also be dithered to get the >>> resolution you need. >>> >>> http://www.linear.com/product/LTC2656 >>> >>> 8 channels in one chip and one interface. Update at X times per second >>> and Bob's your uncle. You might even be able to eliminate the ADC. >>> >> >> 1 ppm linearity might be a bit of a challenge, though. >> > > Right. Delta-sigma ADCs are astonishing. There's nothing that you can > afford that's anywhere close to as accurate and linear as they are.
So what's so bad about a DS DAC? They can be had at up to 24 bits. -- Rick
On Fri, 29 May 2015 15:08:50 -0400, rickman <gnuarm@gmail.com> wrote:

>On 5/29/2015 2:50 PM, John Larkin wrote: >> On Fri, 29 May 2015 14:27:10 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 05/29/2015 01:52 PM, rickman wrote: >>>> On 5/29/2015 12:49 PM, John Larkin wrote: >>>>> On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams" >>>>> <tiwill@seventransistorlabs.com> wrote: >>>>> >>>>>> Also, were you expecting anywhere near 0% or 100% duty? Obviously >>>>>> that's >>>>>> a problem for optos. You'll have to subtract some amount from each end >>>>>> (10-90% working range?), magnifying the juicy middle, and making it that >>>>>> much more critical to be linear and all that. >>>>>> >>>>>> Tim >>>>> >>>>> I'm willing to avoid small zones around 0 and 100%. >>>>> >>>>> In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC >>>>> to feed back the actual output voltage; we have some good reasons to >>>>> do that. But the ADC will be slow, so the PWM DAC not only needs to be >>>>> monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so >>>>> we can close the loop nicely. >>>>> >>>>> Having a very linear DAC is good, too. Once we know the DAC slope and >>>>> offset, easily measured at powerup, the convergence algorithm can >>>>> really rock. >>>> >>>> Rather than PWMing the whole thing and dealing with the issues, it can >>>> be done easily with a multiple DAC which can also be dithered to get the >>>> resolution you need. >>>> >>>> http://www.linear.com/product/LTC2656 >>>> >>>> 8 channels in one chip and one interface. Update at X times per second >>>> and Bob's your uncle. You might even be able to eliminate the ADC. >>>> >>> >>> 1 ppm linearity might be a bit of a challenge, though. >>> >> >> Right. Delta-sigma ADCs are astonishing. There's nothing that you can >> afford that's anywhere close to as accurate and linear as they are. > >So what's so bad about a DS DAC? They can be had at up to 24 bits.
Got any parts in mind? I need DC accuracy, and audio parts don't generally guarantee that. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On 2015-05-29, John Larkin <jlarkin@highlandtechnology.com> wrote:
> On 29 May 2015 05:54:35 -0700, Winfield Hill ><hill@rowland.harvard.edu> wrote: > >>Bill Sloman wrote... >>> >>> John Larkin wrote: >>>> >>>> I need an isolated analog output (many of them, actually) >>>> with, say, 1 PPM programmability and linearity. An >>>> optocoupled DAC would be silly, so I'll use PWM. >> >>>> The average value will be disturbed by the rise and >>>> fall times of the optocoupler (or whatever) so >>>> getting to 1 PPM linearity is scary.) >>> >>> There are more sources of potential linearity error at >>> the 1ppm level than just differences between rise and >>> fall times. >> >> It's actually the overall ON vs OFF delay times, >> rather than rise time alone. The on vs off delays >> are often quite different for optical-couplers and >> drivers, but they're generally fairly stable and >> repeatable. It'd be easy to add adjustable fixed >> delays to both the on and off times, so they could >> be trimmed to be more or less the same. I'll bet >> a given choice of components in a production run >> would have pretty closely matched delays; measure >> one and apply the delay components to the rest. > > Yeah, the bottom line problem with D-S is on/off asymmetry, which > makes errors at high, and essentially random, pulse rates. But I > wouldn't want to attempt to tune it out. > > 1 0 1 0 has 8 edges, whereas 1 1 0 0 has only 4, so they won't > average the same. Delta-sigma generates too many cases. The IC boys > must do tricks to make D-S ICs as good as they are.
??? I count 4 and and 2 not 8 and 4
> The clustered/boogered PWM always has the same, small number of edges, > so will always be monotonic and noise-free. > > It's really not worth trying to de-cluster the wider pulses, ie > > 50001 50000 50001 50000 ON versus > 50001 50001 50000 50000 > > since the difference in ripple is a couple PPMs, and the lowpass > filter will kill that tiny residual ripple. > > There probably *is* some tricky math algorithm to evenly disperse the > N+1 pulses, some bit-field reversal or something, sort of a Van der > Corput sequence thing. My guys will get into that math fun, even if > it's unnecessary.
pure bit field reversal gives an effect a bit like a delta-sigma, most of the noise goes into the high frequencies but the number of transitions is variable. burkes dither used to convert photos one bit depth works like that. If you want a fixed number of transitions pick how many sub-fields you want in your modified PWM and then shift your counter output log_2 that many bits leftwards, reverse the order of the bits that overflowed and insert them into the vacated spots on the right, so for an n bit counter to be split into 8 n n-3 n-1 .... n-2 ----\ 3 n-3 \ 2 ... / 1 3 -----/ 0 2 n-2 1 n-1 0 n if the counter isn't a full binaary counter or you need a number of fields not a power of two, you'll have to use some other base, -- umop apisdn
John Larkin wrote...
> Winfield Hill wrote: >> Bill Sloman wrote... >>> John Larkin wrote: >>>> >>>> I need an isolated analog output (many of them, actually) >>>> with, say, 1 PPM programmability and linearity. An >>>> optocoupled DAC would be silly, so I'll use PWM. >>>> >>>> The average value will be disturbed by the rise and >>>> fall times of the optocoupler (or whatever) so >>>> getting to 1 PPM linearity is scary.) >>> >>> There are more sources of potential linearity error at >>> the 1ppm level than just differences between rise and >>> fall times. >> >> It's actually the overall ON vs OFF delay times, >> rather than rise time alone. The on vs off delays >> are often quite different for optical-couplers and >> drivers, but they're generally fairly stable and >> repeatable. It'd be easy to add adjustable fixed >> delays to both the on and off times, so they could >> be trimmed to be more or less the same. I'll bet >> a given choice of components in a production run >> would have pretty closely matched delays; measure >> one and apply the delay components to the rest. > > Yeah, the bottom line problem with D-S is on/off > asymmetry, which makes errors at high, and > essentially random, pulse rates. But I wouldn't > want to attempt to tune it out.
Whatever scheme you pick, you'd like to keep the total transitions/sec reasonably low, and the minimum transition period fairly long, much longer than ON and OFF time-delay differences. This means you can trim the delay times as needed, and easily pick up a 5-10x linearity improvement. I wouldn't call that tuning. -- Thanks, - Win
On 30/05/2015 9:20 AM, Jasen Betts wrote:
> On 2015-05-29, John Larkin <jlarkin@highlandtechnology.com> wrote: >> On 29 May 2015 05:54:35 -0700, Winfield Hill >> <hill@rowland.harvard.edu> wrote: >> >>> Bill Sloman wrote... >>>> >>>> John Larkin wrote: >>>>> >>>>> I need an isolated analog output (many of them, actually) >>>>> with, say, 1 PPM programmability and linearity. An >>>>> optocoupled DAC would be silly, so I'll use PWM. >>> >>>>> The average value will be disturbed by the rise and >>>>> fall times of the optocoupler (or whatever) so >>>>> getting to 1 PPM linearity is scary.) >>>> >>>> There are more sources of potential linearity error at >>>> the 1ppm level than just differences between rise and >>>> fall times. >>> >>> It's actually the overall ON vs OFF delay times, >>> rather than rise time alone. The on vs off delays >>> are often quite different for optical-couplers and >>> drivers, but they're generally fairly stable and >>> repeatable. It'd be easy to add adjustable fixed >>> delays to both the on and off times, so they could >>> be trimmed to be more or less the same. I'll bet >>> a given choice of components in a production run >>> would have pretty closely matched delays; measure >>> one and apply the delay components to the rest. >> >> Yeah, the bottom line problem with D-S is on/off asymmetry, which >> makes errors at high, and essentially random, pulse rates. But I >> wouldn't want to attempt to tune it out. >> >> 1 0 1 0 has 8 edges, whereas 1 1 0 0 has only 4, so they won't >> average the same. Delta-sigma generates too many cases. The IC boys >> must do tricks to make D-S ICs as good as they are. > > ??? I count 4 and and 2 not 8 and 4 > >> The clustered/boogered PWM always has the same, small number of edges, >> so will always be monotonic and noise-free. >> >> It's really not worth trying to de-cluster the wider pulses, ie >> >> 50001 50000 50001 50000 ON versus >> 50001 50001 50000 50000 >> >> since the difference in ripple is a couple PPMs, and the lowpass >> filter will kill that tiny residual ripple. >> >> There probably *is* some tricky math algorithm to evenly disperse the >> N+1 pulses, some bit-field reversal or something, sort of a Van der >> Corput sequence thing. My guys will get into that math fun, even if >> it's unnecessary. > > pure bit field reversal gives an effect a bit like a delta-sigma, most > of the noise goes into the high frequencies but the number of transitions > is variable. burkes dither used to convert photos one bit depth works > like that. > > If you want a fixed number of transitions > > pick how many sub-fields you want in your modified PWM and then > shift your counter output log_2 that many bits leftwards, reverse > the order of the bits that overflowed and insert them into the > vacated spots on the right, > > so for an n bit counter to be split into 8 > > n n-3 > n-1 .... > n-2 ----\ 3 > n-3 \ 2 > ... / 1 > 3 -----/ 0 > 2 n-2 > 1 n-1 > 0 n
My scheme was to reverse just the top four bits of the 10-bit counter output Counter Comparator 6 \ 10 7 \ 9 8 \ 8 9 / 7 10 / 6 5 5 4 4 3 3 2 2 1 1 which gave 16x more transitions, and a well defined maximum transition rate. John could presumably reverse the order of the top ten of his counter outputs for 1024 more transitions and the same maximum - 200kHz transition rate. -- Bill Sloman, Sydney
On 29 May 2015 18:10:58 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>John Larkin wrote... >> Winfield Hill wrote: >>> Bill Sloman wrote... >>>> John Larkin wrote: >>>>> >>>>> I need an isolated analog output (many of them, actually) >>>>> with, say, 1 PPM programmability and linearity. An >>>>> optocoupled DAC would be silly, so I'll use PWM. >>>>> >>>>> The average value will be disturbed by the rise and >>>>> fall times of the optocoupler (or whatever) so >>>>> getting to 1 PPM linearity is scary.) >>>> >>>> There are more sources of potential linearity error at >>>> the 1ppm level than just differences between rise and >>>> fall times. >>> >>> It's actually the overall ON vs OFF delay times, >>> rather than rise time alone. The on vs off delays >>> are often quite different for optical-couplers and >>> drivers, but they're generally fairly stable and >>> repeatable. It'd be easy to add adjustable fixed >>> delays to both the on and off times, so they could >>> be trimmed to be more or less the same. I'll bet >>> a given choice of components in a production run >>> would have pretty closely matched delays; measure >>> one and apply the delay components to the rest. >> >> Yeah, the bottom line problem with D-S is on/off >> asymmetry, which makes errors at high, and >> essentially random, pulse rates. But I wouldn't >> want to attempt to tune it out. > > Whatever scheme you pick, you'd like to keep the > total transitions/sec reasonably low, and the > minimum transition period fairly long, much > longer than ON and OFF time-delay differences. > > This means you can trim the delay times as needed, > and easily pick up a 5-10x linearity improvement. > I wouldn't call that tuning.
How would I trim the delay times? With plain or goofy PWM, there are only a few transitions per cycle, and any rise/fall asymmetry becomes a small, constant DC offset, independent of output value. My system will dynamically cal out any DC offset. Pulse width distortion shouldn't affect linearity. I'd probably use one of the ADUM1401A family of isolators. Pulse width distortion is 40 ns max, and 11 ps/degC typ. 200 MHz, 1e6 counts, 4 goofies per cycle, is an 800 Hz pulse train. The 40 ns delay distortion will add a tiny offset, way below what I'll see from opamps and such. I think it will work. I will have to test those ADUM parts for jitter. It's not actually specified. We stock the "A" grade parts, but the "B"s have lower PW distortion specs. TI has some nice isolators, 2.5 ns max PW distortion. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Saturday, 30 May 2015 11:46:19 UTC+10, John Larkin  wrote:
> On 29 May 2015 18:10:58 -0700, Winfield Hill > <hill@rowland.harvard.edu> wrote: > >John Larkin wrote... > >> Winfield Hill wrote: > >>> Bill Sloman wrote... > >>>> John Larkin wrote: > >>>>> > >>>>> I need an isolated analog output (many of them, actually) > >>>>> with, say, 1 PPM programmability and linearity. An > >>>>> optocoupled DAC would be silly, so I'll use PWM. > >>>>> > >>>>> The average value will be disturbed by the rise and > >>>>> fall times of the optocoupler (or whatever) so > >>>>> getting to 1 PPM linearity is scary.) > >>>> > >>>> There are more sources of potential linearity error at > >>>> the 1ppm level than just differences between rise and > >>>> fall times. > >>> > >>> It's actually the overall ON vs OFF delay times, > >>> rather than rise time alone. The on vs off delays > >>> are often quite different for optical-couplers and > >>> drivers, but they're generally fairly stable and > >>> repeatable. It'd be easy to add adjustable fixed > >>> delays to both the on and off times, so they could > >>> be trimmed to be more or less the same. I'll bet > >>> a given choice of components in a production run > >>> would have pretty closely matched delays; measure > >>> one and apply the delay components to the rest. > >> > >> Yeah, the bottom line problem with D-S is on/off > >> asymmetry, which makes errors at high, and > >> essentially random, pulse rates. But I wouldn't > >> want to attempt to tune it out. > > > > Whatever scheme you pick, you'd like to keep the > > total transitions/sec reasonably low, and the > > minimum transition period fairly long, much > > longer than ON and OFF time-delay differences. > > > > This means you can trim the delay times as needed, > > and easily pick up a 5-10x linearity improvement. > > I wouldn't call that tuning. > > How would I trim the delay times?
http://www.onsemi.com/pub_link/Collateral/MC10EP195-D.PDF working out how you'd find out what changes to make might be more difficult, but I've worked out schemes.
> With plain or goofy PWM, there are only a few transitions per cycle, > and any rise/fall asymmetry becomes a small, constant DC offset, > independent of output value. My system will dynamically cal out any DC > offset. Pulse width distortion shouldn't affect linearity.
With "goofy" - reduced ripple - PWM the number of transitions per cycle varies so the error ceases to be a DC offset. My scheme limited the number of transitions in my output to equal to or less than about 16 per cycle. If one applied something similar to your application you could have anything from two to 1024, through mostly you'd have 1024 - in the range from 0.1% to 99.9% of full scale.
> I'd probably use one of the ADUM1401A family of isolators. Pulse width > distortion is 40 ns max, and 11 ps/degC typ.
That doesn't take into account the differing rise and fall times on the switches doing the actual pulse width modulation, which does matter.
> 200 MHz, 1e6 counts, 4 goofies per cycle, is an 800 Hz pulse train. > The 40 ns delay distortion will add a tiny offset, way below what I'll > see from opamps and such. I think it will work. > > I will have to test those ADUM parts for jitter. It's not actually > specified. We stock the "A" grade parts, but the "B"s have lower PW > distortion specs. > > TI has some nice isolators, 2.5 ns max PW distortion.
If you just want precise isolation, a three-winding transformer can be difficult to beat - one high current winding is driven, one on the driven side is used to sense the rate of change of flux in the core as a voltage, and the third isolated winding on the other side generates exactly the same voltage - if it's wound bifilar with the other sense winding - to about one part in 10 million. There's a upper limit to the frequencies you can push across with that precision, but it beats the pants off 200Hz PWM. -- Bill Sloman, Sydney
On Saturday, 30 May 2015 05:57:29 UTC+10, John Larkin  wrote:
> On Fri, 29 May 2015 15:08:50 -0400, rickman <gnuarm@gmail.com> wrote: > > >On 5/29/2015 2:50 PM, John Larkin wrote: > >> On Fri, 29 May 2015 14:27:10 -0400, Phil Hobbs > >> <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> > >>> On 05/29/2015 01:52 PM, rickman wrote: > >>>> On 5/29/2015 12:49 PM, John Larkin wrote: > >>>>> On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams" > >>>>> <tiwill@seventransistorlabs.com> wrote: > >>>>> > >>>>>> Also, were you expecting anywhere near 0% or 100% duty? Obviously > >>>>>> that's > >>>>>> a problem for optos. You'll have to subtract some amount from each end > >>>>>> (10-90% working range?), magnifying the juicy middle, and making it that > >>>>>> much more critical to be linear and all that. > >>>>>> > >>>>>> Tim > >>>>> > >>>>> I'm willing to avoid small zones around 0 and 100%. > >>>>> > >>>>> In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC > >>>>> to feed back the actual output voltage; we have some good reasons to > >>>>> do that. But the ADC will be slow, so the PWM DAC not only needs to be > >>>>> monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so > >>>>> we can close the loop nicely. > >>>>> > >>>>> Having a very linear DAC is good, too. Once we know the DAC slope and > >>>>> offset, easily measured at powerup, the convergence algorithm can > >>>>> really rock. > >>>> > >>>> Rather than PWMing the whole thing and dealing with the issues, it can > >>>> be done easily with a multiple DAC which can also be dithered to get the > >>>> resolution you need. > >>>> > >>>> http://www.linear.com/product/LTC2656 > >>>> > >>>> 8 channels in one chip and one interface. Update at X times per second > >>>> and Bob's your uncle. You might even be able to eliminate the ADC. > >>>> > >>> > >>> 1 ppm linearity might be a bit of a challenge, though. > >>> > >> > >> Right. Delta-sigma ADCs are astonishing. There's nothing that you can > >> afford that's anywhere close to as accurate and linear as they are. > > > >So what's so bad about a DS DAC? They can be had at up to 24 bits. > > Got any parts in mind? I need DC accuracy, and audio parts don't > generally guarantee that.
http://www.ti.com/lit/ds/symlink/pcm1796.pdf It does have a guaranteed bipolar zero error at +/-2% of full scale, which isn't impressive for a 24-bit part. The +/-0.5% typical range isn't impressive either, but there is at least "a" guaranteed specification. Burr-Brown originally aimed the part at instrumentation applications as well as audio, and it shows in the data sheet. If you did your "goofy" PWM properly, you could do a lot better. -- Bill Sloman, Sydney
On 2015-05-30, Bill Sloman <bill.sloman@ieee.org> wrote:
> On 30/05/2015 9:20 AM, Jasen Betts wrote: >> On 2015-05-29, John Larkin <jlarkin@highlandtechnology.com> wrote: >>> On 29 May 2015 05:54:35 -0700, Winfield Hill >>> <hill@rowland.harvard.edu> wrote: >>> >>>> Bill Sloman wrote... >>>>> >>>>> John Larkin wrote: >>>>>> >>>>>> I need an isolated analog output (many of them, actually) >>>>>> with, say, 1 PPM programmability and linearity. An >>>>>> optocoupled DAC would be silly, so I'll use PWM. >>>> >>>>>> The average value will be disturbed by the rise and >>>>>> fall times of the optocoupler (or whatever) so >>>>>> getting to 1 PPM linearity is scary.) >>>>> >>>>> There are more sources of potential linearity error at >>>>> the 1ppm level than just differences between rise and >>>>> fall times. >>>> >>>> It's actually the overall ON vs OFF delay times, >>>> rather than rise time alone. The on vs off delays >>>> are often quite different for optical-couplers and >>>> drivers, but they're generally fairly stable and >>>> repeatable. It'd be easy to add adjustable fixed >>>> delays to both the on and off times, so they could >>>> be trimmed to be more or less the same. I'll bet >>>> a given choice of components in a production run >>>> would have pretty closely matched delays; measure >>>> one and apply the delay components to the rest. >>> >>> Yeah, the bottom line problem with D-S is on/off asymmetry, which >>> makes errors at high, and essentially random, pulse rates. But I >>> wouldn't want to attempt to tune it out. >>> >>> 1 0 1 0 has 8 edges, whereas 1 1 0 0 has only 4, so they won't >>> average the same. Delta-sigma generates too many cases. The IC boys >>> must do tricks to make D-S ICs as good as they are. >> >> ??? I count 4 and and 2 not 8 and 4 >> >>> The clustered/boogered PWM always has the same, small number of edges, >>> so will always be monotonic and noise-free. >>> >>> It's really not worth trying to de-cluster the wider pulses, ie >>> >>> 50001 50000 50001 50000 ON versus >>> 50001 50001 50000 50000 >>> >>> since the difference in ripple is a couple PPMs, and the lowpass >>> filter will kill that tiny residual ripple. >>> >>> There probably *is* some tricky math algorithm to evenly disperse the >>> N+1 pulses, some bit-field reversal or something, sort of a Van der >>> Corput sequence thing. My guys will get into that math fun, even if >>> it's unnecessary. >> >> pure bit field reversal gives an effect a bit like a delta-sigma, most >> of the noise goes into the high frequencies but the number of transitions >> is variable. burkes dither used to convert photos one bit depth works >> like that. >> >> If you want a fixed number of transitions >> >> pick how many sub-fields you want in your modified PWM and then >> shift your counter output log_2 that many bits leftwards, reverse >> the order of the bits that overflowed and insert them into the >> vacated spots on the right, >> >> so for an n bit counter to be split into 8 >> >>b n n-3 >> n-1 .... >> n-2 ----\ 3 >> n-3 \ 2 >> ... / 1 >> 3 -----/ 0 >> 2 n-2 >> 1 n-1 >> 0 n
I was diagramming the transformation to make to the clock my second column is the order the go into the comparitor
> My scheme was to reverse just the top four bits of the 10-bit counter output > > Counter Comparator > > 6 \ 10 > 7 \ 9 > 8 \ 8 > 9 / 7 > 10 / 6 > 5 5 > 4 4 > 3 3 > 2 2 > 1 1 > > which gave 16x more transitions, and a well defined maximum transition rate.
that looks like it would give mismatched pulse lengths: most of the of the 32 slices would be either full or empty. What I have done is reverse all the bits which gives maximum deterministic dither at the cost of an umpredictable number of edges per cycle, but then un-reverse the least-signifigant bits to limit the number of edges. so long as he programme input stays in the middle of of its range (does fill or empty all its high-order bits there will be a predictable number of transitions (2^(b+1)) for b bits moved. -- umop apisdn