# goofy PWM

Started by May 29, 2015
```
I need an isolated analog output (many of them, actually) with, say, 1
PPM programmability and linearity. An optocoupled DAC would be silly,
so I'll use PWM.

https://dl.dropboxusercontent.com/u/53724080/Circuits/PWM_WB_P470.JPG

If I start at 200 MHz, and do a 20 bit (1 PPM) pwm, the output
frequency would be 200 Hz. If I use a 3-pole lowpass filter (not too
much delay) it has to be -3 dB at 2 Hz to get the ripple down to 1
PPM. That's the n-squared dilemma of straight PWM.

(Delta-sigma is noisy and has a lot of squirmy transitions. The
average value will be disturbed by the rise and fall times of the
optocoupler (or whatever) so getting to 1 PPM linearity is scary.)

To make, say, 20% output, PWM would be (in decimal) 200000 clocks high
and 800000 clocks low. The ripple is 200 Hz.

But we could break the 5 msec PWM interval into four chunks, 50000
ticks high each, with the 800000 lows spread out between. That raises
the ripple frequency to 800 Hz, and the filter bandwidth can go up to
8 Hz to maintain the 1 PPM ripple. Less delay.

To increase the straight PWM output by 1 PPM, the ON time would
increase to 200001 ticks. In the boogered version, we'd generate
50001, 50000, 50000, and 50000 highs.

200002 would translate to pulse widths of 50001, 50000, 50001 and
50000 clocks. That balances the ripple.

Turns out there's an appnote a lot like this.

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00119042.pdf

An 8-fold booger is shown in Table 6. That would be nice, push my
ripple frequency up to 1600 Hz. There seems to be no resolution or
linearity penalty as long as I stay away from 0 and 100% duty cycle.

ST was trying to get more resolution out of a fixed-length PWM
generator. In my FPGA, I can make any width PWM machine, but the trick
is used to push the ripple frequency up.

Unlike true delta-sigma or PWM with a delta-sigma LSB dithering
scheme, this is totally deterministic, hence noise-free, excepting the
ripple.

--

John Larkin         Highland Technology, Inc
picosecond timing   laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

```
```On Friday, 29 May 2015 15:20:19 UTC+10, John Larkin  wrote:
> I need an isolated analog output (many of them, actually) with, say, 1
> PPM programmability and linearity. An optocoupled DAC would be silly,
> so I'll use PWM.
>
> https://dl.dropboxusercontent.com/u/53724080/Circuits/PWM_WB_P470.JPG
>
> If I start at 200 MHz, and do a 20 bit (1 PPM) pwm, the output
> frequency would be 200 Hz. If I use a 3-pole lowpass filter (not too
> much delay) it has to be -3 dB at 2 Hz to get the ripple down to 1
> PPM. That's the n-squared dilemma of straight PWM.

Check out

Sloman A.W., Buggs P., Molloy J., and Stewart D. "A microcontroller-based driver to stabilise the temperature of an optical stage to 1mK in the range 4C to 38C, using a Peltier heat pump and a thermistor sensor" Measurement Science and Technology, 7 1653-64 (1996)

I think I've sent you a copy - e-mail me if you can't find it.

It describes a dead simple technique for decreasing the worst case ripple on a PWM output. What it costs you is extra on-off transitions, which - if rise and fall times aren't equal - add to your non-linearity.

Basically, if you generate your PWM waveform by using a digital magnitude comparator to compare a fixed number - your PWM mark-to-period ratio - to the output of a counter, comparing from most-significant bit down to least significant bit minimises the number of transitions on the PWM output, while flipping from big-endian to little-endian on one or other maximiises the number of transitions. If you don't want too many transitions, just scramble the high order outputs from the counter. I swapped the top four, pushing my maximum transition rate from 17.4kHz to 278.4kHz which was the point at which my switching transistors started to run hotter. John could reverse the top twelve of his counter outputs before he hit 200kHz, and modern transistors can be switched faster before the switching losses get bigger than the static dissipation when "on".

> (Delta-sigma is noisy and has a lot of squirmy transitions.

Delta-sigma isn't "noisy". It pushes the switching noise up to higher frequencies, and introduces even more extra transitions than my approach - none of which are "squirmy" - whatever that might mean in this context.

>  The
> average value will be disturbed by the rise and fall times of the
> optocoupler (or whatever) so getting to 1 PPM linearity is scary.)

There are more sources of potential linearity error at the 1ppm level than just differences between rise and fall times.

> To make, say, 20% output, PWM would be (in decimal) 200000 clocks high
> and 800000 clocks low. The ripple is 200 Hz.
>
> But we could break the 5 msec PWM interval into four chunks, 50000
> ticks high each, with the 800000 lows spread out between. That raises
> the ripple frequency to 800 Hz, and the filter bandwidth can go up to
> 8 Hz to maintain the 1 PPM ripple. Less delay.

Not precisely. You still have to cope with the situation where one chunk is high for only 49999 ticks, while the others are high for 50000 ticks.

That's a 200Hz component, but you can organise things so that the worst case 200Hz component is a quarter the size it was with the simple minded approach. Check out my paper - it's spelled out there for 16 chunks, and the worst case over-all repetition rate component was then reduced by a factor of 16.

> To increase the straight PWM output by 1 PPM, the ON time would
> increase to 200001 ticks. In the boogered version, we'd generate
> 50001, 50000, 50000, and 50000 highs.
>
> 200002 would translate to pulse widths of 50001, 50000, 50001 and
> 50000 clocks. That balances the ripple.
>
> Turns out there's an appnote a lot like this.
>
> http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00119042.pdf

It's dated 2014, My paper is dated 1996 and I've talked about the approach here once or twice.

--
Bill Sloman, Sydney
```
```Bill Sloman wrote...
>
> John Larkin wrote:
>>
>> I need an isolated analog output (many of them, actually)
>> with, say, 1 PPM programmability and linearity.  An
>> optocoupled DAC would be silly, so I'll use PWM.

>> The average value will be disturbed by the rise and
>> fall times of the optocoupler (or whatever) so
>> getting to 1 PPM linearity is scary.)
>
> There are more sources of potential linearity error at
> the 1ppm level than just differences between rise and
> fall times.

It's actually the overall ON vs OFF delay times,
rather than rise time alone.  The on vs off delays
are often quite different for optical-couplers and
drivers, but they're generally fairly stable and
delays to both the on and off times, so they could
be trimmed to be more or less the same.  I'll bet
a given choice of components in a production run
would have pretty closely matched delays; measure
one and apply the delay components to the rest.

--
Thanks,
- Win
```
```On 29 May 2015 05:54:35 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>Bill Sloman wrote...
>>
>> John Larkin wrote:
>>>
>>> I need an isolated analog output (many of them, actually)
>>> with, say, 1 PPM programmability and linearity.  An
>>> optocoupled DAC would be silly, so I'll use PWM.
>
>>> The average value will be disturbed by the rise and
>>> fall times of the optocoupler (or whatever) so
>>> getting to 1 PPM linearity is scary.)
>>
>> There are more sources of potential linearity error at
>> the 1ppm level than just differences between rise and
>> fall times.
>
> It's actually the overall ON vs OFF delay times,
> rather than rise time alone.  The on vs off delays
> are often quite different for optical-couplers and
> drivers, but they're generally fairly stable and
> delays to both the on and off times, so they could
> be trimmed to be more or less the same.  I'll bet
> a given choice of components in a production run
> would have pretty closely matched delays; measure
> one and apply the delay components to the rest.

Yeah, the bottom line problem with D-S is on/off asymmetry, which
makes errors at high, and essentially random, pulse rates. But I
wouldn't want to attempt to tune it out.

1 0 1 0  has 8 edges, whereas 1 1 0 0 has only 4, so they won't
average the same. Delta-sigma generates too many cases. The IC boys
must do tricks to make D-S ICs as good as they are.

The clustered/boogered PWM always has the same, small number of edges,
so will always be monotonic and noise-free.

It's really not worth trying to de-cluster the wider pulses, ie

50001   50000  50001  50000     ON versus
50001   50001  50000  50000

since the difference in ripple is a couple PPMs, and the lowpass
filter will kill that tiny residual ripple.

There probably *is* some tricky math algorithm to evenly disperse the
N+1 pulses, some bit-field reversal or something, sort of a Van der
Corput sequence thing. My guys will get into that math fun, even if
it's unnecessary.

--

John Larkin         Highland Technology, Inc
picosecond timing   laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

```
```On Saturday, 30 May 2015 00:19:04 UTC+10, John Larkin  wrote:
> On 29 May 2015 05:54:35 -0700, Winfield Hill
> <hill@rowland.harvard.edu> wrote:
>
> >Bill Sloman wrote...
> >>
> >> John Larkin wrote:
> >>>
> >>> I need an isolated analog output (many of them, actually)
> >>> with, say, 1 PPM programmability and linearity.  An
> >>> optocoupled DAC would be silly, so I'll use PWM.
> >
> >>> The average value will be disturbed by the rise and
> >>> fall times of the optocoupler (or whatever) so
> >>> getting to 1 PPM linearity is scary.)
> >>
> >> There are more sources of potential linearity error at
> >> the 1ppm level than just differences between rise and
> >> fall times.
> >
> > It's actually the overall ON vs OFF delay times,
> > rather than rise time alone.  The on vs off delays
> > are often quite different for optical-couplers and
> > drivers, but they're generally fairly stable and
> > delays to both the on and off times, so they could
> > be trimmed to be more or less the same.  I'll bet
> > a given choice of components in a production run
> > would have pretty closely matched delays; measure
> > one and apply the delay components to the rest.
>
> Yeah, the bottom line problem with D-S is on/off asymmetry, which
> makes errors at high, and essentially random, pulse rates. But I
> wouldn't want to attempt to tune it out.
>
> 1 0 1 0  has 8 edges, whereas 1 1 0 0 has only 4, so they won't
> average the same. Delta-sigma generates too many cases. The IC boys
> must do tricks to make D-S ICs as good as they are.
>
> The clustered/boogered PWM always has the same, small number of edges,
> so will always be monotonic and noise-free.
>
> It's really not worth trying to de-cluster the wider pulses, ie
>
> 50001   50000  50001  50000     ON versus
> 50001   50001  50000  50000
>
> since the difference in ripple is a couple PPMs, and the lowpass
> filter will kill that tiny residual ripple.
>
> There probably *is* some tricky math algorithm to evenly disperse the
> N+1 pulses, some bit-field reversal or something, sort of a Van der
> Corput sequence thing. My guys will get into that math fun, even if
> it's unnecessary.

Reversing the order of the most significant bits of your counter output does it automatically - no math fun involved.

But you should have known that ...

--
Bill Sloman, Sydney
```
```You can use rational approximation to approach an arbitrary idealized
ratio.

Iterate until the denominator is greater than the maximum count length of
the register (i.e., 65536 for a 16-bit register; maybe you'd be limited by
output frequency instead for longer registers).  Stop and take the
preceeding pair.

While you're at it, check the ordinary N/MAXCOUNT ratio and see if it's
better.  If so, pick it.

As with D-S, the worst case ratio need not be any better than the ordinary
step size of the PWM register.  Indeed, this method is constructing the
sum of a D-S sequence, analytically rather than by feedback and time.

The results can be much better than N/MAXCOUNT in the general case.
(Which is more important, RMS or peak INL/DNL?)

You can also calculate step sizes by varying the denominator, as you
propose:
a / (b + epsilon) ~= (a - epsilon/b) / b

If you use this as a repeated increment to the register values, you'll
want to also apply some "negative feedback", such as a few iterations of
Newton's Method of approximating a function (perform that approximation
with extended precision, then truncate the fractions when complete, don't
just iterate on the integers).

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

"John Larkin" <jlarkin@highlandtechnology.com> wrote in message
>
>
> I need an isolated analog output (many of them, actually) with, say, 1
> PPM programmability and linearity. An optocoupled DAC would be silly,
> so I'll use PWM.
>
> https://dl.dropboxusercontent.com/u/53724080/Circuits/PWM_WB_P470.JPG
>
> If I start at 200 MHz, and do a 20 bit (1 PPM) pwm, the output
> frequency would be 200 Hz. If I use a 3-pole lowpass filter (not too
> much delay) it has to be -3 dB at 2 Hz to get the ripple down to 1
> PPM. That's the n-squared dilemma of straight PWM.
>
> (Delta-sigma is noisy and has a lot of squirmy transitions. The
> average value will be disturbed by the rise and fall times of the
> optocoupler (or whatever) so getting to 1 PPM linearity is scary.)
>
> To make, say, 20% output, PWM would be (in decimal) 200000 clocks high
> and 800000 clocks low. The ripple is 200 Hz.
>
> But we could break the 5 msec PWM interval into four chunks, 50000
> ticks high each, with the 800000 lows spread out between. That raises
> the ripple frequency to 800 Hz, and the filter bandwidth can go up to
> 8 Hz to maintain the 1 PPM ripple. Less delay.
>
> To increase the straight PWM output by 1 PPM, the ON time would
> increase to 200001 ticks. In the boogered version, we'd generate
> 50001, 50000, 50000, and 50000 highs.
>
> 200002 would translate to pulse widths of 50001, 50000, 50001 and
> 50000 clocks. That balances the ripple.
>
> Turns out there's an appnote a lot like this.
>
> http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00119042.pdf
>
> An 8-fold booger is shown in Table 6. That would be nice, push my
> ripple frequency up to 1600 Hz. There seems to be no resolution or
> linearity penalty as long as I stay away from 0 and 100% duty cycle.
>
> ST was trying to get more resolution out of a fixed-length PWM
> generator. In my FPGA, I can make any width PWM machine, but the trick
> is used to push the ripple frequency up.
>
> Unlike true delta-sigma or PWM with a delta-sigma LSB dithering
> scheme, this is totally deterministic, hence noise-free, excepting the
> ripple.
>
>
> --
>
> John Larkin         Highland Technology, Inc
> picosecond timing   laser drivers and controllers
>
> jlarkin att highlandtechnology dott com
> http://www.highlandtechnology.com
>

```
```Also, were you expecting anywhere near 0% or 100% duty?  Obviously that's
a problem for optos.  You'll have to subtract some amount from each end
(10-90% working range?), magnifying the juicy middle, and making it that
much more critical to be linear and all that.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

"John Larkin" <jlarkin@highlandtechnology.com> wrote in message
>
>
> I need an isolated analog output (many of them, actually) with, say, 1
> PPM programmability and linearity. An optocoupled DAC would be silly,
> so I'll use PWM.
>
> https://dl.dropboxusercontent.com/u/53724080/Circuits/PWM_WB_P470.JPG
>
> If I start at 200 MHz, and do a 20 bit (1 PPM) pwm, the output
> frequency would be 200 Hz. If I use a 3-pole lowpass filter (not too
> much delay) it has to be -3 dB at 2 Hz to get the ripple down to 1
> PPM. That's the n-squared dilemma of straight PWM.
>
> (Delta-sigma is noisy and has a lot of squirmy transitions. The
> average value will be disturbed by the rise and fall times of the
> optocoupler (or whatever) so getting to 1 PPM linearity is scary.)
>
> To make, say, 20% output, PWM would be (in decimal) 200000 clocks high
> and 800000 clocks low. The ripple is 200 Hz.
>
> But we could break the 5 msec PWM interval into four chunks, 50000
> ticks high each, with the 800000 lows spread out between. That raises
> the ripple frequency to 800 Hz, and the filter bandwidth can go up to
> 8 Hz to maintain the 1 PPM ripple. Less delay.
>
> To increase the straight PWM output by 1 PPM, the ON time would
> increase to 200001 ticks. In the boogered version, we'd generate
> 50001, 50000, 50000, and 50000 highs.
>
> 200002 would translate to pulse widths of 50001, 50000, 50001 and
> 50000 clocks. That balances the ripple.
>
> Turns out there's an appnote a lot like this.
>
> http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00119042.pdf
>
> An 8-fold booger is shown in Table 6. That would be nice, push my
> ripple frequency up to 1600 Hz. There seems to be no resolution or
> linearity penalty as long as I stay away from 0 and 100% duty cycle.
>
> ST was trying to get more resolution out of a fixed-length PWM
> generator. In my FPGA, I can make any width PWM machine, but the trick
> is used to push the ripple frequency up.
>
> Unlike true delta-sigma or PWM with a delta-sigma LSB dithering
> scheme, this is totally deterministic, hence noise-free, excepting the
> ripple.
>
>
> --
>
> John Larkin         Highland Technology, Inc
> picosecond timing   laser drivers and controllers
>
> jlarkin att highlandtechnology dott com
> http://www.highlandtechnology.com
>

```
```On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>Also, were you expecting anywhere near 0% or 100% duty?  Obviously that's
>a problem for optos.  You'll have to subtract some amount from each end
>(10-90% working range?), magnifying the juicy middle, and making it that
>much more critical to be linear and all that.
>
>Tim

I'm willing to avoid small zones around 0 and 100%.

In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC
to feed back the actual output voltage; we have some good reasons to
do that. But the ADC will be slow, so the PWM DAC not only needs to be
monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so
we can close the loop nicely.

Having a very linear DAC is good, too. Once we know the DAC slope and
offset, easily measured at powerup, the convergence algorithm can
really rock.

--

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

```
```On 5/29/2015 12:49 PM, John Larkin wrote:
> On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams"
> <tiwill@seventransistorlabs.com> wrote:
>
>> Also, were you expecting anywhere near 0% or 100% duty?  Obviously that's
>> a problem for optos.  You'll have to subtract some amount from each end
>> (10-90% working range?), magnifying the juicy middle, and making it that
>> much more critical to be linear and all that.
>>
>> Tim
>
> I'm willing to avoid small zones around 0 and 100%.
>
> In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC
> to feed back the actual output voltage; we have some good reasons to
> do that. But the ADC will be slow, so the PWM DAC not only needs to be
> monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so
> we can close the loop nicely.
>
> Having a very linear DAC is good, too. Once we know the DAC slope and
> offset, easily measured at powerup, the convergence algorithm can
> really rock.

Rather than PWMing the whole thing and dealing with the issues, it can
be done easily with a multiple DAC which can also be dithered to get the
resolution you need.

http://www.linear.com/product/LTC2656

8 channels in one chip and one interface.  Update at X times per second
and Bob's your uncle.  You might even be able to eliminate the ADC.

--

Rick
```
```On 05/29/2015 01:52 PM, rickman wrote:
> On 5/29/2015 12:49 PM, John Larkin wrote:
>> On Fri, 29 May 2015 11:44:50 -0500, "Tim Williams"
>> <tiwill@seventransistorlabs.com> wrote:
>>
>>> Also, were you expecting anywhere near 0% or 100% duty?  Obviously
>>> that's
>>> a problem for optos.  You'll have to subtract some amount from each end
>>> (10-90% working range?), magnifying the juicy middle, and making it that
>>> much more critical to be linear and all that.
>>>
>>> Tim
>>
>> I'm willing to avoid small zones around 0 and 100%.
>>
>> In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC
>> to feed back the actual output voltage; we have some good reasons to
>> do that. But the ADC will be slow, so the PWM DAC not only needs to be
>> monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so
>> we can close the loop nicely.
>>
>> Having a very linear DAC is good, too. Once we know the DAC slope and
>> offset, easily measured at powerup, the convergence algorithm can
>> really rock.
>
> Rather than PWMing the whole thing and dealing with the issues, it can
> be done easily with a multiple DAC which can also be dithered to get the
> resolution you need.
>
> http://www.linear.com/product/LTC2656
>
> 8 channels in one chip and one interface.  Update at X times per second
> and Bob's your uncle.  You might even be able to eliminate the ADC.
>

1 ppm linearity might be a bit of a challenge, though.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics