This model for a PMOSFET shows VTO=1.00. The data sheet shows VGS(th) as -1.0 to -0.45 volts. I'm guess these are two different specs? One is where the current is at a specified level and the other is where the current starts to change from the cut off condition? Here is the model for this part. *SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V 2.00A 0.150ohms Diodes Inc MOSFET .MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24 + PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m + IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p + CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u ) * -- Assumes default L=100U W=100U -- -- Rick
Is This Spice Model Accurate?
Started by ●December 20, 2014
Reply by ●December 21, 20142014-12-21
Ewww, LEVEL=1... Is it really worth simulating the thing? I mean, are you just using it as a switch or something? Might as well use a SPICE switch, plus a couple resistors and capacitors to crudely approximate the rise and fall time (if even those are at all important). Besides the shitty model, there's no [sufficiently nuanced] model of Cgd, or recovery, or package parasitics, or... If you do, well and truly, need to simulate this thing, to the level of having accurate transient analysis results, keep shopping and find one that is well specified and modeled. As for VTO, I would think that should be negative in keeping with convention, but maybe it's inverted in PMOS. I haven't looked at the exact definition (SPICE .MODEL definitions are the same for all flavors, so search for your favorite simulator's manual and look it up). Tim -- Seven Transistor Labs Electrical Engineering Consultation Website: http://seventransistorlabs.com "rickman" <gnuarm@gmail.com> wrote in message news:m75e1t$adp$1@dont-email.me...> This model for a PMOSFET shows VTO=1.00. The data sheet shows VGS(th) > as -1.0 to -0.45 volts. I'm guess these are two different specs? One > is where the current is at a specified level and the other is where the > current starts to change from the cut off condition? > > Here is the model for this part. > > *SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V 2.00A 0.150ohms Diodes > Inc MOSFET > .MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24 > + PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m > + IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p > + CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u ) > * -- Assumes default L=100U W=100U -- > > -- > > Rick
Reply by ●December 21, 20142014-12-21
On 12/20/2014 11:46 PM, Tim Williams wrote:> Ewww, LEVEL=1... > > Is it really worth simulating the thing? I mean, are you just using it as > a switch or something? Might as well use a SPICE switch, plus a couple > resistors and capacitors to crudely approximate the rise and fall time (if > even those are at all important). > > Besides the shitty model, there's no [sufficiently nuanced] model of Cgd, > or recovery, or package parasitics, or... > > If you do, well and truly, need to simulate this thing, to the level of > having accurate transient analysis results, keep shopping and find one > that is well specified and modeled. > > As for VTO, I would think that should be negative in keeping with > convention, but maybe it's inverted in PMOS. I haven't looked at the > exact definition (SPICE .MODEL definitions are the same for all flavors, > so search for your favorite simulator's manual and look it up).Thanks for the feedback, but for now I am stuck with this device until I can figure out what it is doing right and wrong. Actually, I think the Vto really is +1 volt. I simulated just the FET and it seems that the *cutoff* voltage, meaning the voltage where the current starts to increase simulates to +1 volt ballpark. As the gate gets more negative the channel resistance drops which is what a PMOS device should do, right? But the channel resistance never gets out of the Kohm range even with -10 volts on the gate, so something is wrong. The real problem is the circuit it is used in needs an NMOS FET but this device both simulates and works (according to the LT FAE) on their demo board. This is an LTC3109 low voltage boost switcher simulation which I had posted previously, but no one tried to run. The PMOS FETs were added to shut down the switcher by clamping the control input to ground. In order for the circuit to start up cold, the disable must be a high input and the enable must be a low on the input. The strange part is that the DMP2240 works! This is opposite how a PMOS FET should work so I have to assume this is working correctly because of parasitic effects. To top it off I can't get any MOSFET of either polarity to work when I change the circuit to the auto-polarity mode which is what I need. I noticed that in the simulation when the control input is clamped to ground by a FET, since the FET still has a finite resistance there is still some voltage on the drain when on. It seems the LTC3109 control input switches when the control input is at 0 volts so the thing will still oscillate. If the FETs are turned off while the AC signal is positive that charge gets trapped on the control node biasing it enough that the small control voltage swing won't trigger the switches! So because of the parasitics the PMOS device works oppositely from what it should. I can get the circuit to work somewhat with a FDC637AN NMOS FET, but because of the trapped charge issue it won't restart reliably. I suppose in the real world that charge will leak off in a few seconds to let it run. This is a circuit that will be running for minutes and hours to get enough power to run the app so a few seconds of lost power is not a real issue. But I just don't have any confidence this will work reliably. Does this make any sense? I'm having a hard time finding any sense in it. -- Rick
Reply by ●December 22, 20142014-12-22
"rickman" wrote in message news:m75e1t$adp$1@dont-email.me...>This model for a PMOSFET shows VTO=1.00. The data sheet shows VGS(th) >as -1.0 to -0.45 volts. I'm guess these are two different specs? One is >where the current is at a specified level and the other is where the >current starts to change from the cut off condition?>Here is the model for this part.>*SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V 2.00A 0.150ohms Diodes Inc >MOSFET >.MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24 >+ PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m >+ IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p >+ CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u ) >* -- Assumes default L=100U W=100U -- >But the channel resistance never gets out of the Kohm range even with -10 >volts on the gate, so something is wrong.Well, I ran the graphs on it in SuperSpice, and no, the model is not correct. For W/L =1 it should be: Id = kp * Vgst * Vgst From inspection, at a Vgs= 5V, its (5V- 1V) for a Vgst=4V, it would be only 11.9u * 16 = 190ua What I would say though, is that LTSpice is a real pain if you want to actually get behaviour over worst case process corners. e.g. Vt being 4V or 2v. http://www.anasoft.co.uk/images/worst_case.png Kevin Aylward www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
Reply by ●December 22, 20142014-12-22
On Mon, 22 Dec 2014 20:21:26 -0000, "Kevin Aylward" <ExtractkevinRemove@kevinaylward.co.uk> wrote:>"rickman" wrote in message news:m75e1t$adp$1@dont-email.me... > >>This model for a PMOSFET shows VTO=1.00. The data sheet shows VGS(th) >>as -1.0 to -0.45 volts. I'm guess these are two different specs? One is >>where the current is at a specified level and the other is where the >>current starts to change from the cut off condition? > >>Here is the model for this part. > >>*SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V 2.00A 0.150ohms Diodes Inc >>MOSFET >>.MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24 >>+ PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m >>+ IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p >>+ CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u ) >>* -- Assumes default L=100U W=100U -- >>But the channel resistance never gets out of the Kohm range even with -10 >>volts on the gate, so something is wrong. > >Well, I ran the graphs on it in SuperSpice, and no, the model is not >correct. > >For W/L =1 it should be: > >Id = kp * Vgst * Vgst > >From inspection, at a Vgs= 5V, its (5V- 1V) for a Vgst=4V, it would be only >11.9u * 16 = 190ua > >What I would say though, is that LTSpice is a real pain if you want to >actually get behaviour over worst case process corners. e.g. Vt being 4V or >2v. > >http://www.anasoft.co.uk/images/worst_case.png > >Kevin Aylward >www.kevinaylward.co.uk >www.anasoft.co.uk - SuperSpiceI just fit a high level chip model (Level=48 or some such BSIM3 or BSIM4) to the discrete data sheet ;-) LTspice tends to be behavioral, which often doesn't lend itself to corner checking.) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●December 22, 20142014-12-22
On Monday, December 22, 2014 7:24:38 PM UTC-5, Jim Thompson wrote:> On Mon, 22 Dec 2014 20:21:26 -0000, "Kevin Aylward" > <ExtractkevinRemove@kevinaylward.co.uk> wrote: >=20 > >"rickman" wrote in message news:m75e1t$adp$1@dont-email.me... > > > >>This model for a PMOSFET shows VTO=3D1.00. The data sheet shows VGS(th=)=20> >>as -1.0 to -0.45 volts. I'm guess these are two different specs? One =is=20> >>where the current is at a specified level and the other is where the=20 > >>current starts to change from the cut off condition? > > > >>Here is the model for this part. > > > >>*SRC=3DDMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V 2.00A 0.150ohms Diod=es Inc=20> >>MOSFET > >>.MODEL DI_DMP2240UDM PMOS( LEVEL=3D1 VTO=3D1.00 KP=3D11.9u GAMMA=3D1.=24> >>+ PHI=3D.75 LAMBDA=3D514u RD=3D21.0m RS=3D21.0m > >>+ IS=3D1.00p PB=3D0.800 MJ=3D0.460 CBD=3D81.1p > >>+ CBS=3D97.4p CGSO=3D720n CGDO=3D600n CGBO=3D1.88u ) > >>* -- Assumes default L=3D100U W=3D100U -- > >>But the channel resistance never gets out of the Kohm range even with -=10=20> >>volts on the gate, so something is wrong. > > > >Well, I ran the graphs on it in SuperSpice, and no, the model is not=20 > >correct. > > > >For W/L =3D1 it should be: > > > >Id =3D kp * Vgst * Vgst > > > >From inspection, at a Vgs=3D 5V, its (5V- 1V) for a Vgst=3D4V, it would =be only=20> >11.9u * 16 =3D 190ua > > > >What I would say though, is that LTSpice is a real pain if you want to==20> >actually get behaviour over worst case process corners. e.g. Vt being 4V=or=20> >2v. > > > >http://www.anasoft.co.uk/images/worst_case.png > > > >Kevin Aylward > >www.kevinaylward.co.uk > >www.anasoft.co.uk - SuperSpice=20 >=20 > I just fit a high level chip model (Level=3D48 or some such BSIM3 or > BSIM4) to the discrete data sheet ;-) >=20 > LTspice tends to be behavioral, which often doesn't lend itself to > corner checking.)I'm not trying to do corner checking or anything fancy. I want to use the = LTC3109 to power a small receiver. But it is a switcher and the noise it g= enerates would likely swamp out the signal to be received. So I want to tu= rn it off and run from battery/caps while receiving. I asked the FAE what = they suggested and they gave me a circuit that simulates fine and runs on a= modified demo board. But it used PMOS FETs which *should* have the wrong = polarity for the control so that it would never start up cold (no voltage o= n the caps). But for some reason the circuit *works* with the disable high= and enable low. =20 So I am trying to understand what the F...FET is going on with this thing. = It is hard to tell the FAE his circuit is goofy when it works. Since they= have a demo board working with this mod I would run with it and prototype,= but they used two TEGs on the input rather than the one TEG auto-polarity = circuit the chip is touted as supporting. When I make that change to the s= imulation, the FETs stop working right.=20 I plotted Vd/Id in spice and get 5 kohms with Vgs =3D -10 volts. That seem= s a bit high for a part that is supposed to be in the milliohm range.=20 I've tried changing to NMOS FETs since that is what I would expect work the= way I need it, but they don't work a lot better in simulation.=20 Rick
Reply by ●December 23, 20142014-12-23
>"Jim Thompson" wrote in message >news:vddh9a1uvqg7luh64524bbuh7u84rt8hp7@4ax.com...>I just fit a high level chip model (Level=48 or some such BSIM3 or >BSIM4) to the discrete data sheet ;-)>LTspice tends to be behavioral, which often doesn't lend itself to >corner checking.)As far as published stuff goes, LTSpice has, essentially, zero support for WC. This makes LTSPice, essentially, useless for serious *simulation* based *design*. I found some references where people were piddling about to get the feature, e.g. http://k6jca.blogspot.co.uk/2012/07/monte-carlo-and-worst-case-circuit.html Like, every component has to be set up with {expressions} type stuff, so its truly a non starter. What I find strange is, why doesn't LTSPice have WC support? I had this idea that LTSpice grew out of a tool they used internally for IC design, and then decided to give it way as a marketing gimmick. Many companies developed their own Spice's before the Cadence and Mentor came along. If so, I would have guessed that there would be some sort of Rerun support, say a file where you could list model includes to be used on each auto run. I haven't found any documentation that says this is the case though. As we noted prior, I don't really use MC, but I did recently add full support for this in SS. Its just a button press. I also added in VBIC support, finally. Kevin Aylward www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
Reply by ●December 23, 20142014-12-23
On Tue, 23 Dec 2014 13:41:28 -0000, "Kevin Aylward" <ExtractkevinRemove@kevinaylward.co.uk> wrote:>>"Jim Thompson" wrote in message >>news:vddh9a1uvqg7luh64524bbuh7u84rt8hp7@4ax.com... > > >>I just fit a high level chip model (Level=48 or some such BSIM3 or >>BSIM4) to the discrete data sheet ;-) > >>LTspice tends to be behavioral, which often doesn't lend itself to >>corner checking.) > >As far as published stuff goes, LTSpice has, essentially, zero support for >WC. This makes LTSPice, essentially, useless for serious *simulation* based >*design*. I found some references where people were piddling about to get >the feature, e.g. > >http://k6jca.blogspot.co.uk/2012/07/monte-carlo-and-worst-case-circuit.html > >Like, every component has to be set up with {expressions} type stuff, so its >truly a non starter. > >What I find strange is, why doesn't LTSPice have WC support? I had this idea >that LTSpice grew out of a tool they used internally for IC design, and then >decided to give it way as a marketing gimmick. Many companies developed >their own Spice's before the Cadence and Mentor came along. If so, I would >have guessed that there would be some sort of Rerun support, say a file >where you could list model includes to be used on each auto run. I haven't >found any documentation that says this is the case though. > >As we noted prior, I don't really use MC, but I did recently add full >support for this in SS. Its just a button press. I also added in VBIC >support, finally. > >Kevin Aylward >www.kevinaylward.co.uk >www.anasoft.co.uk - SuperSpiceI don't do Monte Carlo either... AFAIK it's only useful for discrete designs. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●December 23, 20142014-12-23
On 12/23/2014 8:41 AM, Kevin Aylward wrote:>> "Jim Thompson" wrote in message >> news:vddh9a1uvqg7luh64524bbuh7u84rt8hp7@4ax.com... > > >> I just fit a high level chip model (Level=48 or some such BSIM3 or >> BSIM4) to the discrete data sheet ;-) > >> LTspice tends to be behavioral, which often doesn't lend itself to >> corner checking.) > > As far as published stuff goes, LTSpice has, essentially, zero support > for WC.LTSpice has zero support for water closets??? :(> This makes LTSPice, essentially, useless for serious > *simulation* based *design*. I found some references where people were > piddling about to get the feature, e.g. > > http://k6jca.blogspot.co.uk/2012/07/monte-carlo-and-worst-case-circuit.html > > Like, every component has to be set up with {expressions} type stuff, so > its truly a non starter. > > What I find strange is, why doesn't LTSPice have WC support? I had this > idea that LTSpice grew out of a tool they used internally for IC design, > and then decided to give it way as a marketing gimmick. Many companies > developed their own Spice's before the Cadence and Mentor came along. If > so, I would have guessed that there would be some sort of Rerun support, > say a file where you could list model includes to be used on each auto > run. I haven't found any documentation that says this is the case though. > > As we noted prior, I don't really use MC, but I did recently add full > support for this in SS. Its just a button press. I also added in VBIC > support, finally. > > Kevin Aylward > www.kevinaylward.co.uk > www.anasoft.co.uk - SuperSpice-- Rick
Reply by ●December 23, 20142014-12-23
"rickman" wrote in message news:m7c2hv$kfr$1@dont-email.me... On 12/23/2014 8:41 AM, Kevin Aylward wrote:>> "Jim Thompson" wrote in message >> news:vddh9a1uvqg7luh64524bbuh7u84rt8hp7@4ax.com... > > >> I just fit a high level chip model (Level=48 or some such BSIM3 or >> BSIM4) to the discrete data sheet ;-) > >>> LTspice tends to be behavioral, which often doesn't lend itself to >>> corner checking.) > >> As far as published stuff goes, LTSpice has, essentially, zero support >> for WC.>LTSpice has zero support for water closets??? :(Assuming that's' a genuine ??? WC = Worst Case http://www.anasoft.co.uk/worstcase.htm No ic company will send a chip to fab without extensive WC simulation. Kevin Aylward www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
